llvm.org GIT mirror llvm / 521804a
Move ARM subreg index compositions to the SubRegIndex itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149557 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 7 years ago
1 changed file(s) with 24 addition(s) and 30 deletion(s). Raw diff Collapse all Expand all
2626
2727 // Subregister indices.
2828 let Namespace = "ARM" in {
29 def qqsub_0 : SubRegIndex;
30 def qqsub_1 : SubRegIndex;
31
2932 // Note: Code depends on these having consecutive numbers.
33 def qsub_0 : SubRegIndex;
34 def qsub_1 : SubRegIndex;
35 def qsub_2 : SubRegIndex<[qqsub_1, qsub_0]>;
36 def qsub_3 : SubRegIndex<[qqsub_1, qsub_1]>;
37
38 def dsub_0 : SubRegIndex;
39 def dsub_1 : SubRegIndex;
40 def dsub_2 : SubRegIndex<[qsub_1, dsub_0]>;
41 def dsub_3 : SubRegIndex<[qsub_1, dsub_1]>;
42 def dsub_4 : SubRegIndex<[qsub_2, dsub_0]>;
43 def dsub_5 : SubRegIndex<[qsub_2, dsub_1]>;
44 def dsub_6 : SubRegIndex<[qsub_3, dsub_0]>;
45 def dsub_7 : SubRegIndex<[qsub_3, dsub_1]>;
46
3047 def ssub_0 : SubRegIndex;
3148 def ssub_1 : SubRegIndex;
32 def ssub_2 : SubRegIndex; // In a Q reg.
33 def ssub_3 : SubRegIndex;
34
35 def dsub_0 : SubRegIndex;
36 def dsub_1 : SubRegIndex;
37 def dsub_2 : SubRegIndex;
38 def dsub_3 : SubRegIndex;
39 def dsub_4 : SubRegIndex;
40 def dsub_5 : SubRegIndex;
41 def dsub_6 : SubRegIndex;
42 def dsub_7 : SubRegIndex;
43
44 def qsub_0 : SubRegIndex;
45 def qsub_1 : SubRegIndex;
46 def qsub_2 : SubRegIndex;
47 def qsub_3 : SubRegIndex;
48
49 def qqsub_0 : SubRegIndex;
50 def qqsub_1 : SubRegIndex;
49 def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
50 def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;
51 // Let TableGen synthesize the remaining 12 ssub_* indices.
52 // We don't need to name them.
5153 }
5254
5355 // Integer registers
128130 def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>;
129131
130132 // Advanced SIMD (NEON) defines 16 quad-word aliases
131 let SubRegIndices = [dsub_0, dsub_1],
132 CompositeIndices = [(ssub_2 dsub_1, ssub_0),
133 (ssub_3 dsub_1, ssub_1)] in {
133 let SubRegIndices = [dsub_0, dsub_1] in {
134134 def Q0 : ARMReg< 0, "q0", [D0, D1]>;
135135 def Q1 : ARMReg< 1, "q1", [D2, D3]>;
136136 def Q2 : ARMReg< 2, "q2", [D4, D5]>;
296296 // stuff very messy.
297297 def Tuples2Q : RegisterTuples<[qsub_0, qsub_1],
298298 [(decimate QPR, 2),
299 (decimate (shl QPR, 1), 2)]> {
300 let CompositeIndices = [(dsub_2 qsub_1, dsub_0), (dsub_3 qsub_1, dsub_1)];
301 }
299 (decimate (shl QPR, 1), 2)]>;
302300
303301 // Pseudo 256-bit vector register class to model pairs of Q registers
304302 // (4 consecutive D registers).
313311 // Pseudo 512-bit registers to represent four consecutive Q registers.
314312 def Tuples2QQ : RegisterTuples<[qqsub_0, qqsub_1],
315313 [(decimate QQPR, 2),
316 (decimate (shl QQPR, 1), 2)]> {
317 let CompositeIndices = [(qsub_2 qqsub_1, qsub_0), (qsub_3 qqsub_1, qsub_1),
318 (dsub_4 qqsub_1, dsub_0), (dsub_5 qqsub_1, dsub_1),
319 (dsub_6 qqsub_1, dsub_2), (dsub_7 qqsub_1, dsub_3)];
320 }
314 (decimate (shl QQPR, 1), 2)]>;
321315
322316 // Pseudo 512-bit vector register class to model 4 consecutive Q registers
323317 // (8 consecutive D registers).