llvm.org GIT mirror llvm / 51fa1bc
Allow AVX vrsqrtps generation. This is a follow-on to r220570 that allows a 256-bit (v8f32) version of vrsqrtps to be generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220579 91177308-0d34-0410-b5e6-96231b3b80d8 Sanjay Patel 5 years ago
2 changed file(s) with 30 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
1438214382 EVT VT = Op.getValueType();
1438314383
1438414384 // SSE1 has rsqrtss and rsqrtps.
14385 // TODO: Add support for AVX (v8f32) and AVX512 (v16f32).
14385 // TODO: Add support for AVX512 (v16f32).
1438614386 // It is likely not profitable to do this for f64 because a double-precision
1438714387 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
1438814388 // instructions: convert to single, rsqrtss, convert back to double, refine
1438914389 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
1439014390 // along with FMA, this could be a throughput win.
14391 if (Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) {
14391 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14392 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
1439214393 RefinementSteps = 1;
1439314394 UseOneConstNR = false;
1439414395 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
5454
5555 declare x86_fp80 @__sqrtl_finite(x86_fp80) #1
5656
57 declare float @llvm.sqrt.f32(float) #1
58 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
59 declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) #1
60
5761 ; If the target's sqrtss and divss instructions are substantially
5862 ; slower than rsqrtss with a Newton-Raphson refinement, we should
5963 ; generate the estimate sequence.
64
6065 define float @reciprocal_square_root(float %x) #0 {
6166 %sqrt = tail call float @llvm.sqrt.f32(float %x)
6267 %div = fdiv fast float 1.0, %sqrt
7782 ; BTVER2-NEXT: retq
7883 }
7984
80 declare float @llvm.sqrt.f32(float) #1
81
82 ; If the target's sqrtps and divps instructions are substantially
83 ; slower than rsqrtps with a Newton-Raphson refinement, we should
84 ; generate the estimate sequence.
8585 define <4 x float> @reciprocal_square_root_v4f32(<4 x float> %x) #0 {
8686 %sqrt = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
8787 %div = fdiv fast <4 x float> , %sqrt
102102 ; BTVER2-NEXT: retq
103103 }
104104
105 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
105 define <8 x float> @reciprocal_square_root_v8f32(<8 x float> %x) #0 {
106 %sqrt = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> %x)
107 %div = fdiv fast <8 x float> , %sqrt
108 ret <8 x float> %div
109
110 ; CHECK-LABEL: reciprocal_square_root_v8f32:
111 ; CHECK: sqrtps
112 ; CHECK-NEXT: sqrtps
113 ; CHECK-NEXT: movaps
114 ; CHECK-NEXT: movaps
115 ; CHECK-NEXT: divps
116 ; CHECK-NEXT: divps
117 ; CHECK-NEXT: retq
118 ; BTVER2-LABEL: reciprocal_square_root_v8f32:
119 ; BTVER2: vrsqrtps
120 ; BTVER2-NEXT: vmulps
121 ; BTVER2-NEXT: vmulps
122 ; BTVER2-NEXT: vmulps
123 ; BTVER2-NEXT: vaddps
124 ; BTVER2-NEXT: vmulps
125 ; BTVER2-NEXT: retq
126 }
106127
107128
108129 attributes #0 = { nounwind readnone uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" "use-soft-float"="false" }