llvm.org GIT mirror llvm / 51f0596
[X86] Remove duplicate instructions for (v)movq and replace with patterns on other instructions. NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287519 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 3 years ago
2 changed file(s) with 10 addition(s) and 29 deletion(s). Raw diff Collapse all Expand all
10191019 LLVM_FALLTHROUGH;
10201020
10211021 case X86::MOVQI2PQIrm:
1022 case X86::MOVZQI2PQIrm:
10231022 case X86::MOVZPQILo2PQIrm:
10241023 case X86::VMOVQI2PQIrm:
10251024 case X86::VMOVQI2PQIZrm:
1026 case X86::VMOVZQI2PQIrm:
10271025 case X86::VMOVZPQILo2PQIrm:
10281026 case X86::VMOVZPQILo2PQIZrm:
10291027 DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
49014901 def : InstAlias<"vmovq\t{$src, $dst|$dst, $src}",
49024902 (VMOVPQI2QIrr VR128L:$dst, VR128H:$src), 0>;
49034903
4904 //===---------------------------------------------------------------------===//
4905 // Store / copy lower 64-bits of a XMM register.
4906 //
4907 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, AddedComplexity = 20 in {
4908 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4909 "vmovq\t{$src, $dst|$dst, $src}",
4910 [(set VR128:$dst,
4911 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4912 (loadi64 addr:$src))))))],
4913 IIC_SSE_MOVDQ>,
4914 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
4915
4916 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4917 "movq\t{$src, $dst|$dst, $src}",
4918 [(set VR128:$dst,
4919 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4920 (loadi64 addr:$src))))))],
4921 IIC_SSE_MOVDQ>,
4922 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
4923 } // ExeDomain, isCodeGenOnly, AddedComplexity
4924
49254904 let Predicates = [UseAVX], AddedComplexity = 20 in {
4905 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4906 (VMOVQI2PQIrm addr:$src)>;
49264907 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4927 (VMOVZQI2PQIrm addr:$src)>;
4908 (VMOVQI2PQIrm addr:$src)>;
49284909 def : Pat<(v2i64 (X86vzload addr:$src)),
4929 (VMOVZQI2PQIrm addr:$src)>;
4910 (VMOVQI2PQIrm addr:$src)>;
49304911 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
49314912 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
4932 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
4913 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIrm addr:$src), sub_xmm)>;
49334914 def : Pat<(v4i64 (X86vzload addr:$src)),
4934 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
4915 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIrm addr:$src), sub_xmm)>;
49354916 }
49364917
49374918 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4919 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4920 (MOVQI2PQIrm addr:$src)>;
49384921 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4939 (MOVZQI2PQIrm addr:$src)>;
4940 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4922 (MOVQI2PQIrm addr:$src)>;
4923 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVQI2PQIrm addr:$src)>;
49414924 }
49424925
49434926 //===---------------------------------------------------------------------===//