llvm.org GIT mirror llvm / 51cd16c
[x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199807 91177308-0d34-0410-b5e6-96231b3b80d8 David Woodhouse 6 years ago
6 changed file(s) with 54 addition(s) and 31 deletion(s). Raw diff Collapse all Expand all
23572357 }
23582358 }
23592359
2360 // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
2361 if (Name.startswith("movs") && Operands.size() == 3 &&
2362 (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
2363 (is64BitMode() && Name == "movsq"))) {
2364 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2365 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2366 if (isSrcOp(Op) && isDstOp(Op2)) {
2367 Operands.pop_back();
2368 Operands.pop_back();
2369 delete &Op;
2370 delete &Op2;
2371 }
2372 }
23732360 // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
23742361 // values of $SIREG according to the mode. It would be nice if this
23752362 // could be achieved with InstAlias in the tables.
24052392 } else {
24062393 Operands.push_back(DefaultMemDIOperand(NameLoc));
24072394 Operands.push_back(DefaultMemSIOperand(NameLoc));
2395 }
2396 } else if (Operands.size() == 3) {
2397 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2398 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2399 if (!doSrcDstMatch(Op, Op2))
2400 return Error(Op.getStartLoc(),
2401 "mismatching source and destination index registers");
2402 }
2403 }
2404
2405 // Add default SI and DI operands to "movs[bwlq]".
2406 if ((Name.startswith("movs") &&
2407 (Name == "movs" || Name == "movsb" || Name == "movsw" ||
2408 Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
2409 (Name.startswith("smov") &&
2410 (Name == "smov" || Name == "smovb" || Name == "smovw" ||
2411 Name == "smovl" || Name == "smovd" || Name == "smovq"))) {
2412 if (Operands.size() == 1) {
2413 if (Name == "movsd")
2414 Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
2415 if (isParsingIntelSyntax()) {
2416 Operands.push_back(DefaultMemDIOperand(NameLoc));
2417 Operands.push_back(DefaultMemSIOperand(NameLoc));
2418 } else {
2419 Operands.push_back(DefaultMemSIOperand(NameLoc));
2420 Operands.push_back(DefaultMemDIOperand(NameLoc));
24082421 }
24092422 } else if (Operands.size() == 3) {
24102423 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
11361136 let SchedRW = [WriteMicrocoded] in {
11371137 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
11381138 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1139 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
1140 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
1141 def MOVSL : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>, OpSize16;
1142 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
1139 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1140 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1141 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1142 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize;
1143 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1144 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1145 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1146 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
11431147 }
11441148
11451149 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
25922596 def : InstAlias<"movq $src, $dst",
25932597 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
25942598
2595 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
2596 // alias for movsl. (as in rep; movsd)
2597 def : InstAlias<"movsd", (MOVSL), 0>;
2598
25992599 // movsx aliases
26002600 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
26012601 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
118118 // 64: cmpsq %es:(%rdi), (%rsi) # encoding: [0x48,0xa7]
119119 // ERR32: 64-bit
120120 // ERR16: 64-bit
121
122 movsb (%esi), (%edi)
123 // 64: movsb (%esi), %es:(%edi) # encoding: [0x67,0xa4]
124 // 32: movsb (%esi), %es:(%edi) # encoding: [0xa4]
125 // 16: movsb (%esi), %es:(%edi) # encoding: [0x67,0xa4]
126
127 movsl %gs:(%esi), (%edi)
128 // 64: movsl %gs:(%esi), %es:(%edi) # encoding: [0x65,0x67,0xa5]
129 // 32: movsl %gs:(%esi), %es:(%edi) # encoding: [0x65,0xa5]
130 // 16: movsl %gs:(%esi), %es:(%edi) # encoding: [0x66,0x65,0x67,0xa5]
823823 insl
824824 insl %dx, %es:(%di)
825825
826 // CHECK: movsb # encoding: [0xa4]
826 // CHECK: movsb (%si), %es:(%di) # encoding: [0xa4]
827827 // CHECK: movsb
828828 // CHECK: movsb
829829 movsb
830830 movsb %ds:(%si), %es:(%di)
831831 movsb (%si), %es:(%di)
832832
833 // CHECK: movsw # encoding: [0xa5]
833 // CHECK: movsw (%si), %es:(%di) # encoding: [0xa5]
834834 // CHECK: movsw
835835 // CHECK: movsw
836836 movsw
837837 movsw %ds:(%si), %es:(%di)
838838 movsw (%si), %es:(%di)
839839
840 // CHECK: movsl # encoding: [0x66,0xa5]
840 // CHECK: movsl (%si), %es:(%di) # encoding: [0x66,0xa5]
841841 // CHECK: movsl
842842 // CHECK: movsl
843843 movsl
899899 insl
900900 insl %dx, %es:(%edi)
901901
902 // CHECK: movsb # encoding: [0xa4]
902 // CHECK: movsb (%esi), %es:(%edi) # encoding: [0xa4]
903903 // CHECK: movsb
904904 // CHECK: movsb
905905 movsb
906906 movsb %ds:(%esi), %es:(%edi)
907907 movsb (%esi), %es:(%edi)
908908
909 // CHECK: movsw # encoding: [0x66,0xa5]
909 // CHECK: movsw (%esi), %es:(%edi) # encoding: [0x66,0xa5]
910910 // CHECK: movsw
911911 // CHECK: movsw
912912 movsw
913913 movsw %ds:(%esi), %es:(%edi)
914914 movsw (%esi), %es:(%edi)
915915
916 // CHECK: movsl # encoding: [0xa5]
916 // CHECK: movsl (%esi), %es:(%edi) # encoding: [0xa5]
917917 // CHECK: movsl
918918 // CHECK: movsl
919919 movsl
10841084 insl
10851085 insl %dx, %es:(%rdi)
10861086
1087 // CHECK: movsb # encoding: [0xa4]
1087 // CHECK: movsb (%rsi), %es:(%rdi) # encoding: [0xa4]
10881088 // CHECK: movsb
10891089 // CHECK: movsb
10901090 movsb
10911091 movsb %ds:(%rsi), %es:(%rdi)
10921092 movsb (%rsi), %es:(%rdi)
10931093
1094 // CHECK: movsw # encoding: [0x66,0xa5]
1094 // CHECK: movsw (%rsi), %es:(%rdi) # encoding: [0x66,0xa5]
10951095 // CHECK: movsw
10961096 // CHECK: movsw
10971097 movsw
10981098 movsw %ds:(%rsi), %es:(%rdi)
10991099 movsw (%rsi), %es:(%rdi)
11001100
1101 // CHECK: movsl # encoding: [0xa5]
1101 // CHECK: movsl (%rsi), %es:(%rdi) # encoding: [0xa5]
11021102 // CHECK: movsl
11031103 // CHECK: movsl
11041104 movsl
11081108 // CHECK: movsl
11091109 movsl (%rsi), (%rdi)
11101110
1111 // CHECK: movsq # encoding: [0x48,0xa5]
1111 // CHECK: movsq (%rsi), %es:(%rdi) # encoding: [0x48,0xa5]
11121112 // CHECK: movsq
11131113 // CHECK: movsq
11141114 movsq