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Merging r246372: ------------------------------------------------------------------------ r246372 | hfinkel | 2015-08-30 03:44:05 -0400 (Sun, 30 Aug 2015) | 10 lines [PowerPC] Don't assume ADDISdtprelHA's source is r3 Even through ADDISdtprelHA generally has r3 as its source register, it is possible for the instruction scheduler to move things around such that some other register is the source. We need to print the actual source register, not always r3. Fixes PR24394. The test case will come in a follow-up commit because it depends on MIR target-flags parsing. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@252477 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
1 changed file(s) with 5 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
946946 return;
947947 }
948948 case PPC::ADDISdtprelHA:
949 // Transform: %Xd = ADDISdtprelHA %X3,
950 // Into: %Xd = ADDIS8 %X3, sym@dtprel@ha
949 // Transform: %Xd = ADDISdtprelHA %Xs,
950 // Into: %Xd = ADDIS8 %Xs, sym@dtprel@ha
951951 case PPC::ADDISdtprelHA32: {
952 // Transform: %Rd = ADDISdtprelHA32 %R3,
953 // Into: %Rd = ADDIS %R3, sym@dtprel@ha
952 // Transform: %Rd = ADDISdtprelHA32 %Rs,
953 // Into: %Rd = ADDIS %Rs, sym@dtprel@ha
954954 const MachineOperand &MO = MI->getOperand(2);
955955 const GlobalValue *GValue = MO.getGlobal();
956956 MCSymbol *MOSymbol = getSymbol(GValue);
961961 *OutStreamer,
962962 MCInstBuilder(Subtarget->isPPC64() ? PPC::ADDIS8 : PPC::ADDIS)
963963 .addReg(MI->getOperand(0).getReg())
964 .addReg(Subtarget->isPPC64() ? PPC::X3 : PPC::R3)
964 .addReg(MI->getOperand(1).getReg())
965965 .addExpr(SymDtprel));
966966 return;
967967 }