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Merging r226188: ------------------------------------------------------------------------ r226188 | marek.olsak | 2015-01-15 13:42:51 -0500 (Thu, 15 Jan 2015) | 7 lines R600/SI: Don't shrink instructions whose e32 encoding doesn't exist v2: modify hasVALU32BitEncoding instead v3: - add pseudoToMCOpcode helper to AMDGPUInstInfo, which is used by both hasVALU32BitEncoding and AMDGPUMCInstLower::lower - report an error if a pseudo can't be lowered ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@226717 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
8 changed file(s) with 59 addition(s) and 44 deletion(s). Raw diff Collapse all Expand all
340340 // instead.
341341 namespace llvm {
342342 namespace AMDGPU {
343 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
343 static int getMCOpcode(uint16_t Opcode, unsigned Gen) {
344344 return getMCOpcodeGen(Opcode, (enum Subtarget)Gen);
345345 }
346346 }
347347 }
348
349 // This must be kept in sync with the SISubtarget class in SIInstrInfo.td
350 enum SISubtarget {
351 SI = 0,
352 VI = 1
353 };
354
355 enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen) {
356 switch (Gen) {
357 default:
358 return SI;
359 case AMDGPUSubtarget::VOLCANIC_ISLANDS:
360 return VI;
361 }
362 }
363
364 int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const {
365 int MCOp = AMDGPU::getMCOpcode(Opcode,
366 AMDGPUSubtargetToSISubtarget(RI.ST.getGeneration()));
367
368 // -1 means that Opcode is already a native instruction.
369 if (MCOp == -1)
370 return Opcode;
371
372 // (uint16_t)-1 means that Opcode is a pseudo instruction that has
373 // no encoding in the given subtarget generation.
374 if (MCOp == (uint16_t)-1)
375 return -1;
376
377 return MCOp;
378 }
134134 bool isRegisterStore(const MachineInstr &MI) const;
135135 bool isRegisterLoad(const MachineInstr &MI) const;
136136
137 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
138 /// Return -1 if the target-specific opcode for the pseudo instruction does
139 /// not exist. If Opcode is not a pseudo instruction, this is identity.
140 int pseudoToMCOpcode(int Opcode) const;
141
137142 //===---------------------------------------------------------------------===//
138143 // Pure virtual funtions to be implemented by sub-classes.
139144 //===---------------------------------------------------------------------===//
2121 #include "llvm/CodeGen/MachineBasicBlock.h"
2222 #include "llvm/CodeGen/MachineInstr.h"
2323 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/Function.h"
2425 #include "llvm/IR/GlobalVariable.h"
2526 #include "llvm/MC/MCCodeEmitter.h"
2627 #include "llvm/MC/MCContext.h"
3839 Ctx(ctx), ST(st)
3940 { }
4041
41 enum AMDGPUMCInstLower::SISubtarget
42 AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const {
43 switch (Gen) {
44 default:
45 return AMDGPUMCInstLower::SI;
46 case AMDGPUSubtarget::VOLCANIC_ISLANDS:
47 return AMDGPUMCInstLower::VI;
48 }
49 }
50
51 unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const {
52
53 int MCOpcode = AMDGPU::getMCOpcode(MIOpcode,
54 AMDGPUSubtargetToSISubtarget(ST.getGeneration()));
55 if (MCOpcode == -1)
56 MCOpcode = MIOpcode;
57
58 return MCOpcode;
59 }
60
6142 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
6243
63 OutMI.setOpcode(getMCOpcode(MI->getOpcode()));
44 int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode());
45
46 if (MCOpcode == -1) {
47 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
48 C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
49 "a target-specific version: " + Twine(MI->getOpcode()));
50 }
51
52 OutMI.setOpcode(MCOpcode);
6453
6554 for (const MachineOperand &MO : MI->explicit_operands()) {
6655 MCOperand MCOp;
1818 class MCInst;
1919
2020 class AMDGPUMCInstLower {
21
22 // This must be kept in sync with the SISubtarget class in SIInstrInfo.td
23 enum SISubtarget {
24 SI = 0,
25 VI = 1
26 };
27
2821 MCContext &Ctx;
2922 const AMDGPUSubtarget &ST;
30
31 /// Convert a member of the AMDGPUSubtarget::Generation enum to the
32 /// SISubtarget enum.
33 enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen) const;
34
35 /// Get the MC opcode for this MachineInstr.
36 unsigned getMCOpcode(unsigned MIOpcode) const;
3723
3824 public:
3925 AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &ST);
10521052 }
10531053
10541054 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1055 return AMDGPU::getVOPe32(Opcode) != -1;
1055 int Op32 = AMDGPU::getVOPe32(Opcode);
1056 if (Op32 == -1)
1057 return false;
1058
1059 return pseudoToMCOpcode(Op32) != -1;
10561060 }
10571061
10581062 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
324324 int getVOPe32(uint16_t Opcode);
325325 int getCommuteRev(uint16_t Opcode);
326326 int getCommuteOrig(uint16_t Opcode);
327 int getMCOpcode(uint16_t Opcode, unsigned Gen);
328327 int getAddr64Inst(uint16_t Opcode);
329328 int getAtomicRetOp(uint16_t Opcode);
330329 int getAtomicNoRetOp(uint16_t Opcode);
5656 }
5757
5858 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
59 // in AMDGPUMCInstLower.h
59 // in AMDGPUInstrInfo.cpp
6060 def SISubtarget {
6161 int NONE = -1;
6262 int SI = 0;
99 //
1010
1111 #include "AMDGPU.h"
12 #include "AMDGPUMCInstLower.h"
1213 #include "AMDGPUSubtarget.h"
1314 #include "SIInstrInfo.h"
1415 #include "llvm/ADT/Statistic.h"
205206 continue;
206207 }
207208
209 // getVOPe32 could be -1 here if we started with an instruction that had
210 // a 32-bit encoding and then commuted it to an instruction that did not.
211 if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
212 continue;
213
208214 int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
209
210 // Op32 could be -1 here if we started with an instruction that had a
211 // a 32-bit encoding and then commuted it to an instruction that did not.
212 if (Op32 == -1)
213 continue;
214215
215216 if (TII->isVOPC(Op32)) {
216217 unsigned DstReg = MI.getOperand(0).getReg();