llvm.org GIT mirror llvm / 51481b9
[ARM] Add MVE vector shift instructions. This includes saturating and non-saturating shifts, both with immediate shift count and with the shift counts given by another vector register; VSHLC (in which the bits shifted out of each active vector lane are shifted in to the next active lane); and also VMOVL, which is enough like an immediate shift that it didn't fit too badly in this category. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62672 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363696 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 1 year, 1 month ago
6 changed file(s) with 1816 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
776776 imm1_16_XFORM> {
777777 let PrintMethod = "printImmPlusOneOperand";
778778 let ParserMatchClass = Imm1_16AsmOperand;
779 }
780
781 def MVEShiftImm1_7AsmOperand: ImmAsmOperand<1,7> {
782 let Name = "MVEShiftImm1_7";
783 // Reason we're doing this is because instruction vshll.s8 t1 encoding
784 // accepts 1,7 but the t2 encoding accepts 8. By doing this we can get a
785 // better diagnostic message if someone uses bigger immediate than the t1/t2
786 // encodings allow.
787 let DiagnosticString = "operand must be an immediate in the range [1,8]";
788 }
789 def mve_shift_imm1_7 : Operand {
790 let ParserMatchClass = MVEShiftImm1_7AsmOperand;
791 let EncoderMethod = "getMVEShiftImmOpValue";
792 }
793
794 def MVEShiftImm1_15AsmOperand: ImmAsmOperand<1,15> {
795 let Name = "MVEShiftImm1_15";
796 // Reason we're doing this is because instruction vshll.s16 t1 encoding
797 // accepts 1,15 but the t2 encoding accepts 16. By doing this we can get a
798 // better diagnostic message if someone uses bigger immediate than the t1/t2
799 // encodings allow.
800 let DiagnosticString = "operand must be an immediate in the range [1,16]";
801 }
802 def mve_shift_imm1_15 : Operand {
803 let ParserMatchClass = MVEShiftImm1_15AsmOperand;
804 let EncoderMethod = "getMVEShiftImmOpValue";
779805 }
780806
781807 // Define ARM specific addressing modes.
669669
670670 // end of mve_comp instructions
671671
672 // start of mve_imm_shift instructions
673
674 def MVE_VSHLC : MVE_p<(outs rGPR:$RdmDest, MQPR:$Qd),
675 (ins MQPR:$QdSrc, rGPR:$RdmSrc, long_shift:$imm),
676 NoItinerary, "vshlc", "", "$QdSrc, $RdmSrc, $imm",
677 vpred_n, "$RdmDest = $RdmSrc,$Qd = $QdSrc"> {
678 bits<5> imm;
679 bits<4> Qd;
680 bits<4> RdmDest;
681
682 let Inst{28} = 0b0;
683 let Inst{25-23} = 0b101;
684 let Inst{22} = Qd{3};
685 let Inst{21} = 0b1;
686 let Inst{20-16} = imm{4-0};
687 let Inst{15-13} = Qd{2-0};
688 let Inst{12-4} = 0b011111100;
689 let Inst{3-0} = RdmDest{3-0};
690 }
691
692 class MVE_shift_imm
693 string ops, vpred_ops vpred, string cstr,
694 list pattern=[]>
695 : MVE_p {
696 bits<4> Qd;
697 bits<4> Qm;
698
699 let Inst{22} = Qd{3};
700 let Inst{15-13} = Qd{2-0};
701 let Inst{5} = Qm{3};
702 let Inst{3-1} = Qm{2-0};
703 }
704
705 class MVE_VMOVL sz, bit U,
706 list pattern=[]>
707 : MVE_shift_imm<(outs MQPR:$Qd), (ins MQPR:$Qm),
708 iname, suffix, "$Qd, $Qm", vpred_r, "",
709 pattern> {
710 let Inst{28} = U;
711 let Inst{25-23} = 0b101;
712 let Inst{21} = 0b1;
713 let Inst{20-19} = sz{1-0};
714 let Inst{18-16} = 0b000;
715 let Inst{11-6} = 0b111101;
716 let Inst{4} = 0b0;
717 let Inst{0} = 0b0;
718 }
719
720 multiclass MVE_VMOVL_shift_half sz, bit U,
721 list pattern=[]> {
722 def bh : MVE_VMOVL {
723 let Inst{12} = 0b0;
724 }
725 def th : MVE_VMOVL {
726 let Inst{12} = 0b1;
727 }
728 }
729
730 defm MVE_VMOVLs8 : MVE_VMOVL_shift_half<"vmovl", "s8", 0b01, 0b0>;
731 defm MVE_VMOVLu8 : MVE_VMOVL_shift_half<"vmovl", "u8", 0b01, 0b1>;
732 defm MVE_VMOVLs16 : MVE_VMOVL_shift_half<"vmovl", "s16", 0b10, 0b0>;
733 defm MVE_VMOVLu16 : MVE_VMOVL_shift_half<"vmovl", "u16", 0b10, 0b1>;
734
735 class MVE_VSHLL_imm
736 dag immops, list pattern=[]>
737 : MVE_shift_imm<(outs MQPR:$Qd), !con((ins MQPR:$Qm), immops),
738 iname, suffix, "$Qd, $Qm, $imm", vpred_r, "", pattern> {
739 let Inst{28} = U;
740 let Inst{25-23} = 0b101;
741 let Inst{21} = 0b1;
742 let Inst{12} = th;
743 let Inst{11-6} = 0b111101;
744 let Inst{4} = 0b0;
745 let Inst{0} = 0b0;
746 }
747
748 // The immediate VSHLL instructions accept shift counts from 1 up to
749 // the lane width (8 or 16), but the full-width shifts have an
750 // entirely separate encoding, given below with 'lw' in the name.
751
752 class MVE_VSHLL_imm8
753 bit U, bit th, list pattern=[]>
754 : MVE_VSHLL_imm {
755 bits<3> imm;
756 let Inst{20-19} = 0b01;
757 let Inst{18-16} = imm;
758 }
759
760 class MVE_VSHLL_imm16
761 bit U, bit th, list pattern=[]>
762 : MVE_VSHLL_imm {
763 bits<4> imm;
764 let Inst{20} = 0b1;
765 let Inst{19-16} = imm;
766 }
767
768 def MVE_VSHLL_imms8bh : MVE_VSHLL_imm8 <"vshllb", "s8", 0b0, 0b0>;
769 def MVE_VSHLL_imms8th : MVE_VSHLL_imm8 <"vshllt", "s8", 0b0, 0b1>;
770 def MVE_VSHLL_immu8bh : MVE_VSHLL_imm8 <"vshllb", "u8", 0b1, 0b0>;
771 def MVE_VSHLL_immu8th : MVE_VSHLL_imm8 <"vshllt", "u8", 0b1, 0b1>;
772 def MVE_VSHLL_imms16bh : MVE_VSHLL_imm16<"vshllb", "s16", 0b0, 0b0>;
773 def MVE_VSHLL_imms16th : MVE_VSHLL_imm16<"vshllt", "s16", 0b0, 0b1>;
774 def MVE_VSHLL_immu16bh : MVE_VSHLL_imm16<"vshllb", "u16", 0b1, 0b0>;
775 def MVE_VSHLL_immu16th : MVE_VSHLL_imm16<"vshllt", "u16", 0b1, 0b1>;
776
777 class MVE_VSHLL_by_lane_width size,
778 bit U, string ops, list pattern=[]>
779 : MVE_shift_imm<(outs MQPR:$Qd), (ins MQPR:$Qm),
780 iname, suffix, ops, vpred_r, "", pattern> {
781 let Inst{28} = U;
782 let Inst{25-23} = 0b100;
783 let Inst{21-20} = 0b11;
784 let Inst{19-18} = size{1-0};
785 let Inst{17-16} = 0b01;
786 let Inst{11-6} = 0b111000;
787 let Inst{4} = 0b0;
788 let Inst{0} = 0b1;
789 }
790
791 multiclass MVE_VSHLL_lw sz, bit U,
792 string ops, list pattern=[]> {
793 def bh : MVE_VSHLL_by_lane_width {
794 let Inst{12} = 0b0;
795 }
796 def th : MVE_VSHLL_by_lane_width {
797 let Inst{12} = 0b1;
798 }
799 }
800
801 defm MVE_VSHLL_lws8 : MVE_VSHLL_lw<"vshll", "s8", 0b00, 0b0, "$Qd, $Qm, #8">;
802 defm MVE_VSHLL_lws16 : MVE_VSHLL_lw<"vshll", "s16", 0b01, 0b0, "$Qd, $Qm, #16">;
803 defm MVE_VSHLL_lwu8 : MVE_VSHLL_lw<"vshll", "u8", 0b00, 0b1, "$Qd, $Qm, #8">;
804 defm MVE_VSHLL_lwu16 : MVE_VSHLL_lw<"vshll", "u16", 0b01, 0b1, "$Qd, $Qm, #16">;
805
806 class MVE_VxSHRN
807 dag immops, list pattern=[]>
808 : MVE_shift_imm<(outs MQPR:$Qd), !con((ins MQPR:$QdSrc, MQPR:$Qm), immops),
809 iname, suffix, "$Qd, $Qm, $imm", vpred_n, "$Qd = $QdSrc",
810 pattern> {
811 bits<5> imm;
812
813 let Inst{28} = bit_28;
814 let Inst{25-23} = 0b101;
815 let Inst{21} = 0b0;
816 let Inst{20-16} = imm{4-0};
817 let Inst{12} = bit_12;
818 let Inst{11-6} = 0b111111;
819 let Inst{4} = 0b0;
820 let Inst{0} = 0b1;
821 }
822
823 def MVE_VRSHRNi16bh : MVE_VxSHRN<
824 "vrshrnb", "i16", 0b0, 0b1, (ins shr_imm8:$imm)> {
825 let Inst{20-19} = 0b01;
826 }
827 def MVE_VRSHRNi16th : MVE_VxSHRN<
828 "vrshrnt", "i16", 0b1, 0b1,(ins shr_imm8:$imm)> {
829 let Inst{20-19} = 0b01;
830 }
831 def MVE_VRSHRNi32bh : MVE_VxSHRN<
832 "vrshrnb", "i32", 0b0, 0b1, (ins shr_imm16:$imm)> {
833 let Inst{20} = 0b1;
834 }
835 def MVE_VRSHRNi32th : MVE_VxSHRN<
836 "vrshrnt", "i32", 0b1, 0b1, (ins shr_imm16:$imm)> {
837 let Inst{20} = 0b1;
838 }
839
840 def MVE_VSHRNi16bh : MVE_VxSHRN<
841 "vshrnb", "i16", 0b0, 0b0, (ins shr_imm8:$imm)> {
842 let Inst{20-19} = 0b01;
843 }
844 def MVE_VSHRNi16th : MVE_VxSHRN<
845 "vshrnt", "i16", 0b1, 0b0, (ins shr_imm8:$imm)> {
846 let Inst{20-19} = 0b01;
847 }
848 def MVE_VSHRNi32bh : MVE_VxSHRN<
849 "vshrnb", "i32", 0b0, 0b0, (ins shr_imm16:$imm)> {
850 let Inst{20} = 0b1;
851 }
852 def MVE_VSHRNi32th : MVE_VxSHRN<
853 "vshrnt", "i32", 0b1, 0b0, (ins shr_imm16:$imm)> {
854 let Inst{20} = 0b1;
855 }
856
857 class MVE_VxQRSHRUN
858 list pattern=[]>
859 : MVE_shift_imm<(outs MQPR:$Qd), !con((ins MQPR:$QdSrc, MQPR:$Qm), immops),
860 iname, suffix, "$Qd, $Qm, $imm", vpred_n, "$Qd = $QdSrc",
861 pattern> {
862 bits<5> imm;
863
864 let Inst{28} = bit_28;
865 let Inst{25-23} = 0b101;
866 let Inst{21} = 0b0;
867 let Inst{20-16} = imm{4-0};
868 let Inst{12} = bit_12;
869 let Inst{11-6} = 0b111111;
870 let Inst{4} = 0b0;
871 let Inst{0} = 0b0;
872 }
873
874 def MVE_VQRSHRUNs16bh : MVE_VxQRSHRUN<
875 "vqrshrunb", "s16", 0b1, 0b0, (ins shr_imm8:$imm)> {
876 let Inst{20-19} = 0b01;
877 }
878 def MVE_VQRSHRUNs16th : MVE_VxQRSHRUN<
879 "vqrshrunt", "s16", 0b1, 0b1, (ins shr_imm8:$imm)> {
880 let Inst{20-19} = 0b01;
881 }
882 def MVE_VQRSHRUNs32bh : MVE_VxQRSHRUN<
883 "vqrshrunb", "s32", 0b1, 0b0, (ins shr_imm16:$imm)> {
884 let Inst{20} = 0b1;
885 }
886 def MVE_VQRSHRUNs32th : MVE_VxQRSHRUN<
887 "vqrshrunt", "s32", 0b1, 0b1, (ins shr_imm16:$imm)> {
888 let Inst{20} = 0b1;
889 }
890
891 def MVE_VQSHRUNs16bh : MVE_VxQRSHRUN<
892 "vqshrunb", "s16", 0b0, 0b0, (ins shr_imm8:$imm)> {
893 let Inst{20-19} = 0b01;
894 }
895 def MVE_VQSHRUNs16th : MVE_VxQRSHRUN<
896 "vqshrunt", "s16", 0b0, 0b1, (ins shr_imm8:$imm)> {
897 let Inst{20-19} = 0b01;
898 }
899 def MVE_VQSHRUNs32bh : MVE_VxQRSHRUN<
900 "vqshrunb", "s32", 0b0, 0b0, (ins shr_imm16:$imm)> {
901 let Inst{20} = 0b1;
902 }
903 def MVE_VQSHRUNs32th : MVE_VxQRSHRUN<
904 "vqshrunt", "s32", 0b0, 0b1, (ins shr_imm16:$imm)> {
905 let Inst{20} = 0b1;
906 }
907
908 class MVE_VxQRSHRN
909 dag immops, list pattern=[]>
910 : MVE_shift_imm<(outs MQPR:$Qd), !con((ins MQPR:$QdSrc, MQPR:$Qm), immops),
911 iname, suffix, "$Qd, $Qm, $imm", vpred_n, "$Qd = $QdSrc",
912 pattern> {
913 bits<5> imm;
914
915 let Inst{25-23} = 0b101;
916 let Inst{21} = 0b0;
917 let Inst{20-16} = imm{4-0};
918 let Inst{12} = bit_12;
919 let Inst{11-6} = 0b111101;
920 let Inst{4} = 0b0;
921 let Inst{0} = bit_0;
922 }
923
924 multiclass MVE_VxQRSHRN_types {
925 def s16 : MVE_VxQRSHRN {
926 let Inst{28} = 0b0;
927 let Inst{20-19} = 0b01;
928 }
929 def u16 : MVE_VxQRSHRN {
930 let Inst{28} = 0b1;
931 let Inst{20-19} = 0b01;
932 }
933 def s32 : MVE_VxQRSHRN {
934 let Inst{28} = 0b0;
935 let Inst{20} = 0b1;
936 }
937 def u32 : MVE_VxQRSHRN {
938 let Inst{28} = 0b1;
939 let Inst{20} = 0b1;
940 }
941 }
942
943 defm MVE_VQRSHRNbh : MVE_VxQRSHRN_types<"vqrshrnb", 0b1, 0b0>;
944 defm MVE_VQRSHRNth : MVE_VxQRSHRN_types<"vqrshrnt", 0b1, 0b1>;
945 defm MVE_VQSHRNbh : MVE_VxQRSHRN_types<"vqshrnb", 0b0, 0b0>;
946 defm MVE_VQSHRNth : MVE_VxQRSHRN_types<"vqshrnt", 0b0, 0b1>;
947
948 // end of mve_imm_shift instructions
949
950 // start of mve_shift instructions
951
952 class MVE_shift_by_vec
953 bits<2> size, bit bit_4, bit bit_8>
954 : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qm, MQPR:$Qn), NoItinerary,
955 iname, suffix, "$Qd, $Qm, $Qn", vpred_r, "", []> {
956 // Shift instructions which take a vector of shift counts
957 bits<4> Qd;
958 bits<4> Qm;
959 bits<4> Qn;
960
961 let Inst{28} = U;
962 let Inst{25-24} = 0b11;
963 let Inst{23} = 0b0;
964 let Inst{22} = Qd{3};
965 let Inst{21-20} = size;
966 let Inst{19-17} = Qn{2-0};
967 let Inst{16} = 0b0;
968 let Inst{15-13} = Qd{2-0};
969 let Inst{12-9} = 0b0010;
970 let Inst{8} = bit_8;
971 let Inst{7} = Qn{3};
972 let Inst{6} = 0b1;
973 let Inst{5} = Qm{3};
974 let Inst{4} = bit_4;
975 let Inst{3-1} = Qm{2-0};
976 let Inst{0} = 0b0;
977 }
978
979 multiclass mve_shift_by_vec_multi {
980 def s8 : MVE_shift_by_vec;
981 def s16 : MVE_shift_by_vec;
982 def s32 : MVE_shift_by_vec;
983 def u8 : MVE_shift_by_vec;
984 def u16 : MVE_shift_by_vec;
985 def u32 : MVE_shift_by_vec;
986 }
987
988 defm MVE_VSHL_by_vec : mve_shift_by_vec_multi<"vshl", 0b0, 0b0>;
989 defm MVE_VQSHL_by_vec : mve_shift_by_vec_multi<"vqshl", 0b1, 0b0>;
990 defm MVE_VQRSHL_by_vec : mve_shift_by_vec_multi<"vqrshl", 0b1, 0b1>;
991 defm MVE_VRSHL_by_vec : mve_shift_by_vec_multi<"vrshl", 0b0, 0b1>;
992
993 class MVE_shift_with_imm
994 string ops, vpred_ops vpred, string cstr,
995 list pattern=[]>
996 : MVE_p {
997 bits<4> Qd;
998 bits<4> Qm;
999
1000 let Inst{23} = 0b1;
1001 let Inst{22} = Qd{3};
1002 let Inst{15-13} = Qd{2-0};
1003 let Inst{12-11} = 0b00;
1004 let Inst{7-6} = 0b01;
1005 let Inst{5} = Qm{3};
1006 let Inst{4} = 0b1;
1007 let Inst{3-1} = Qm{2-0};
1008 let Inst{0} = 0b0;
1009 }
1010
1011 class MVE_VSxI_imm
1012 : MVE_shift_with_imm
1013 !con((ins MQPR:$Qd_src, MQPR:$Qm), imm),
1014 "$Qd, $Qm, $imm", vpred_n, "$Qd = $Qd_src"> {
1015 bits<6> imm;
1016 let Inst{28} = 0b1;
1017 let Inst{25-24} = 0b11;
1018 let Inst{21-16} = imm;
1019 let Inst{10-9} = 0b10;
1020 let Inst{8} = bit_8;
1021 }
1022
1023 def MVE_VSRIimm8 : MVE_VSxI_imm<"vsri", "8", 0b0, (ins shr_imm8:$imm)> {
1024 let Inst{21-19} = 0b001;
1025 }
1026
1027 def MVE_VSRIimm16 : MVE_VSxI_imm<"vsri", "16", 0b0, (ins shr_imm16:$imm)> {
1028 let Inst{21-20} = 0b01;
1029 }
1030
1031 def MVE_VSRIimm32 : MVE_VSxI_imm<"vsri", "32", 0b0, (ins shr_imm32:$imm)> {
1032 let Inst{21} = 0b1;
1033 }
1034
1035 def MVE_VSLIimm8 : MVE_VSxI_imm<"vsli", "8", 0b1, (ins imm0_7:$imm)> {
1036 let Inst{21-19} = 0b001;
1037 }
1038
1039 def MVE_VSLIimm16 : MVE_VSxI_imm<"vsli", "16", 0b1, (ins imm0_15:$imm)> {
1040 let Inst{21-20} = 0b01;
1041 }
1042
1043 def MVE_VSLIimm32 : MVE_VSxI_imm<"vsli", "32", 0b1,(ins imm0_31:$imm)> {
1044 let Inst{21} = 0b1;
1045 }
1046
1047 class MVE_VQSHL_imm
1048 : MVE_shift_with_imm<"vqshl", suffix, (outs MQPR:$Qd),
1049 !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
1050 vpred_r, ""> {
1051 bits<6> imm;
1052
1053 let Inst{25-24} = 0b11;
1054 let Inst{21-16} = imm;
1055 let Inst{10-8} = 0b111;
1056 }
1057
1058 def MVE_VSLIimms8 : MVE_VQSHL_imm<"s8", (ins imm0_7:$imm)> {
1059 let Inst{28} = 0b0;
1060 let Inst{21-19} = 0b001;
1061 }
1062
1063 def MVE_VSLIimmu8 : MVE_VQSHL_imm<"u8", (ins imm0_7:$imm)> {
1064 let Inst{28} = 0b1;
1065 let Inst{21-19} = 0b001;
1066 }
1067
1068 def MVE_VSLIimms16 : MVE_VQSHL_imm<"s16", (ins imm0_15:$imm)> {
1069 let Inst{28} = 0b0;
1070 let Inst{21-20} = 0b01;
1071 }
1072
1073 def MVE_VSLIimmu16 : MVE_VQSHL_imm<"u16", (ins imm0_15:$imm)> {
1074 let Inst{28} = 0b1;
1075 let Inst{21-20} = 0b01;
1076 }
1077
1078 def MVE_VSLIimms32 : MVE_VQSHL_imm<"s32", (ins imm0_31:$imm)> {
1079 let Inst{28} = 0b0;
1080 let Inst{21} = 0b1;
1081 }
1082
1083 def MVE_VSLIimmu32 : MVE_VQSHL_imm<"u32", (ins imm0_31:$imm)> {
1084 let Inst{28} = 0b1;
1085 let Inst{21} = 0b1;
1086 }
1087
1088 class MVE_VQSHLU_imm
1089 : MVE_shift_with_imm<"vqshlu", suffix, (outs MQPR:$Qd),
1090 !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
1091 vpred_r, ""> {
1092 bits<6> imm;
1093
1094 let Inst{28} = 0b1;
1095 let Inst{25-24} = 0b11;
1096 let Inst{21-16} = imm;
1097 let Inst{10-8} = 0b110;
1098 }
1099
1100 def MVE_VQSHLU_imms8 : MVE_VQSHLU_imm<"s8", (ins imm0_7:$imm)> {
1101 let Inst{21-19} = 0b001;
1102 }
1103
1104 def MVE_VQSHLU_imms16 : MVE_VQSHLU_imm<"s16", (ins imm0_15:$imm)> {
1105 let Inst{21-20} = 0b01;
1106 }
1107
1108 def MVE_VQSHLU_imms32 : MVE_VQSHLU_imm<"s32", (ins imm0_31:$imm)> {
1109 let Inst{21} = 0b1;
1110 }
1111
1112 class MVE_VRSHR_imm
1113 : MVE_shift_with_imm<"vrshr", suffix, (outs MQPR:$Qd),
1114 !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
1115 vpred_r, ""> {
1116 bits<6> imm;
1117
1118 let Inst{25-24} = 0b11;
1119 let Inst{21-16} = imm;
1120 let Inst{10-8} = 0b010;
1121 }
1122
1123 def MVE_VRSHR_imms8 : MVE_VRSHR_imm<"s8", (ins shr_imm8:$imm)> {
1124 let Inst{28} = 0b0;
1125 let Inst{21-19} = 0b001;
1126 }
1127
1128 def MVE_VRSHR_immu8 : MVE_VRSHR_imm<"u8", (ins shr_imm8:$imm)> {
1129 let Inst{28} = 0b1;
1130 let Inst{21-19} = 0b001;
1131 }
1132
1133 def MVE_VRSHR_imms16 : MVE_VRSHR_imm<"s16", (ins shr_imm16:$imm)> {
1134 let Inst{28} = 0b0;
1135 let Inst{21-20} = 0b01;
1136 }
1137
1138 def MVE_VRSHR_immu16 : MVE_VRSHR_imm<"u16", (ins shr_imm16:$imm)> {
1139 let Inst{28} = 0b1;
1140 let Inst{21-20} = 0b01;
1141 }
1142
1143 def MVE_VRSHR_imms32 : MVE_VRSHR_imm<"s32", (ins shr_imm32:$imm)> {
1144 let Inst{28} = 0b0;
1145 let Inst{21} = 0b1;
1146 }
1147
1148 def MVE_VRSHR_immu32 : MVE_VRSHR_imm<"u32", (ins shr_imm32:$imm)> {
1149 let Inst{28} = 0b1;
1150 let Inst{21} = 0b1;
1151 }
1152
1153 class MVE_VSHR_imm
1154 : MVE_shift_with_imm<"vshr", suffix, (outs MQPR:$Qd),
1155 !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
1156 vpred_r, ""> {
1157 bits<6> imm;
1158
1159 let Inst{25-24} = 0b11;
1160 let Inst{21-16} = imm;
1161 let Inst{10-8} = 0b000;
1162 }
1163
1164 def MVE_VSHR_imms8 : MVE_VSHR_imm<"s8", (ins shr_imm8:$imm)> {
1165 let Inst{28} = 0b0;
1166 let Inst{21-19} = 0b001;
1167 }
1168
1169 def MVE_VSHR_immu8 : MVE_VSHR_imm<"u8", (ins shr_imm8:$imm)> {
1170 let Inst{28} = 0b1;
1171 let Inst{21-19} = 0b001;
1172 }
1173
1174 def MVE_VSHR_imms16 : MVE_VSHR_imm<"s16", (ins shr_imm16:$imm)> {
1175 let Inst{28} = 0b0;
1176 let Inst{21-20} = 0b01;
1177 }
1178
1179 def MVE_VSHR_immu16 : MVE_VSHR_imm<"u16", (ins shr_imm16:$imm)> {
1180 let Inst{28} = 0b1;
1181 let Inst{21-20} = 0b01;
1182 }
1183
1184 def MVE_VSHR_imms32 : MVE_VSHR_imm<"s32", (ins shr_imm32:$imm)> {
1185 let Inst{28} = 0b0;
1186 let Inst{21} = 0b1;
1187 }
1188
1189 def MVE_VSHR_immu32 : MVE_VSHR_imm<"u32", (ins shr_imm32:$imm)> {
1190 let Inst{28} = 0b1;
1191 let Inst{21} = 0b1;
1192 }
1193
1194 class MVE_VSHL_imm
1195 : MVE_shift_with_imm<"vshl", suffix, (outs MQPR:$Qd),
1196 !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
1197 vpred_r, ""> {
1198 bits<6> imm;
1199
1200 let Inst{28} = 0b0;
1201 let Inst{25-24} = 0b11;
1202 let Inst{21-16} = imm;
1203 let Inst{10-8} = 0b101;
1204 }
1205
1206 def MVE_VSHL_immi8 : MVE_VSHL_imm<"i8", (ins imm0_7:$imm)> {
1207 let Inst{21-19} = 0b001;
1208 }
1209
1210 def MVE_VSHL_immi16 : MVE_VSHL_imm<"i16", (ins imm0_15:$imm)> {
1211 let Inst{21-20} = 0b01;
1212 }
1213
1214 def MVE_VSHL_immi32 : MVE_VSHL_imm<"i32", (ins imm0_31:$imm)> {
1215 let Inst{21} = 0b1;
1216 }
1217 // end of mve_shift instructions
1218
6721219 class MVE_VPT size, dag iops, string asm, list pattern=[]>
6731220 : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
6741221 bits<3> fc;
59335933 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
59345934 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
59355935 Mnemonic != "sbcs" && Mnemonic != "rscs" &&
5936 !(hasMVE() && Mnemonic == "vmine")) {
5936 !(hasMVE() &&
5937 (Mnemonic == "vmine" ||
5938 Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt"))) {
59375939 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
59385940 if (CC != ~0U) {
59395941 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
59745976 }
59755977 }
59765978
5977 if (isMnemonicVPTPredicable(Mnemonic, ExtraToken)) {
5979 if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
5980 Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
5981 Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
5982 Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt") {
59785983 unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
59795984 if (CC != ~0U) {
59805985 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
65086513 }
65096514
65106515 // Add the VPT predication code operand, if necessary.
6511 if (CanAcceptVPTPredicationCode) {
6516 // FIXME: We don't add them for the instructions filtered below as these can
6517 // have custom operands which need special parsing. This parsing requires
6518 // the operand to be in the same place in the OperandVector as their
6519 // definition in tblgen. Since these instructions may also have the
6520 // scalar predication operand we do not add the vector one and leave until
6521 // now to fix it up.
6522 if (CanAcceptVPTPredicationCode && Mnemonic != "vmov") {
65126523 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
65136524 CarrySetting);
65146525 Operands.push_back(ARMOperand::CreateVPTPred(
65926603
65936604
65946605 if (hasMVE()) {
6595 if (CanAcceptVPTPredicationCode) {
6606 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) &&
6607 Mnemonic == "vmov" && PredicationCode == ARMCC::LT) {
6608 // Very nasty hack to deal with the vector predicated variant of vmovlt
6609 // the scalar predicated vmov with condition 'lt'. We can not tell them
6610 // apart until we have parsed their operands.
6611 Operands.erase(Operands.begin() + 1);
6612 Operands.erase(Operands.begin());
6613 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
6614 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
6615 Mnemonic.size() - 1 + CarrySetting);
6616 Operands.insert(Operands.begin(),
6617 ARMOperand::CreateVPTPred(ARMVCC::None, PLoc));
6618 Operands.insert(Operands.begin(),
6619 ARMOperand::CreateToken(StringRef("vmovlt"), MLoc));
6620 } else if (CanAcceptVPTPredicationCode) {
65966621 // For all other instructions, make sure only one of the two
65976622 // predication operands is left behind, depending on whether we should
65986623 // use the vector predication.
1124311268 if (CE->getValue() == 0)
1124411269 return Match_Success;
1124511270 break;
11271 case MCK__35_8:
11272 if (Op.isImm())
11273 if (const MCConstantExpr *CE = dyn_cast(Op.getImm()))
11274 if (CE->getValue() == 8)
11275 return Match_Success;
11276 break;
11277 case MCK__35_16:
11278 if (Op.isImm())
11279 if (const MCConstantExpr *CE = dyn_cast(Op.getImm()))
11280 if (CE->getValue() == 16)
11281 return Match_Success;
11282 break;
1124611283 case MCK_ModImm:
1124711284 if (Op.isImm()) {
1124811285 const MCExpr *SOExpr = Op.getImm();
165165 SmallVectorImpl &Fixups,
166166 const MCSubtargetInfo &STI) const;
167167
168 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
169 /// operand.
170 uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
171 SmallVectorImpl &Fixups,
172 const MCSubtargetInfo &STI) const;
173
168174 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
169175 /// operand.
170176 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
902908 return (Rm << 3) | Rn;
903909 }
904910
911 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
912 /// operand.
913 uint32_t
914 ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
915 SmallVectorImpl &Fixups,
916 const MCSubtargetInfo &STI) const {
917 // {4-0} = szimm5
918 // The value we are trying to encode is an immediate between either the
919 // range of [1-7] or [1-15] depending on whether we are dealing with the
920 // u8/s8 or the u16/s16 variants respectively.
921 // This value is encoded as follows, if ShiftImm is the value within those
922 // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
923 // or 16.
924
925 unsigned Size, ShiftImm;
926 switch(MI.getOpcode()) {
927 case ARM::MVE_VSHLL_imms16bh:
928 case ARM::MVE_VSHLL_imms16th:
929 case ARM::MVE_VSHLL_immu16bh:
930 case ARM::MVE_VSHLL_immu16th:
931 Size = 16;
932 break;
933 case ARM::MVE_VSHLL_imms8bh:
934 case ARM::MVE_VSHLL_imms8th:
935 case ARM::MVE_VSHLL_immu8bh:
936 case ARM::MVE_VSHLL_immu8th:
937 Size = 8;
938 break;
939 default:
940 llvm_unreachable("Use of operand not supported by this instruction");
941 }
942 ShiftImm = MI.getOperand(OpIdx).getImm();
943 return Size + ShiftImm;
944 }
945
905946 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
906947 uint32_t ARMMCCodeEmitter::
907948 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
0 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \
1 # RUN: | FileCheck --check-prefix=CHECK-NOFP %s
2 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
3 # RUN: | FileCheck --check-prefix=CHECK %s
4 # RUN: FileCheck --check-prefix=ERROR < %t %s
5
6 # CHECK: vshlc q0, lr, #8 @ encoding: [0xa8,0xee,0xce,0x0f]
7 # CHECK-NOFP: vshlc q0, lr, #8 @ encoding: [0xa8,0xee,0xce,0x0f]
8 vshlc q0, lr, #8
9
10 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
11 vshlc q0, lr, #33
12
13 # CHECK: vmovlb.s8 q0, q6 @ encoding: [0xa8,0xee,0x4c,0x0f]
14 # CHECK-NOFP: vmovlb.s8 q0, q6 @ encoding: [0xa8,0xee,0x4c,0x0f]
15 vmovlb.s8 q0, q6
16
17 # CHECK: vmovlt.s8 q0, q4 @ encoding: [0xa8,0xee,0x48,0x1f]
18 # CHECK-NOFP: vmovlt.s8 q0, q4 @ encoding: [0xa8,0xee,0x48,0x1f]
19 vmovlt.s8 q0, q4
20
21 # CHECK: vpt.i8 eq, q0, q0
22 # CHECK-NOFP: vpt.i8 eq, q0, q0
23 # CHECK: vmovltt.s8 q0, q4 @ encoding: [0xa8,0xee,0x48,0x1f]
24 # CHECK-NOFP: vmovltt.s8 q0, q4 @ encoding: [0xa8,0xee,0x48,0x1f]
25 vpt.i8 eq, q0, q0
26 vmovltt.s8 q0, q4
27
28 # CHECK: vmovlb.u8 q0, q0 @ encoding: [0xa8,0xfe,0x40,0x0f]
29 # CHECK-NOFP: vmovlb.u8 q0, q0 @ encoding: [0xa8,0xfe,0x40,0x0f]
30 vmovlb.u8 q0, q0
31
32 # CHECK: vmovlt.u8 q0, q2 @ encoding: [0xa8,0xfe,0x44,0x1f]
33 # CHECK-NOFP: vmovlt.u8 q0, q2 @ encoding: [0xa8,0xfe,0x44,0x1f]
34 vmovlt.u8 q0, q2
35
36 # CHECK: vmovlb.u16 q1, q0 @ encoding: [0xb0,0xfe,0x40,0x2f]
37 # CHECK-NOFP: vmovlb.u16 q1, q0 @ encoding: [0xb0,0xfe,0x40,0x2f]
38 vmovlb.u16 q1, q0
39
40 # CHECK: vmovlt.u16 q0, q2 @ encoding: [0xb0,0xfe,0x44,0x1f]
41 # CHECK-NOFP: vmovlt.u16 q0, q2 @ encoding: [0xb0,0xfe,0x44,0x1f]
42 vmovlt.u16 q0, q2
43
44 # CHECK: vshllb.s8 q0, q2, #8 @ encoding: [0x31,0xee,0x05,0x0e]
45 # CHECK-NOFP: vshllb.s8 q0, q2, #8 @ encoding: [0x31,0xee,0x05,0x0e]
46 vshllb.s8 q0, q2, #8
47
48 # CHECK: vshllt.s8 q1, q5, #8 @ encoding: [0x31,0xee,0x0b,0x3e]
49 # CHECK-NOFP: vshllt.s8 q1, q5, #8 @ encoding: [0x31,0xee,0x0b,0x3e]
50 vshllt.s8 q1, q5, #8
51
52 # CHECK: vshllb.s8 q0, q0, #7 @ encoding: [0xaf,0xee,0x40,0x0f]
53 # CHECK-NOFP: vshllb.s8 q0, q0, #7 @ encoding: [0xaf,0xee,0x40,0x0f]
54 vshllb.s8 q0, q0, #7
55
56 # CHECK: vshllb.u8 q1, q1, #8 @ encoding: [0x31,0xfe,0x03,0x2e]
57 # CHECK-NOFP: vshllb.u8 q1, q1, #8 @ encoding: [0x31,0xfe,0x03,0x2e]
58 vshllb.u8 q1, q1, #8
59
60 # CHECK: vshllt.u8 q0, q0, #8 @ encoding: [0x31,0xfe,0x01,0x1e]
61 # CHECK-NOFP: vshllt.u8 q0, q0, #8 @ encoding: [0x31,0xfe,0x01,0x1e]
62 vshllt.u8 q0, q0, #8
63
64 # CHECK: vshllb.u8 q0, q0, #3 @ encoding: [0xab,0xfe,0x40,0x0f]
65 # CHECK-NOFP: vshllb.u8 q0, q0, #3 @ encoding: [0xab,0xfe,0x40,0x0f]
66 vshllb.u8 q0, q0, #3
67
68 # CHECK: vshllb.u16 q0, q5, #16 @ encoding: [0x35,0xfe,0x0b,0x0e]
69 # CHECK-NOFP: vshllb.u16 q0, q5, #16 @ encoding: [0x35,0xfe,0x0b,0x0e]
70 vshllb.u16 q0, q5, #16
71
72 # CHECK: vshllt.u16 q0, q3, #16 @ encoding: [0x35,0xfe,0x07,0x1e]
73 # CHECK-NOFP: vshllt.u16 q0, q3, #16 @ encoding: [0x35,0xfe,0x07,0x1e]
74 vshllt.u16 q0, q3, #16
75
76 # CHECK: vshllt.s16 q0, q0, #16 @ encoding: [0x35,0xee,0x01,0x1e]
77 # CHECK-NOFP: vshllt.s16 q0, q0, #16 @ encoding: [0x35,0xee,0x01,0x1e]
78 vshllt.s16 q0, q0, #16
79
80 # CHECK: vshllt.s16 q0, q0, #14 @ encoding: [0xbe,0xee,0x40,0x1f]
81 vshllt.s16 q0, q0, #14
82
83 # CHECK: vshllt.s16 q0, q0, #11 @ encoding: [0xbb,0xee,0x40,0x1f]
84 vshllt.s16 q0, q0, #11
85
86 # CHECK: vshllb.u16 q0, q2, #4 @ encoding: [0xb4,0xfe,0x44,0x0f]
87 # CHECK-NOFP: vshllb.u16 q0, q2, #4 @ encoding: [0xb4,0xfe,0x44,0x0f]
88 vshllb.u16 q0, q2, #4
89
90 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
91 vshllb.s8 q0, q2, #9
92
93 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
94 vshllb.u8 q0, q2, #9
95
96 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
97 vshllb.u8 q0, q2, #0
98
99 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
100 vshllb.s16 q0, q2, #17
101
102 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
103 vshllb.u16 q0, q2, #17
104
105 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
106 vshllb.u16 q0, q2, #0
107
108 # CHECK: vrshrnb.i16 q0, q3, #1 @ encoding: [0x8f,0xfe,0xc7,0x0f]
109 # CHECK-NOFP: vrshrnb.i16 q0, q3, #1 @ encoding: [0x8f,0xfe,0xc7,0x0f]
110 vrshrnb.i16 q0, q3, #1
111
112 # CHECK: vrshrnt.i16 q0, q2, #5 @ encoding: [0x8b,0xfe,0xc5,0x1f]
113 # CHECK-NOFP: vrshrnt.i16 q0, q2, #5 @ encoding: [0x8b,0xfe,0xc5,0x1f]
114 vrshrnt.i16 q0, q2, #5
115
116 # CHECK: vrshrnb.i32 q0, q4, #8 @ encoding: [0x98,0xfe,0xc9,0x0f]
117 # CHECK-NOFP: vrshrnb.i32 q0, q4, #8 @ encoding: [0x98,0xfe,0xc9,0x0f]
118 vrshrnb.i32 q0, q4, #8
119
120 # CHECK: vrshrnt.i32 q0, q2, #7 @ encoding: [0x99,0xfe,0xc5,0x1f]
121 # CHECK-NOFP: vrshrnt.i32 q0, q2, #7 @ encoding: [0x99,0xfe,0xc5,0x1f]
122 vrshrnt.i32 q0, q2, #7
123
124 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
125 vrshrnb.i16 q0, q3, #9
126
127 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
128 vrshrnb.i32 q0, q3, #17
129
130 # CHECK: vshrnb.i16 q1, q2, #1 @ encoding: [0x8f,0xee,0xc5,0x2f]
131 # CHECK-NOFP: vshrnb.i16 q1, q2, #1 @ encoding: [0x8f,0xee,0xc5,0x2f]
132 vshrnb.i16 q1, q2, #1
133
134 # CHECK: vshrnt.i16 q0, q1, #1 @ encoding: [0x8f,0xee,0xc3,0x1f]
135 # CHECK-NOFP: vshrnt.i16 q0, q1, #1 @ encoding: [0x8f,0xee,0xc3,0x1f]
136 vshrnt.i16 q0, q1, #1
137
138 # CHECK: vshrnb.i32 q0, q0, #12 @ encoding: [0x94,0xee,0xc1,0x0f]
139 # CHECK-NOFP: vshrnb.i32 q0, q0, #12 @ encoding: [0x94,0xee,0xc1,0x0f]
140 vshrnb.i32 q0, q0, #12
141
142 # CHECK: vshrnt.i32 q0, q2, #4 @ encoding: [0x9c,0xee,0xc5,0x1f]
143 # CHECK-NOFP: vshrnt.i32 q0, q2, #4 @ encoding: [0x9c,0xee,0xc5,0x1f]
144 vshrnt.i32 q0, q2, #4
145
146 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
147 vshrnb.i16 q1, q2, #9
148
149 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
150 vshrnb.i32 q1, q2, #17
151
152 # CHECK: vqrshrunb.s16 q0, q2, #8 @ encoding: [0x88,0xfe,0xc4,0x0f]
153 # CHECK-NOFP: vqrshrunb.s16 q0, q2, #8 @ encoding: [0x88,0xfe,0xc4,0x0f]
154 vqrshrunb.s16 q0, q2, #8
155
156 # CHECK: vqrshrunt.s16 q0, q0, #6 @ encoding: [0x8a,0xfe,0xc0,0x1f]
157 # CHECK-NOFP: vqrshrunt.s16 q0, q0, #6 @ encoding: [0x8a,0xfe,0xc0,0x1f]
158 vqrshrunt.s16 q0, q0, #6
159
160 # CHECK: vqrshrunt.s32 q0, q1, #8 @ encoding: [0x98,0xfe,0xc2,0x1f]
161 # CHECK-NOFP: vqrshrunt.s32 q0, q1, #8 @ encoding: [0x98,0xfe,0xc2,0x1f]
162 vqrshrunt.s32 q0, q1, #8
163
164 # CHECK: vqrshrunb.s32 q0, q7, #13 @ encoding: [0x93,0xfe,0xce,0x0f]
165 # CHECK-NOFP: vqrshrunb.s32 q0, q7, #13 @ encoding: [0x93,0xfe,0xce,0x0f]
166 vqrshrunb.s32 q0, q7, #13
167
168 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
169 vqrshrunb.s16 q0, q2, #9
170
171 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
172 vqrshrunb.s32 q0, q2, #17
173
174 # CHECK: vqshrunb.s16 q0, q7, #5 @ encoding: [0x8b,0xee,0xce,0x0f]
175 # CHECK-NOFP: vqshrunb.s16 q0, q7, #5 @ encoding: [0x8b,0xee,0xce,0x0f]
176 vqshrunb.s16 q0, q7, #5
177
178 # CHECK: vqshrunt.s16 q0, q1, #7 @ encoding: [0x89,0xee,0xc2,0x1f]
179 # CHECK-NOFP: vqshrunt.s16 q0, q1, #7 @ encoding: [0x89,0xee,0xc2,0x1f]
180 vqshrunt.s16 q0, q1, #7
181
182 # CHECK: vqshrunb.s32 q0, q6, #4 @ encoding: [0x9c,0xee,0xcc,0x0f]
183 # CHECK-NOFP: vqshrunb.s32 q0, q6, #4 @ encoding: [0x9c,0xee,0xcc,0x0f]
184 vqshrunb.s32 q0, q6, #4
185
186 # CHECK: vqshrunt.s32 q0, q2, #10 @ encoding: [0x96,0xee,0xc4,0x1f]
187 # CHECK-NOFP: vqshrunt.s32 q0, q2, #10 @ encoding: [0x96,0xee,0xc4,0x1f]
188 vqshrunt.s32 q0, q2, #10
189
190 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
191 vqshrunt.s16 q0, q1, #9
192
193 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
194 vqshrunb.s32 q0, q6, #17
195
196 # CHECK: vqrshrnb.s16 q0, q7, #8 @ encoding: [0x88,0xee,0x4f,0x0f]
197 # CHECK-NOFP: vqrshrnb.s16 q0, q7, #8 @ encoding: [0x88,0xee,0x4f,0x0f]
198 vqrshrnb.s16 q0, q7, #8
199
200 # CHECK: vqrshrnt.u16 q1, q3, #4 @ encoding: [0x8c,0xfe,0x47,0x3f]
201 # CHECK-NOFP: vqrshrnt.u16 q1, q3, #4 @ encoding: [0x8c,0xfe,0x47,0x3f]
202 vqrshrnt.u16 q1, q3, #4
203
204 # CHECK: vqrshrnb.u32 q0, q1, #7 @ encoding: [0x99,0xfe,0x43,0x0f]
205 # CHECK-NOFP: vqrshrnb.u32 q0, q1, #7 @ encoding: [0x99,0xfe,0x43,0x0f]
206 vqrshrnb.u32 q0, q1, #7
207
208 # CHECK: vqrshrnt.s32 q0, q1, #11 @ encoding: [0x95,0xee,0x43,0x1f]
209 # CHECK-NOFP: vqrshrnt.s32 q0, q1, #11 @ encoding: [0x95,0xee,0x43,0x1f]
210 vqrshrnt.s32 q0, q1, #11
211
212 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
213 vqrshrnb.s16 q0, q7, #9
214
215 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
216 vqrshrnb.s32 q0, q7, #17
217
218 # CHECK: vqshrnb.s16 q0, q6, #5 @ encoding: [0x8b,0xee,0x4c,0x0f]
219 # CHECK-NOFP: vqshrnb.s16 q0, q6, #5 @ encoding: [0x8b,0xee,0x4c,0x0f]
220 vqshrnb.s16 q0, q6, #5
221
222 # CHECK: vqshrnt.s16 q0, q1, #4 @ encoding: [0x8c,0xee,0x42,0x1f]
223 # CHECK-NOFP: vqshrnt.s16 q0, q1, #4 @ encoding: [0x8c,0xee,0x42,0x1f]
224 vqshrnt.s16 q0, q1, #4
225
226 # CHECK: vqshrnb.u16 q0, q3, #7 @ encoding: [0x89,0xfe,0x46,0x0f]
227 # CHECK-NOFP: vqshrnb.u16 q0, q3, #7 @ encoding: [0x89,0xfe,0x46,0x0f]
228 vqshrnb.u16 q0, q3, #7
229
230 # CHECK: vqshrnt.u16 q0, q2, #8 @ encoding: [0x88,0xfe,0x44,0x1f]
231 # CHECK-NOFP: vqshrnt.u16 q0, q2, #8 @ encoding: [0x88,0xfe,0x44,0x1f]
232 vqshrnt.u16 q0, q2, #8
233
234 # CHECK: vqshrnt.s32 q1, q4, #3 @ encoding: [0x9d,0xee,0x48,0x3f]
235 # CHECK-NOFP: vqshrnt.s32 q1, q4, #3 @ encoding: [0x9d,0xee,0x48,0x3f]
236 vqshrnt.s32 q1, q4, #3
237
238 # CHECK: vqshrnb.u32 q0, q2, #14 @ encoding: [0x92,0xfe,0x44,0x0f]
239 # CHECK-NOFP: vqshrnb.u32 q0, q2, #14 @ encoding: [0x92,0xfe,0x44,0x0f]
240 vqshrnb.u32 q0, q2, #14
241
242 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
243 vqshrnb.s16 q0, q6, #9
244
245 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
246 vqshrnb.u32 q0, q6, #17
247
248 # CHECK: vshl.s8 q6, q6, q6 @ encoding: [0x0c,0xef,0x4c,0xc4]
249 # CHECK-NOFP: vshl.s8 q6, q6, q6 @ encoding: [0x0c,0xef,0x4c,0xc4]
250 vshl.s8 q6, q6, q6
251
252 # CHECK: vshl.s16 q0, q4, q2 @ encoding: [0x14,0xef,0x48,0x04]
253 # CHECK-NOFP: vshl.s16 q0, q4, q2 @ encoding: [0x14,0xef,0x48,0x04]
254 vshl.s16 q0, q4, q2
255
256 # CHECK: vshl.s32 q1, q1, q5 @ encoding: [0x2a,0xef,0x42,0x24]
257 # CHECK-NOFP: vshl.s32 q1, q1, q5 @ encoding: [0x2a,0xef,0x42,0x24]
258 vshl.s32 q1, q1, q5
259
260 # CHECK: vshl.u8 q1, q7, q2 @ encoding: [0x04,0xff,0x4e,0x24]
261 # CHECK-NOFP: vshl.u8 q1, q7, q2 @ encoding: [0x04,0xff,0x4e,0x24]
262 vshl.u8 q1, q7, q2
263
264 # CHECK: vshl.u16 q0, q4, q0 @ encoding: [0x10,0xff,0x48,0x04]
265 # CHECK-NOFP: vshl.u16 q0, q4, q0 @ encoding: [0x10,0xff,0x48,0x04]
266 vshl.u16 q0, q4, q0
267
268 # CHECK: vshl.u32 q2, q2, q4 @ encoding: [0x28,0xff,0x44,0x44]
269 # CHECK-NOFP: vshl.u32 q2, q2, q4 @ encoding: [0x28,0xff,0x44,0x44]
270 vshl.u32 q2, q2, q4
271
272 # CHECK: vqshl.s8 q0, q1, q6 @ encoding: [0x0c,0xef,0x52,0x04]
273 # CHECK-NOFP: vqshl.s8 q0, q1, q6 @ encoding: [0x0c,0xef,0x52,0x04]
274 vqshl.s8 q0, q1, q6
275
276 # CHECK: vqshl.s16 q4, q3, q7 @ encoding: [0x1e,0xef,0x56,0x84]
277 # CHECK-NOFP: vqshl.s16 q4, q3, q7 @ encoding: [0x1e,0xef,0x56,0x84]
278 vqshl.s16 q4, q3, q7
279
280 # CHECK: vqshl.s32 q0, q5, q5 @ encoding: [0x2a,0xef,0x5a,0x04]
281 # CHECK-NOFP: vqshl.s32 q0, q5, q5 @ encoding: [0x2a,0xef,0x5a,0x04]
282 vqshl.s32 q0, q5, q5
283
284 # CHECK: vqshl.u8 q0, q0, q6 @ encoding: [0x0c,0xff,0x50,0x04]
285 # CHECK-NOFP: vqshl.u8 q0, q0, q6 @ encoding: [0x0c,0xff,0x50,0x04]
286 vqshl.u8 q0, q0, q6
287
288 # CHECK: vqshl.u16 q0, q5, q4 @ encoding: [0x18,0xff,0x5a,0x04]
289 # CHECK-NOFP: vqshl.u16 q0, q5, q4 @ encoding: [0x18,0xff,0x5a,0x04]
290 vqshl.u16 q0, q5, q4
291
292 # CHECK: vqshl.u32 q1, q0, q4 @ encoding: [0x28,0xff,0x50,0x24]
293 # CHECK-NOFP: vqshl.u32 q1, q0, q4 @ encoding: [0x28,0xff,0x50,0x24]
294 vqshl.u32 q1, q0, q4
295
296 # CHECK: vqrshl.s8 q1, q6, q1 @ encoding: [0x02,0xef,0x5c,0x25]
297 # CHECK-NOFP: vqrshl.s8 q1, q6, q1 @ encoding: [0x02,0xef,0x5c,0x25]
298 vqrshl.s8 q1, q6, q1
299
300 # CHECK: vqrshl.s16 q2, q4, q6 @ encoding: [0x1c,0xef,0x58,0x45]
301 # CHECK-NOFP: vqrshl.s16 q2, q4, q6 @ encoding: [0x1c,0xef,0x58,0x45]
302 vqrshl.s16 q2, q4, q6
303
304 # CHECK: vqrshl.s32 q0, q0, q5 @ encoding: [0x2a,0xef,0x50,0x05]
305 # CHECK-NOFP: vqrshl.s32 q0, q0, q5 @ encoding: [0x2a,0xef,0x50,0x05]
306 vqrshl.s32 q0, q0, q5
307
308 # CHECK: vqrshl.u8 q0, q2, q1 @ encoding: [0x02,0xff,0x54,0x05]
309 # CHECK-NOFP: vqrshl.u8 q0, q2, q1 @ encoding: [0x02,0xff,0x54,0x05]
310 vqrshl.u8 q0, q2, q1
311
312 # CHECK: vqrshl.u16 q1, q6, q0 @ encoding: [0x10,0xff,0x5c,0x25]
313 # CHECK-NOFP: vqrshl.u16 q1, q6, q0 @ encoding: [0x10,0xff,0x5c,0x25]
314 vqrshl.u16 q1, q6, q0
315
316 # CHECK: vqrshl.u32 q0, q0, q0 @ encoding: [0x20,0xff,0x50,0x05]
317 # CHECK-NOFP: vqrshl.u32 q0, q0, q0 @ encoding: [0x20,0xff,0x50,0x05]
318 vqrshl.u32 q0, q0, q0
319
320 # CHECK: vrshl.s8 q0, q6, q4 @ encoding: [0x08,0xef,0x4c,0x05]
321 # CHECK-NOFP: vrshl.s8 q0, q6, q4 @ encoding: [0x08,0xef,0x4c,0x05]
322 vrshl.s8 q0, q6, q4
323
324 # CHECK: vrshl.s16 q1, q4, q7 @ encoding: [0x1e,0xef,0x48,0x25]
325 # CHECK-NOFP: vrshl.s16 q1, q4, q7 @ encoding: [0x1e,0xef,0x48,0x25]
326 vrshl.s16 q1, q4, q7
327
328 # CHECK: vrshl.s32 q1, q4, q4 @ encoding: [0x28,0xef,0x48,0x25]
329 # CHECK-NOFP: vrshl.s32 q1, q4, q4 @ encoding: [0x28,0xef,0x48,0x25]
330 vrshl.s32 q1, q4, q4
331
332 # CHECK: vrshl.u8 q0, q3, q5 @ encoding: [0x0a,0xff,0x46,0x05]
333 # CHECK-NOFP: vrshl.u8 q0, q3, q5 @ encoding: [0x0a,0xff,0x46,0x05]
334 vrshl.u8 q0, q3, q5
335
336 # CHECK: vrshl.u16 q5, q6, q5 @ encoding: [0x1a,0xff,0x4c,0xa5]
337 # CHECK-NOFP: vrshl.u16 q5, q6, q5 @ encoding: [0x1a,0xff,0x4c,0xa5]
338 vrshl.u16 q5, q6, q5
339
340 # CHECK: vrshl.u32 q1, q7, q3 @ encoding: [0x26,0xff,0x4e,0x25]
341 # CHECK-NOFP: vrshl.u32 q1, q7, q3 @ encoding: [0x26,0xff,0x4e,0x25]
342 vrshl.u32 q1, q7, q3
343
344 # CHECK: vsri.8 q0, q2, #3 @ encoding: [0x8d,0xff,0x54,0x04]
345 # CHECK-NOFP: vsri.8 q0, q2, #3 @ encoding: [0x8d,0xff,0x54,0x04]
346 vsri.8 q0, q2, #3
347
348 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
349 vsri.8 q0, q2, #9
350
351 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
352 vsri.8 q0, q2, #0
353
354 # CHECK: vsri.16 q0, q2, #5 @ encoding: [0x9b,0xff,0x54,0x04]
355 # CHECK-NOFP: vsri.16 q0, q2, #5 @ encoding: [0x9b,0xff,0x54,0x04]
356 vsri.16 q0, q2, #5
357
358 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
359 vsri.16 q0, q2, #17
360
361 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
362 vsri.16 q0, q2, #0
363
364 # CHECK: vsri.32 q0, q1, #15 @ encoding: [0xb1,0xff,0x52,0x04]
365 # CHECK-NOFP: vsri.32 q0, q1, #15 @ encoding: [0xb1,0xff,0x52,0x04]
366 vsri.32 q0, q1, #15
367
368 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
369 vsri.32 q0, q2, #33
370
371 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
372 vsri.32 q0, q2, #0
373
374 # CHECK: vsli.8 q0, q3, #3 @ encoding: [0x8b,0xff,0x56,0x05]
375 # CHECK-NOFP: vsli.8 q0, q3, #3 @ encoding: [0x8b,0xff,0x56,0x05]
376 vsli.8 q0, q3, #3
377
378 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
379 vsli.8 q0, q3, #8
380
381 # CHECK: vsli.16 q0, q1, #12 @ encoding: [0x9c,0xff,0x52,0x05]
382 # CHECK-NOFP: vsli.16 q0, q1, #12 @ encoding: [0x9c,0xff,0x52,0x05]
383 vsli.16 q0, q1, #12
384
385 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
386 vsli.16 q0, q3, #16
387
388 # CHECK: vsli.32 q0, q1, #8 @ encoding: [0xa8,0xff,0x52,0x05]
389 # CHECK-NOFP: vsli.32 q0, q1, #8 @ encoding: [0xa8,0xff,0x52,0x05]
390 vsli.32 q0, q1, #8
391
392 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
393 vsli.32 q0, q1, #32
394
395 # CHECK: vqshl.s8 q0, q4, #6 @ encoding: [0x8e,0xef,0x58,0x07]
396 # CHECK-NOFP: vqshl.s8 q0, q4, #6 @ encoding: [0x8e,0xef,0x58,0x07]
397 vqshl.s8 q0, q4, #6
398
399 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
400 vqshl.s8 q0, q4, #8
401
402 # CHECK: vqshl.u8 q0, q6, #6 @ encoding: [0x8e,0xff,0x5c,0x07]
403 # CHECK-NOFP: vqshl.u8 q0, q6, #6 @ encoding: [0x8e,0xff,0x5c,0x07]
404 vqshl.u8 q0, q6, #6
405
406 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
407 vqshl.u8 q0, q4, #8
408
409 # CHECK: vqshl.s16 q1, q2, #5 @ encoding: [0x95,0xef,0x54,0x27]
410 # CHECK-NOFP: vqshl.s16 q1, q2, #5 @ encoding: [0x95,0xef,0x54,0x27]
411 vqshl.s16 q1, q2, #5
412
413 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
414 vqshl.s16 q1, q2, #16
415
416 # CHECK: vqshl.u16 q0, q5, #3 @ encoding: [0x93,0xff,0x5a,0x07]
417 # CHECK-NOFP: vqshl.u16 q0, q5, #3 @ encoding: [0x93,0xff,0x5a,0x07]
418 vqshl.u16 q0, q5, #3
419
420 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
421 vqshl.u16 q1, q2, #16
422
423 # CHECK: vqshl.s32 q1, q3, #29 @ encoding: [0xbd,0xef,0x56,0x27]
424 # CHECK-NOFP: vqshl.s32 q1, q3, #29 @ encoding: [0xbd,0xef,0x56,0x27]
425 vqshl.s32 q1, q3, #29
426
427 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
428 vqshl.s32 q1, q3, #32
429
430 # CHECK: vqshl.u32 q0, q2, #19 @ encoding: [0xb3,0xff,0x54,0x07]
431 # CHECK-NOFP: vqshl.u32 q0, q2, #19 @ encoding: [0xb3,0xff,0x54,0x07]
432 vqshl.u32 q0, q2, #19
433
434 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
435 vqshl.u32 q0, q2, #32
436
437 # CHECK: vqshlu.s8 q0, q1, #0 @ encoding: [0x88,0xff,0x52,0x06]
438 # CHECK-NOFP: vqshlu.s8 q0, q1, #0 @ encoding: [0x88,0xff,0x52,0x06]
439 vqshlu.s8 q0, q1, #0
440
441 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
442 vqshlu.s8 q0, q1, #8
443
444 # CHECK: vqshlu.s16 q2, q1, #12 @ encoding: [0x9c,0xff,0x52,0x46]
445 # CHECK-NOFP: vqshlu.s16 q2, q1, #12 @ encoding: [0x9c,0xff,0x52,0x46]
446 vqshlu.s16 q2, q1, #12
447
448 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
449 vqshlu.s16 q0, q1, #16
450
451 # CHECK: vqshlu.s32 q0, q4, #26 @ encoding: [0xba,0xff,0x58,0x06]
452 # CHECK-NOFP: vqshlu.s32 q0, q4, #26 @ encoding: [0xba,0xff,0x58,0x06]
453 vqshlu.s32 q0, q4, #26
454
455 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
456 vqshlu.s32 q0, q1, #32
457
458 # CHECK: vrshr.s8 q1, q3, #7 @ encoding: [0x89,0xef,0x56,0x22]
459 # CHECK-NOFP: vrshr.s8 q1, q3, #7 @ encoding: [0x89,0xef,0x56,0x22]
460 vrshr.s8 q1, q3, #7
461
462 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
463 vrshr.s8 q1, q3, #9
464
465 # CHECK: vrshr.u8 q1, q3, #2 @ encoding: [0x8e,0xff,0x56,0x22]
466 # CHECK-NOFP: vrshr.u8 q1, q3, #2 @ encoding: [0x8e,0xff,0x56,0x22]
467 vrshr.u8 q1, q3, #2
468
469 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
470 vrshr.u8 q1, q3, #9
471
472 # CHECK: vrshr.s16 q0, q1, #10 @ encoding: [0x96,0xef,0x52,0x02]
473 # CHECK-NOFP: vrshr.s16 q0, q1, #10 @ encoding: [0x96,0xef,0x52,0x02]
474 vrshr.s16 q0, q1, #10
475
476 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
477 vrshr.s16 q0, q1, #17
478
479 # CHECK: vrshr.u16 q0, q5, #12 @ encoding: [0x94,0xff,0x5a,0x02]
480 # CHECK-NOFP: vrshr.u16 q0, q5, #12 @ encoding: [0x94,0xff,0x5a,0x02]
481 vrshr.u16 q0, q5, #12
482
483 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
484 vrshr.u16 q0, q5, #20
485
486 # CHECK: vrshr.s32 q0, q5, #23 @ encoding: [0xa9,0xef,0x5a,0x02]
487 # CHECK-NOFP: vrshr.s32 q0, q5, #23 @ encoding: [0xa9,0xef,0x5a,0x02]
488 vrshr.s32 q0, q5, #23
489
490 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
491 vrshr.s32 q0, q5, #33
492
493 # CHECK: vrshr.u32 q0, q1, #30 @ encoding: [0xa2,0xff,0x52,0x02]
494 # CHECK-NOFP: vrshr.u32 q0, q1, #30 @ encoding: [0xa2,0xff,0x52,0x02]
495 vrshr.u32 q0, q1, #30
496
497 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
498 vrshr.u32 q0, q1, #55
499
500 # CHECK: vshr.s8 q0, q7, #4 @ encoding: [0x8c,0xef,0x5e,0x00]
501 # CHECK-NOFP: vshr.s8 q0, q7, #4 @ encoding: [0x8c,0xef,0x5e,0x00]
502 vshr.s8 q0, q7, #4
503
504 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
505 vshr.s8 q0, q7, #9
506
507 # CHECK: vshr.u8 q0, q2, #5 @ encoding: [0x8b,0xff,0x54,0x00]
508 # CHECK-NOFP: vshr.u8 q0, q2, #5 @ encoding: [0x8b,0xff,0x54,0x00]
509 vshr.u8 q0, q2, #5
510
511 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
512 vshr.u8 q0, q2, #9
513
514 # CHECK: vshr.s16 q0, q3, #16 @ encoding: [0x90,0xef,0x56,0x00]
515 # CHECK-NOFP: vshr.s16 q0, q3, #16 @ encoding: [0x90,0xef,0x56,0x00]
516 vshr.s16 q0, q3, #16
517
518 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
519 vshr.s16 q0, q2, #17
520
521 # CHECK: vshr.u16 q7, q6, #8 @ encoding: [0x98,0xff,0x5c,0xe0]
522 # CHECK-NOFP: vshr.u16 q7, q6, #8 @ encoding: [0x98,0xff,0x5c,0xe0]
523 vshr.u16 q7, q6, #8
524
525 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
526 vshr.u16 q7, q6, #20
527
528 # CHECK: vshr.s32 q0, q6, #24 @ encoding: [0xa8,0xef,0x5c,0x00]
529 # CHECK-NOFP: vshr.s32 q0, q6, #24 @ encoding: [0xa8,0xef,0x5c,0x00]
530 vshr.s32 q0, q6, #24
531
532 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
533 vshr.s32 q0, q6, #33
534
535 # CHECK: vshr.u32 q2, q5, #30 @ encoding: [0xa2,0xff,0x5a,0x40]
536 # CHECK-NOFP: vshr.u32 q2, q5, #30 @ encoding: [0xa2,0xff,0x5a,0x40]
537 vshr.u32 q2, q5, #30
538
539 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
540 vshr.u32 q2, q5, #33
541
542 # CHECK: vshl.i8 q0, q6, #6 @ encoding: [0x8e,0xef,0x5c,0x05]
543 # CHECK-NOFP: vshl.i8 q0, q6, #6 @ encoding: [0x8e,0xef,0x5c,0x05]
544 vshl.i8 q0, q6, #6
545
546 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
547 vshl.i8 q0, q6, #8
548
549 # CHECK: vshl.i16 q1, q0, #12 @ encoding: [0x9c,0xef,0x50,0x25]
550 # CHECK-NOFP: vshl.i16 q1, q0, #12 @ encoding: [0x9c,0xef,0x50,0x25]
551 vshl.i16 q1, q0, #12
552
553 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
554 vshl.i16 q1, q0, #16
555
556 # CHECK: vshl.i32 q2, q2, #26 @ encoding: [0xba,0xef,0x54,0x45]
557 # CHECK-NOFP: vshl.i32 q2, q2, #26 @ encoding: [0xba,0xef,0x54,0x45]
558 vshl.i32 q2, q2, #26
559
560 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
561 vshl.i32 q2, q2, #33
562
563 vshllt.s8 q0, q1, #1
564 # CHECK: vshllt.s8 q0, q1, #1 @ encoding: [0xa9,0xee,0x42,0x1f]
565 # CHECK-NOFP: vshllt.s8 q0, q1, #1 @ encoding: [0xa9,0xee,0x42,0x1f]
566
567 vpste
568 vshlltt.s16 q0, q1, #4
569 vshllbe.u16 q0, q1, #8
570 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
571 # CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
572 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
573 # CHECK-NOFP: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
574 # CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
575 # CHECK-NOFP: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
0 # RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
1 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
2 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
3
4 # CHECK: vshlc q0, lr, #8 @ encoding: [0xa8,0xee,0xce,0x0f]
5 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
6 [0xa8,0xee,0xce,0x0f]
7
8 # CHECK: vmovlb.s8 q0, q6 @ encoding: [0xa8,0xee,0x4c,0x0f]
9 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
10 [0xa8,0xee,0x4c,0x0f]
11
12 # CHECK: vmovlt.s8 q0, q4 @ encoding: [0xa8,0xee,0x48,0x1f]
13 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
14 [0xa8,0xee,0x48,0x1f]
15
16 # CHECK: vmovlb.u8 q0, q0 @ encoding: [0xa8,0xfe,0x40,0x0f]
17 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
18 [0xa8,0xfe,0x40,0x0f]
19
20 # CHECK: vmovlt.u8 q0, q2 @ encoding: [0xa8,0xfe,0x44,0x1f]
21 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
22 [0xa8,0xfe,0x44,0x1f]
23
24 # CHECK: vmovlb.u16 q1, q0 @ encoding: [0xb0,0xfe,0x40,0x2f]
25 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
26 [0xb0,0xfe,0x40,0x2f]
27
28 # CHECK: vmovlt.u16 q0, q2 @ encoding: [0xb0,0xfe,0x44,0x1f]
29 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
30 [0xb0,0xfe,0x44,0x1f]
31
32 # CHECK: vshllb.s8 q0, q2, #8 @ encoding: [0x31,0xee,0x05,0x0e]
33 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
34 [0x31,0xee,0x05,0x0e]
35
36 # CHECK: vshllt.s8 q1, q5, #8 @ encoding: [0x31,0xee,0x0b,0x3e]
37 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
38 [0x31,0xee,0x0b,0x3e]
39
40 # CHECK: vshllb.s8 q0, q0, #7 @ encoding: [0xaf,0xee,0x40,0x0f]
41 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
42 [0xaf,0xee,0x40,0x0f]
43
44 # CHECK: vshllb.u8 q1, q1, #8 @ encoding: [0x31,0xfe,0x03,0x2e]
45 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
46 [0x31,0xfe,0x03,0x2e]
47
48 # CHECK: vshllt.u8 q0, q0, #8 @ encoding: [0x31,0xfe,0x01,0x1e]
49 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
50 [0x31,0xfe,0x01,0x1e]
51
52 # CHECK: vshllb.u8 q0, q0, #3 @ encoding: [0xab,0xfe,0x40,0x0f]
53 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
54 [0xab,0xfe,0x40,0x0f]
55
56 # CHECK: vshllb.u16 q0, q5, #16 @ encoding: [0x35,0xfe,0x0b,0x0e]
57 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
58 [0x35,0xfe,0x0b,0x0e]
59
60 # CHECK: vshllt.u16 q0, q3, #16 @ encoding: [0x35,0xfe,0x07,0x1e]
61 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
62 [0x35,0xfe,0x07,0x1e]
63
64 # CHECK: vshllt.s16 q0, q0, #16 @ encoding: [0x35,0xee,0x01,0x1e]
65 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
66 [0x35,0xee,0x01,0x1e]
67
68 # CHECK: vshllt.s16 q0, q0, #14 @ encoding: [0xbe,0xee,0x40,0x1f]
69 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
70 [0xbe,0xee,0x40,0x1f]
71
72 # CHECK: vshllt.s16 q0, q0, #11 @ encoding: [0xbb,0xee,0x40,0x1f]
73 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
74 [0xbb,0xee,0x40,0x1f]
75
76 # CHECK: vshllb.u16 q0, q2, #4 @ encoding: [0xb4,0xfe,0x44,0x0f]
77 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
78 [0xb4,0xfe,0x44,0x0f]
79
80 # CHECK: vrshrnb.i16 q0, q3, #1 @ encoding: [0x8f,0xfe,0xc7,0x0f]
81 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
82 [0x8f,0xfe,0xc7,0x0f]
83
84 # CHECK: vrshrnt.i16 q0, q2, #5 @ encoding: [0x8b,0xfe,0xc5,0x1f]
85 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
86 [0x8b,0xfe,0xc5,0x1f]
87
88 # CHECK: vrshrnb.i32 q0, q4, #8 @ encoding: [0x98,0xfe,0xc9,0x0f]
89 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
90 [0x98,0xfe,0xc9,0x0f]
91
92 # CHECK: vrshrnt.i32 q0, q2, #7 @ encoding: [0x99,0xfe,0xc5,0x1f]
93 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
94 [0x99,0xfe,0xc5,0x1f]
95
96 # CHECK: vshrnb.i16 q1, q2, #1 @ encoding: [0x8f,0xee,0xc5,0x2f]
97 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
98 [0x8f,0xee,0xc5,0x2f]
99
100 # CHECK: vshrnt.i16 q0, q1, #1 @ encoding: [0x8f,0xee,0xc3,0x1f]
101 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
102 [0x8f,0xee,0xc3,0x1f]
103
104 # CHECK: vshrnb.i32 q0, q0, #12 @ encoding: [0x94,0xee,0xc1,0x0f]
105 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
106 [0x94,0xee,0xc1,0x0f]
107
108 # CHECK: vshrnt.i32 q0, q2, #4 @ encoding: [0x9c,0xee,0xc5,0x1f]
109 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
110 [0x9c,0xee,0xc5,0x1f]
111
112 # CHECK: vqrshrunb.s16 q0, q2, #8 @ encoding: [0x88,0xfe,0xc4,0x0f]
113 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
114 [0x88,0xfe,0xc4,0x0f]
115
116 # CHECK: vqrshrunt.s16 q0, q0, #6 @ encoding: [0x8a,0xfe,0xc0,0x1f]
117 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
118 [0x8a,0xfe,0xc0,0x1f]
119
120 # CHECK: vqrshrunt.s32 q0, q1, #8 @ encoding: [0x98,0xfe,0xc2,0x1f]
121 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
122 [0x98,0xfe,0xc2,0x1f]
123
124 # CHECK: vqrshrunb.s32 q0, q7, #13 @ encoding: [0x93,0xfe,0xce,0x0f]
125 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
126 [0x93,0xfe,0xce,0x0f]
127
128 # CHECK: vqshrunb.s16 q0, q7, #5 @ encoding: [0x8b,0xee,0xce,0x0f]
129 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
130 [0x8b,0xee,0xce,0x0f]
131
132 # CHECK: vqshrunt.s16 q0, q1, #7 @ encoding: [0x89,0xee,0xc2,0x1f]
133 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
134 [0x89,0xee,0xc2,0x1f]
135
136 # CHECK: vqshrunb.s32 q0, q6, #4 @ encoding: [0x9c,0xee,0xcc,0x0f]
137 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
138 [0x9c,0xee,0xcc,0x0f]
139
140 # CHECK: vqshrunt.s32 q0, q2, #10 @ encoding: [0x96,0xee,0xc4,0x1f]
141 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
142 [0x96,0xee,0xc4,0x1f]
143
144 # CHECK: vqrshrnb.s16 q0, q7, #8 @ encoding: [0x88,0xee,0x4f,0x0f]
145 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
146 [0x88,0xee,0x4f,0x0f]
147
148 # CHECK: vqrshrnt.u16 q1, q3, #4 @ encoding: [0x8c,0xfe,0x47,0x3f]
149 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
150 [0x8c,0xfe,0x47,0x3f]
151
152 # CHECK: vqrshrnb.u32 q0, q1, #7 @ encoding: [0x99,0xfe,0x43,0x0f]
153 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
154 [0x99,0xfe,0x43,0x0f]
155
156 # CHECK: vqrshrnt.s32 q0, q1, #11 @ encoding: [0x95,0xee,0x43,0x1f]
157 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
158 [0x95,0xee,0x43,0x1f]
159
160 # CHECK: vqshrnb.s16 q0, q6, #5 @ encoding: [0x8b,0xee,0x4c,0x0f]
161 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
162 [0x8b,0xee,0x4c,0x0f]
163
164 # CHECK: vqshrnt.s16 q0, q1, #4 @ encoding: [0x8c,0xee,0x42,0x1f]
165 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
166 [0x8c,0xee,0x42,0x1f]
167
168 # CHECK: vqshrnb.u16 q0, q3, #7 @ encoding: [0x89,0xfe,0x46,0x0f]
169 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
170 [0x89,0xfe,0x46,0x0f]
171
172 # CHECK: vqshrnt.u16 q0, q2, #8 @ encoding: [0x88,0xfe,0x44,0x1f]
173 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
174 [0x88,0xfe,0x44,0x1f]
175
176 # CHECK: vqshrnt.s32 q1, q4, #3 @ encoding: [0x9d,0xee,0x48,0x3f]
177 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
178 [0x9d,0xee,0x48,0x3f]
179
180 # CHECK: vqshrnb.u32 q0, q2, #14 @ encoding: [0x92,0xfe,0x44,0x0f]
181 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
182 [0x92,0xfe,0x44,0x0f]
183
184 # CHECK: vshl.s8 q6, q6, q6 @ encoding: [0x0c,0xef,0x4c,0xc4]
185 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
186 [0x0c,0xef,0x4c,0xc4]
187
188 # CHECK: vshl.s16 q0, q4, q2 @ encoding: [0x14,0xef,0x48,0x04]
189 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
190 [0x14,0xef,0x48,0x04]
191
192 # CHECK: vshl.s32 q1, q1, q5 @ encoding: [0x2a,0xef,0x42,0x24]
193 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
194 [0x2a,0xef,0x42,0x24]
195
196 # CHECK: vshl.u8 q1, q7, q2 @ encoding: [0x04,0xff,0x4e,0x24]
197 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
198 [0x04,0xff,0x4e,0x24]
199
200 # CHECK: vshl.u16 q0, q4, q0 @ encoding: [0x10,0xff,0x48,0x04]
201 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
202 [0x10,0xff,0x48,0x04]
203
204 # CHECK: vshl.u32 q2, q2, q4 @ encoding: [0x28,0xff,0x44,0x44]
205 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
206 [0x28,0xff,0x44,0x44]
207
208 # CHECK: vqshl.s8 q0, q1, q6 @ encoding: [0x0c,0xef,0x52,0x04]
209 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
210 [0x0c,0xef,0x52,0x04]
211
212 # CHECK: vqshl.s16 q4, q3, q7 @ encoding: [0x1e,0xef,0x56,0x84]
213 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
214 [0x1e,0xef,0x56,0x84]
215
216 # CHECK: vqshl.s32 q0, q5, q5 @ encoding: [0x2a,0xef,0x5a,0x04]
217 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
218 [0x2a,0xef,0x5a,0x04]
219
220 # CHECK: vqshl.u8 q0, q0, q6 @ encoding: [0x0c,0xff,0x50,0x04]
221 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
222 [0x0c,0xff,0x50,0x04]
223
224 # CHECK: vqshl.u16 q0, q5, q4 @ encoding: [0x18,0xff,0x5a,0x04]
225 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
226 [0x18,0xff,0x5a,0x04]
227
228 # CHECK: vqshl.u32 q1, q0, q4 @ encoding: [0x28,0xff,0x50,0x24]
229 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
230 [0x28,0xff,0x50,0x24]
231
232 # CHECK: vqrshl.s8 q1, q6, q1 @ encoding: [0x02,0xef,0x5c,0x25]
233 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
234 [0x02,0xef,0x5c,0x25]
235
236 # CHECK: vqrshl.s16 q2, q4, q6 @ encoding: [0x1c,0xef,0x58,0x45]
237 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
238 [0x1c,0xef,0x58,0x45]
239
240 # CHECK: vqrshl.s32 q0, q0, q5 @ encoding: [0x2a,0xef,0x50,0x05]
241 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
242 [0x2a,0xef,0x50,0x05]
243
244 # CHECK: vqrshl.u8 q0, q2, q1 @ encoding: [0x02,0xff,0x54,0x05]
245 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
246 [0x02,0xff,0x54,0x05]
247
248 # CHECK: vqrshl.u16 q1, q6, q0 @ encoding: [0x10,0xff,0x5c,0x25]
249 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
250 [0x10,0xff,0x5c,0x25]
251
252 # CHECK: vqrshl.u32 q0, q0, q0 @ encoding: [0x20,0xff,0x50,0x05]
253 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
254 [0x20,0xff,0x50,0x05]
255
256 # CHECK: vrshl.s8 q0, q6, q4 @ encoding: [0x08,0xef,0x4c,0x05]
257 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
258 [0x08,0xef,0x4c,0x05]
259
260 # CHECK: vrshl.s16 q1, q4, q7 @ encoding: [0x1e,0xef,0x48,0x25]
261 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
262 [0x1e,0xef,0x48,0x25]
263
264 # CHECK: vrshl.s32 q1, q4, q4 @ encoding: [0x28,0xef,0x48,0x25]
265 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
266 [0x28,0xef,0x48,0x25]
267
268 # CHECK: vrshl.u8 q0, q3, q5 @ encoding: [0x0a,0xff,0x46,0x05]
269 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
270 [0x0a,0xff,0x46,0x05]
271
272 # CHECK: vrshl.u16 q5, q6, q5 @ encoding: [0x1a,0xff,0x4c,0xa5]
273 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
274 [0x1a,0xff,0x4c,0xa5]
275
276 # CHECK: vrshl.u32 q1, q7, q3 @ encoding: [0x26,0xff,0x4e,0x25]
277 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
278 [0x26,0xff,0x4e,0x25]
279
280 # CHECK: vsri.8 q0, q2, #3 @ encoding: [0x8d,0xff,0x54,0x04]
281 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
282 [0x8d,0xff,0x54,0x04]
283
284 # CHECK: vsri.16 q0, q2, #5 @ encoding: [0x9b,0xff,0x54,0x04]
285 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
286 [0x9b,0xff,0x54,0x04]
287
288 # CHECK: vsri.32 q0, q1, #15 @ encoding: [0xb1,0xff,0x52,0x04]
289 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
290 [0xb1,0xff,0x52,0x04]
291
292 # CHECK: vsli.8 q0, q3, #3 @ encoding: [0x8b,0xff,0x56,0x05]
293 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
294 [0x8b,0xff,0x56,0x05]
295
296 # CHECK: vsli.16 q0, q1, #12 @ encoding: [0x9c,0xff,0x52,0x05]
297 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
298 [0x9c,0xff,0x52,0x05]
299
300 # CHECK: vsli.32 q0, q1, #8 @ encoding: [0xa8,0xff,0x52,0x05]
301 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
302 [0xa8,0xff,0x52,0x05]
303
304 # CHECK: vqshl.s8 q0, q4, #6 @ encoding: [0x8e,0xef,0x58,0x07]
305 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
306 [0x8e,0xef,0x58,0x07]
307
308 # CHECK: vqshl.u8 q0, q6, #6 @ encoding: [0x8e,0xff,0x5c,0x07]
309 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
310 [0x8e,0xff,0x5c,0x07]
311
312 # CHECK: vqshl.s16 q1, q2, #5 @ encoding: [0x95,0xef,0x54,0x27]
313 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
314 [0x95,0xef,0x54,0x27]
315
316 # CHECK: vqshl.u16 q0, q5, #3 @ encoding: [0x93,0xff,0x5a,0x07]
317 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
318 [0x93,0xff,0x5a,0x07]
319
320 # CHECK: vqshl.s32 q1, q3, #29 @ encoding: [0xbd,0xef,0x56,0x27]
321 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
322 [0xbd,0xef,0x56,0x27]
323
324 # CHECK: vqshl.u32 q0, q2, #19 @ encoding: [0xb3,0xff,0x54,0x07]
325 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
326 [0xb3,0xff,0x54,0x07]
327
328 # CHECK: vqshlu.s8 q0, q1, #0 @ encoding: [0x88,0xff,0x52,0x06]
329 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
330 [0x88,0xff,0x52,0x06]
331
332 # CHECK: vqshlu.s16 q2, q1, #12 @ encoding: [0x9c,0xff,0x52,0x46]
333 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
334 [0x9c,0xff,0x52,0x46]
335
336 # CHECK: vqshlu.s32 q0, q4, #26 @ encoding: [0xba,0xff,0x58,0x06]
337 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
338 [0xba,0xff,0x58,0x06]
339
340 # CHECK: vrshr.s8 q1, q3, #7 @ encoding: [0x89,0xef,0x56,0x22]
341 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
342 [0x89,0xef,0x56,0x22]
343
344 # CHECK: vrshr.u8 q1, q3, #2 @ encoding: [0x8e,0xff,0x56,0x22]
345 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
346 [0x8e,0xff,0x56,0x22]
347
348 # CHECK: vrshr.s16 q0, q1, #10 @ encoding: [0x96,0xef,0x52,0x02]
349 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
350 [0x96,0xef,0x52,0x02]
351
352 # CHECK: vrshr.u16 q0, q5, #12 @ encoding: [0x94,0xff,0x5a,0x02]
353 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
354 [0x94,0xff,0x5a,0x02]
355
356 # CHECK: vrshr.s32 q0, q5, #23 @ encoding: [0xa9,0xef,0x5a,0x02]
357 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
358 [0xa9,0xef,0x5a,0x02]
359
360 # CHECK: vrshr.u32 q0, q1, #30 @ encoding: [0xa2,0xff,0x52,0x02]
361 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
362 [0xa2,0xff,0x52,0x02]
363
364 # CHECK: vshr.s8 q0, q7, #4 @ encoding: [0x8c,0xef,0x5e,0x00]
365 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
366 [0x8c,0xef,0x5e,0x00]
367
368 # CHECK: vshr.u8 q0, q2, #5 @ encoding: [0x8b,0xff,0x54,0x00]
369 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
370 [0x8b,0xff,0x54,0x00]
371
372 # CHECK: vshr.s16 q0, q3, #16 @ encoding: [0x90,0xef,0x56,0x00]
373 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
374 [0x90,0xef,0x56,0x00]
375
376 # CHECK: vshr.u16 q7, q6, #8 @ encoding: [0x98,0xff,0x5c,0xe0]
377 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
378 [0x98,0xff,0x5c,0xe0]
379
380 # CHECK: vshr.s32 q0, q6, #24 @ encoding: [0xa8,0xef,0x5c,0x00]
381 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
382 [0xa8,0xef,0x5c,0x00]
383
384 # CHECK: vshr.u32 q2, q5, #30 @ encoding: [0xa2,0xff,0x5a,0x40]
385 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
386 [0xa2,0xff,0x5a,0x40]
387
388 # CHECK: vshl.i8 q0, q6, #6 @ encoding: [0x8e,0xef,0x5c,0x05]
389 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
390 [0x8e,0xef,0x5c,0x05]
391
392 # CHECK: vshl.i16 q1, q0, #12 @ encoding: [0x9c,0xef,0x50,0x25]
393 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
394 [0x9c,0xef,0x50,0x25]
395
396 # CHECK: vshl.i32 q2, q2, #26 @ encoding: [0xba,0xef,0x54,0x45]
397 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
398 [0xba,0xef,0x54,0x45]
399
400 # CHECK: vpst @ encoding: [0x71,0xfe,0x4d,0x0f]
401 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
402 [0x71,0xfe,0x4d,0x0f]
403 [0xb4,0xee,0x42,0x1f]
404
405 # CHECK: vpstt @ encoding: [0x31,0xfe,0x4d,0x8f]
406 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
407 # CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
408 [0x31,0xfe,0x4d,0x8f]
409 [0xb4,0xee,0x42,0x1f]
410 [0xb8,0xfe,0x42,0x0f]
411
412 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
413 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
414 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
415 # CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
416 # CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
417 # CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
418 [0x71,0xfe,0x4d,0x8f]
419 [0xb4,0xee,0x42,0x1f]
420 [0xb8,0xfe,0x42,0x0f]
421
422 # CHECK: vpsttt @ encoding: [0x31,0xfe,0x4d,0x4f]
423 # CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
424 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
425 # CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
426 # CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
427 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
428 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
429 # CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
430 [0x31,0xfe,0x4d,0x4f]
431 [0xb4,0xee,0x42,0x1f]
432 [0xb8,0xfe,0x42,0x0f]
433 [0xb4,0xee,0x42,0x1f]
434
435 # CHECK: vpstte @ encoding: [0x31,0xfe,0x4d,0xcf]
436 # CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
437 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
438 # CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
439 # CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
440 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
441 # CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
442 # CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
443 [0x31,0xfe,0x4d,0xcf]
444 [0xb4,0xee,0x42,0x1f]
445 [0xb8,0xfe,0x42,0x0f]
446 [0xb4,0xee,0x42,0x1f]
447
448 # CHECK: vpstet @ encoding: [0x71,0xfe,0x4d,0xcf]
449 # CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
450 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
451 # CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
452 # CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
453 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
454 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
455 # CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
456 [0x71,0xfe,0x4d,0xcf]
457 [0xb4,0xee,0x42,0x1f]
458 [0xb8,0xfe,0x42,0x0f]
459 [0xb4,0xee,0x42,0x1f]
460
461 # CHECK: vpstee @ encoding: [0x71,0xfe,0x4d,0x4f]
462 # CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
463 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
464 # CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
465 # CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
466 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
467 # CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
468 # CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
469 [0x71,0xfe,0x4d,0x4f]
470 [0xb4,0xee,0x42,0x1f]
471 [0xb8,0xfe,0x42,0x0f]
472 [0xb4,0xee,0x42,0x1f]
473
474 # CHECK: vpstttt @ encoding: [0x31,0xfe,0x4d,0x2f]
475 # CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
476 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
477 # CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
478 # CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
479 # CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
480 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
481 # CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
482 # CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
483 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
484 [0x31,0xfe,0x4d,0x2f]
485 [0xb4,0xee,0x42,0x1f]
486 [0xb8,0xfe,0x42,0x0f]
487 [0xb4,0xee,0x42,0x1f]
488 [0xb8,0xfe,0x42,0x0f]
489
490 # CHECK: vpsttte @ encoding: [0x31,0xfe,0x4d,0x6f]
491 # CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
492 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
493 # CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
494 # CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
495 # CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
496 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
497 # CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
498 # CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
499 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
500 [0x31,0xfe,0x4d,0x6f]
501 [0xb4,0xee,0x42,0x1f]
502 [0xb8,0xfe,0x42,0x0f]
503 [0xb4,0xee,0x42,0x1f]
504 [0xb8,0xfe,0x42,0x0f]
505
506 # CHECK: vpsttet @ encoding: [0x31,0xfe,0x4d,0xef]
507 # CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
508 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
509 # CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
510 # CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
511 # CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
512 # CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
513 # CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
514 # CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
515 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
516 [0x31,0xfe,0x4d,0xef]
517 [0xb4,0xee,0x42,0x1f]
518 [0xb8,0xfe,0x42,0x0f]
519 [0xb4,0xee,0x42,0x1f]
520 [0xb8,0xfe,0x42,0x0f]
521
522 # CHECK: vpsttee @ encoding: [0x31,0xfe,0x4d,0xaf]
523 # CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
524 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
525 # CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
526 # CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
527 # CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
528 # CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
529 # CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
530 # CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
531 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
532 [0x31,0xfe,0x4d,0xaf]
533 [0xb4,0xee,0x42,0x1f]
534 [0xb8,0xfe,0x42,0x0f]
535 [0xb4,0xee,0x42,0x1f]
536 [0xb8,0xfe,0x42,0x0f]
537
538 # CHECK: vpstett @ encoding: [0x71,0xfe,0x4d,0xaf]
539 # CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
540 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
541 # CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
542 # CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
543 # CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
544 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
545 # CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
546 # CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
547 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
548 [0x71,0xfe,0x4d,0xaf]
549 [0xb4,0xee,0x42,0x1f]
550 [0xb8,0xfe,0x42,0x0f]
551 [0xb4,0xee,0x42,0x1f]
552 [0xb8,0xfe,0x42,0x0f]
553
554 # CHECK: vpstete @ encoding: [0x71,0xfe,0x4d,0xef]
555 # CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
556 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
557 # CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
558 # CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
559 # CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
560 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
561 # CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
562 # CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
563 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
564 [0x71,0xfe,0x4d,0xef]
565 [0xb4,0xee,0x42,0x1f]
566 [0xb8,0xfe,0x42,0x0f]
567 [0xb4,0xee,0x42,0x1f]
568 [0xb8,0xfe,0x42,0x0f]
569
570 # CHECK: vpsteee @ encoding: [0x71,0xfe,0x4d,0x2f]
571 # CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
572 # CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
573 # CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
574 # CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
575 # CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
576 # CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
577 # CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
578 # CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
579 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
580 [0x71,0xfe,0x4d,0x2f]
581 [0xb4,0xee,0x42,0x1f]
582 [0xb8,0xfe,0x42,0x0f]
583 [0xb4,0xee,0x42,0x1f]
584 [0xb8,0xfe,0x42,0x0f]