llvm.org GIT mirror llvm / 51458ed
Be more aggressive about following hints. RAGreedy::tryAssign will now evict interference from the preferred register even when another register is free. To support this, add the EvictionCost struct that counts how many hints are broken by an eviction. We don't want to break one hint just to satisfy another. Rename canEvict to shouldEvict, and add the first bit of eviction policy that doesn't depend on spill weights: Always make room in the preferred register as long as the evictees can be split and aren't already assigned to their preferred register. Also make the CSR avoidance more accurate. When looking for a cheaper register it is OK to use a new volatile register. Only CSR aliases that have never been used before should be avoided. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134735 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
11 changed file(s) with 178 addition(s) and 82 deletion(s). Raw diff Collapse all Expand all
223223 getRegAllocationHint(unsigned Reg) const {
224224 return RegAllocHints[Reg];
225225 }
226
227 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
228 /// standard simple hint (Type == 0) is not set.
229 unsigned getSimpleHint(unsigned Reg) const {
230 std::pair Hint = getRegAllocationHint(Reg);
231 return Hint.first ? 0 : Hint.second;
232 }
233
226234
227235 //===--------------------------------------------------------------------===//
228236 // Physical Register Use Info
243243 //
244244 // For comments on how to speed it up, see Query::findIntersection().
245245 unsigned LiveIntervalUnion::Query::
246 collectInterferingVRegs(unsigned MaxInterferingRegs, float MaxWeight) {
246 collectInterferingVRegs(unsigned MaxInterferingRegs) {
247247 InterferenceResult IR = firstInterference();
248248 LiveInterval::iterator VirtRegEnd = VirtReg->end();
249249 LiveInterval *RecentInterferingVReg = NULL;
286286 RecentInterferingVReg = IR.LiveUnionI.value();
287287 ++IR.LiveUnionI;
288288
289 // Stop collecting when the max weight is exceeded.
290 if (RecentInterferingVReg->weight >= MaxWeight)
291 return InterferingVRegs.size();
292
293289 continue;
294290 }
295291 // VirtRegI may have advanced far beyond LiveUnionI,
228228
229229 // Count the virtual registers in this union that interfere with this
230230 // query's live virtual register, up to maxInterferingRegs.
231 unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX,
232 float MaxWeight = HUGE_VALF);
231 unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX);
233232
234233 // Was this virtual register visited during collectInterferingVRegs?
235234 bool isSeenInterference(LiveInterval *VReg) const;
132132 }
133133 }
134134
135 /// Cost of evicting interference.
136 struct EvictionCost {
137 unsigned BrokenHints; ///< Total number of broken hints.
138 float MaxWeight; ///< Maximum spill weight evicted.
139
140 EvictionCost(unsigned B = 0) : BrokenHints(B), MaxWeight(0) {}
141
142 bool operator<(const EvictionCost &O) const {
143 if (BrokenHints != O.BrokenHints)
144 return BrokenHints < O.BrokenHints;
145 return MaxWeight < O.MaxWeight;
146 }
147 };
148
135149 // splitting state.
136150 std::auto_ptr SA;
137151 std::auto_ptr SE;
196210 void splitAroundRegion(LiveInterval&, GlobalSplitCandidate&,
197211 SmallVectorImpl&);
198212 void calcGapWeights(unsigned, SmallVectorImpl&);
199 bool canEvict(LiveInterval &A, LiveInterval &B);
200 bool canEvictInterference(LiveInterval&, unsigned, float&);
213 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
214 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
215 void evictInterference(LiveInterval&, unsigned,
216 SmallVectorImpl&);
201217
202218 unsigned tryAssign(LiveInterval&, AllocationOrder&,
203219 SmallVectorImpl&);
381397 if (!PhysReg || Order.isHint(PhysReg))
382398 return PhysReg;
383399
384 // PhysReg is available. Try to evict interference from a cheaper alternative.
400 // PhysReg is available, but there may be a better choice.
401
402 // If we missed a simple hint, try to cheaply evict interference from the
403 // preferred register.
404 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
405 if (Order.isHint(Hint)) {
406 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
407 EvictionCost MaxCost(1);
408 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
409 evictInterference(VirtReg, Hint, NewVRegs);
410 return Hint;
411 }
412 }
413
414 // Try to evict interference from a cheaper alternative.
385415 unsigned Cost = TRI->getCostPerUse(PhysReg);
386416
387417 // Most registers have 0 additional cost.
399429 // Interference eviction
400430 //===----------------------------------------------------------------------===//
401431
402 /// canEvict - determine if A can evict the assigned live range B. The eviction
403 /// policy defined by this function together with the allocation order defined
404 /// by enqueue() decides which registers ultimately end up being split and
405 /// spilled.
432 /// shouldEvict - determine if A should evict the assigned live range B. The
433 /// eviction policy defined by this function together with the allocation order
434 /// defined by enqueue() decides which registers ultimately end up being split
435 /// and spilled.
406436 ///
407437 /// Cascade numbers are used to prevent infinite loops if this function is a
408438 /// cyclic relation.
409 bool RAGreedy::canEvict(LiveInterval &A, LiveInterval &B) {
439 ///
440 /// @param A The live range to be assigned.
441 /// @param IsHint True when A is about to be assigned to its preferred
442 /// register.
443 /// @param B The live range to be evicted.
444 /// @param BreaksHint True when B is already assigned to its preferred register.
445 bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
446 LiveInterval &B, bool BreaksHint) {
447 bool CanSplit = getStage(B) <= RS_Second;
448
449 // Be fairly aggressive about following hints as long as the evictee can be
450 // split.
451 if (CanSplit && IsHint && !BreaksHint)
452 return true;
453
410454 return A.weight > B.weight;
411455 }
412456
413 /// canEvict - Return true if all interferences between VirtReg and PhysReg can
414 /// be evicted.
415 /// Return false if any interference is heavier than MaxWeight.
416 /// On return, set MaxWeight to the maximal spill weight of an interference.
457 /// canEvictInterference - Return true if all interferences between VirtReg and
458 /// PhysReg can be evicted. When OnlyCheap is set, don't do anything
459 ///
460 /// @param VirtReg Live range that is about to be assigned.
461 /// @param PhysReg Desired register for assignment.
462 /// @prarm IsHint True when PhysReg is VirtReg's preferred register.
463 /// @param MaxCost Only look for cheaper candidates and update with new cost
464 /// when returning true.
465 /// @returns True when interference can be evicted cheaper than MaxCost.
417466 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
418 float &MaxWeight) {
467 bool IsHint, EvictionCost &MaxCost) {
419468 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
420469 // involved in an eviction before. If a cascade number was assigned, deny
421470 // evicting anything with the same or a newer cascade number. This prevents
427476 if (!Cascade)
428477 Cascade = NextCascade;
429478
430 float Weight = 0;
479 EvictionCost Cost;
431480 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
432481 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
433482 // If there is 10 or more interferences, chances are one is heavier.
434 if (Q.collectInterferingVRegs(10, MaxWeight) >= 10)
483 if (Q.collectInterferingVRegs(10) >= 10)
435484 return false;
436485
437486 // Check if any interfering live range is heavier than MaxWeight.
439488 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
440489 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
441490 return false;
442 if (Cascade <= ExtraRegInfo[Intf->reg].Cascade)
491 // Never evict spill products. They cannot split or spill.
492 if (getStage(*Intf) == RS_Spill)
443493 return false;
444 if (Intf->weight >= MaxWeight)
494 // Once a live range becomes small enough, it is urgent that we find a
495 // register for it. This is indicated by an infinite spill weight. These
496 // urgent live ranges get to evict almost anything.
497 bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable();
498 // Only evict older cascades or live ranges without a cascade.
499 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
500 if (Cascade <= IntfCascade) {
501 if (!Urgent)
502 return false;
503 // We permit breaking cascades for urgent evictions. It should be the
504 // last resort, though, so make it really expensive.
505 Cost.BrokenHints += 10;
506 }
507 // Would this break a satisfied hint?
508 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
509 // Update eviction cost.
510 Cost.BrokenHints += BreaksHint;
511 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
512 // Abort if this would be too expensive.
513 if (!(Cost < MaxCost))
445514 return false;
446 if (!canEvict(VirtReg, *Intf))
515 // Finally, apply the eviction policy for non-urgent evictions.
516 if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
447517 return false;
448 Weight = std::max(Weight, Intf->weight);
449 }
450 }
451 MaxWeight = Weight;
518 }
519 }
520 MaxCost = Cost;
452521 return true;
522 }
523
524 /// evictInterference - Evict any interferring registers that prevent VirtReg
525 /// from being assigned to Physreg. This assumes that canEvictInterference
526 /// returned true.
527 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
528 SmallVectorImpl &NewVRegs) {
529 // Make sure that VirtReg has a cascade number, and assign that cascade
530 // number to every evicted register. These live ranges than then only be
531 // evicted by a newer cascade, preventing infinite loops.
532 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
533 if (!Cascade)
534 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
535
536 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
537 << " interference: Cascade " << Cascade << '\n');
538 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
539 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
540 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
541 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
542 LiveInterval *Intf = Q.interferingVRegs()[i];
543 unassign(*Intf, VRM->getPhys(Intf->reg));
544 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
545 VirtReg.isSpillable() < Intf->isSpillable()) &&
546 "Cannot decrease cascade number, illegal eviction");
547 ExtraRegInfo[Intf->reg].Cascade = Cascade;
548 ++NumEvicted;
549 NewVRegs.push_back(Intf);
550 }
551 }
453552 }
454553
455554 /// tryEvict - Try to evict all interferences for a physreg.
462561 unsigned CostPerUseLimit) {
463562 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
464563
465 // Keep track of the lightest single interference seen so far.
466 float BestWeight = HUGE_VALF;
564 // Keep track of the cheapest interference seen so far.
565 EvictionCost BestCost(~0u);
467566 unsigned BestPhys = 0;
567
568 // When we are just looking for a reduced cost per use, don't break any
569 // hints, and only evict smaller spill weights.
570 if (CostPerUseLimit < ~0u) {
571 BestCost.BrokenHints = 0;
572 BestCost.MaxWeight = VirtReg.weight;
573 }
468574
469575 Order.rewind();
470576 while (unsigned PhysReg = Order.next()) {
471577 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
472578 continue;
473 // The first use of a register in a function has cost 1.
474 if (CostPerUseLimit == 1 && !MRI->isPhysRegUsed(PhysReg))
475 continue;
476
477 float Weight = BestWeight;
478 if (!canEvictInterference(VirtReg, PhysReg, Weight))
479 continue;
480
481 // This is an eviction candidate.
482 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " interference = "
483 << Weight << '\n');
484 if (BestPhys && Weight >= BestWeight)
579 // The first use of a callee-saved register in a function has cost 1.
580 // Don't start using a CSR when the CostPerUseLimit is low.
581 if (CostPerUseLimit == 1)
582 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
583 if (!MRI->isPhysRegUsed(CSR)) {
584 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
585 << PrintReg(CSR, TRI) << '\n');
586 continue;
587 }
588
589 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
485590 continue;
486591
487592 // Best so far.
488593 BestPhys = PhysReg;
489 BestWeight = Weight;
594
490595 // Stop if the hint can be used.
491596 if (Order.isHint(PhysReg))
492597 break;
495600 if (!BestPhys)
496601 return 0;
497602
498 // We will evict interference. Make sure that VirtReg has a cascade number,
499 // and assign that cascade number to every evicted register. These live
500 // ranges than then only be evicted by a newer cascade, preventing infinite
501 // loops.
502 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
503 if (!Cascade)
504 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
505
506 DEBUG(dbgs() << "evicting " << PrintReg(BestPhys, TRI)
507 << " interference: Cascade " << Cascade << '\n');
508 for (const unsigned *AliasI = TRI->getOverlaps(BestPhys); *AliasI; ++AliasI) {
509 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
510 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
511 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
512 LiveInterval *Intf = Q.interferingVRegs()[i];
513 unassign(*Intf, VRM->getPhys(Intf->reg));
514 assert(ExtraRegInfo[Intf->reg].Cascade < Cascade &&
515 "Cannot decrease cascade number, illegal eviction");
516 ExtraRegInfo[Intf->reg].Cascade = Cascade;
517 ++NumEvicted;
518 NewVRegs.push_back(Intf);
519 }
520 }
603 evictInterference(VirtReg, BestPhys, NewVRegs);
521604 return BestPhys;
522605 }
523606
15511634
15521635 // If we couldn't allocate a register from spilling, there is probably some
15531636 // invalid inline assembly. The base class wil report it.
1554 if (Stage >= RS_Spill)
1637 if (Stage >= RS_Spill || !VirtReg.isSpillable())
15551638 return ~0u;
15561639
15571640 // Try splitting VirtReg or interferences.
207207 /// @brief returns the register allocation preference.
208208 unsigned getRegAllocPref(unsigned virtReg);
209209
210 /// @brief returns true if VirtReg is assigned to its preferred physreg.
211 bool hasPreferredPhys(unsigned VirtReg) {
212 return getPhys(VirtReg) == getRegAllocPref(VirtReg);
213 }
214
210215 /// @brief records virtReg is a split live interval from SReg.
211216 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
212217 Virt2SplitMap[virtReg] = SReg;
33 ; register pressure and therefore spilling. There is more room for improvement
44 ; here.
55
6 ; CHECK: sub sp, #{{32|24}}
6 ; CHECK: sub sp, #{{32|28|24}}
77
8 ; CHECK: ldr r{{.*}}, [sp, #4]
9 ; CHECK-NEXT: ldr r{{.*}}, [sp, #16]
10 ; CHECK-NEXT: ldr r{{.*}}, [sp, #12]
11 ; CHECK-NEXT: adds
8 ; CHECK: %for.inc
9 ; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
10 ; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
11 ; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
12 ; CHECK: add
1213
1314 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
1415 target triple = "thumbv7-apple-macosx10.7.0"
2121 define void @t2() nounwind ssp {
2222 entry:
2323 ; CHECK: t2:
24 ; CHECK: movl %eax, %ecx
25 ; CHECK: %ecx = foo (%ecx, %eax)
24 ; CHECK: movl
25 ; CHECK: [[D2:%e.x]] = foo
26 ; CHECK: ([[D2]],
27 ; CHECK-NOT: [[D2]]
28 ; CHECK: )
2629 %b = alloca i32 ; [#uses=2]
2730 %a = alloca i32 ; [#uses=1]
2831 %"alloca point" = bitcast i32 0 to i32 ; [#uses=0]
3939 %div = sdiv i16 %x, 33 ; [#uses=1]
4040 ret i16 %div
4141 ; CHECK: test4:
42 ; CHECK: imull $1986, %eax, %eax
42 ; CHECK: imull $1986, %eax, %
4343 }
4444
4545 define i32 @test5(i32 %A) nounwind {
44 ; stick with indexing here.
55
66 ; CHECK: movaps (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]]
7 ; CHECK: movaps
8 ; CHECK: [[X3]], (%{{rdi|rcx}},%rax,4)
7 ; CHECK: cvtdq2ps
8 ; CHECK: orps {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]]
9 ; CHECK: movaps [[X4]], (%{{rdi|rcx}},%rax,4)
910 ; CHECK: addq $4, %rax
1011 ; CHECK: cmpl %eax, (%{{rdx|r8}})
1112 ; CHECK-NEXT: jg
88 %0 = ptrtoint float* %A to i32 ; [#uses=1]
99 %1 = and i32 %0, 3 ; [#uses=1]
1010 %2 = xor i32 %IA, 1 ; [#uses=1]
11 ; CHECK: orl %ecx, %edx
11 ; CHECK: orl %e
1212 ; CHECK-NEXT: je
1313 %3 = or i32 %2, %1 ; [#uses=1]
1414 %4 = icmp eq i32 %3, 0 ; [#uses=1]
168168 ; X64: t10:
169169 ; X64: pextrw $4, [[X0:%xmm[0-9]+]], %eax
170170 ; X64: unpcklpd [[X1:%xmm[0-9]+]]
171 ; X64: pshuflw $8, [[X1]], [[X1]]
172 ; X64: pinsrw $2, %eax, [[X1]]
171 ; X64: pshuflw $8, [[X1]], [[X2:%xmm[0-9]+]]
172 ; X64: pinsrw $2, %eax, [[X2]]
173173 ; X64: pextrw $6, [[X0]], %eax
174 ; X64: pinsrw $3, %eax, [[X1]]
174 ; X64: pinsrw $3, %eax, [[X2]]
175175 }
176176
177177