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[WebAssembly] v4f32.abs and v2f64.abs Summary: implement lowering of @llvm.fabs for vector types. Reviewers: aheejin, dschuff Subscribers: git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342513 91177308-0d34-0410-b5e6-96231b3b80d8 Thomas Lively 1 year, 9 months ago
3 changed file(s) with 39 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
205205 defm "" : SIMDCondition;
206206 defm "" : SIMDCondition
207207 !add(baseInst, 1)>;
208 }
209 multiclass SIMDAbs simdop> {
210 defm ABS_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
211 [(set (vec_t V128:$dst), (vec_t (fabs V128:$vec)))],
212 vec#".abs\t$dst, $vec", vec#".abs", simdop>;
208213 }
209214
210215 let Defs = [ARGUMENTS] in {
361366 defm GE_S : SIMDConditionInt<"ge_s", SETGE, 106, 2>;
362367 defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 107, 2>;
363368 defm GE : SIMDConditionFP<"ge", SETOGE, 112>;
369
370 defm "" : SIMDAbs;
371 defm "" : SIMDAbs;
364372
365373 } // Defs = [ARGUMENTS]
366374
666666 ret <4 x float> %a
667667 }
668668
669 ; CHECK-LABEL: abs_v4f32:
670 ; NO-SIMD128-NOT: f32x4
671 ; SIMD128-NEXT: .param v128{{$}}
672 ; SIMD128-NEXT: .result v128{{$}}
673 ; SIMD128-NEXT: f32x4.abs $push0=, $0{{$}}
674 ; SIMD128-NEXT: return $pop0{{$}}
675 declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone
676 define <4 x float> @abs_v4f32(<4 x float> %x) {
677 %a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
678 ret <4 x float> %a
679 }
680
669681 ; CHECK-LABEL: add_v4f32:
670682 ; NO-SIMD128-NOT: f32x4
671683 ; SIMD128-NEXT: .param v128, v128{{$}}
724736 ret <2 x double> %a
725737 }
726738
739 ; CHECK-LABEL: abs_v2f64:
740 ; NO-SIMD128-NOT: f64x2
741 ; SIMD128-NEXT: .param v128{{$}}
742 ; SIMD128-NEXT: .result v128{{$}}
743 ; SIMD128-NEXT: f64x2.abs $push0=, $0{{$}}
744 ; SIMD128-NEXT: return $pop0{{$}}
745 declare <2 x double> @llvm.fabs.v2f64(<2 x double>) nounwind readnone
746 define <2 x double> @abs_v2f64(<2 x double> %x) {
747 %a = call <2 x double> @llvm.fabs.v2f64(<2 x double> %x)
748 ret <2 x double> %a
749 }
750
751
727752 ; CHECK-LABEL: add_v2f64:
728753 ; NO-SIMD128-NOT: f64x2
729754 ; SIMD128-VM-NOT: f62x2
324324 # CHECK: f64x2.neg # encoding: [0xfd,0x73]
325325 f64x2.neg
326326
327 # CHECK: f32x4.abs # encoding: [0xfd,0x74]
328 f32x4.abs
329
330 # CHECK: f64x2.abs # encoding: [0xfd,0x75]
331 f64x2.abs
332
327333 # CHECK: f32x4.add # encoding: [0xfd,0x7a]
328334 f32x4.add
329335