llvm.org GIT mirror llvm / 50bf433
[X86] Teach constant hoisting that ANDs with 64-bit immediates in the range 0x80000000-0xffffffff can be handled cheaply and don't need to be hoisted. Most importantly, this keeps constant hoisting from preventing instruction selections ability to turn an AND with 0xffffffff into a move into a 32-bit subregister. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249370 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 4 years ago
2 changed file(s) with 26 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
10771077 case Instruction::Store:
10781078 ImmIdx = 0;
10791079 break;
1080 case Instruction::And:
1081 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes
1082 // by using a 32-bit operation with implicit zero extension. Detect such
1083 // immediates here as the normal path expects bit 31 to be sign extended.
1084 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue()))
1085 return TTI::TCC_Free;
1086 // Fallthrough
10801087 case Instruction::Add:
10811088 case Instruction::Sub:
10821089 case Instruction::Mul:
10841091 case Instruction::SDiv:
10851092 case Instruction::URem:
10861093 case Instruction::SRem:
1087 case Instruction::And:
10881094 case Instruction::Or:
10891095 case Instruction::Xor:
10901096 case Instruction::ICmp:
0 ; RUN: llc < %s -O3 -march=x86-64 |FileCheck %s
1 define i64 @foo(i1 %z, i64 %data1, i64 %data2)
2 {
3 ; If constant 4294967294 is hoisted to a variable, then we won't be able to use
4 ; the implicit zero extension of 32-bit operations to handle the AND.
5 entry:
6 %val1 = and i64 %data1, 4294967294
7 br i1 %z, label %End, label %L_val2
8
9 ; CHECK: andl $-2, {{.*}}
10 ; CHECK: andl $-2, {{.*}}
11 L_val2:
12 %val2 = and i64 %data2, 4294967294
13 br label %End
14
15 End:
16 %p1 = phi i64 [%val1,%entry], [%val2,%L_val2]
17 ret i64 %p1
18 }