llvm.org GIT mirror llvm / 508bd63
[MC] Require an MCContext when constructing an MCDisassembler. This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206241 91177308-0d34-0410-b5e6-96231b3b80d8 Lang Hames 6 years ago
17 changed file(s) with 121 addition(s) and 82 deletion(s). Raw diff Collapse all Expand all
5555 };
5656
5757 /// Constructor - Performs initial setup for the disassembler.
58 MCDisassembler(const MCSubtargetInfo &STI)
59 : STI(STI), Symbolizer(), CommentStream(nullptr) {}
58 MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
59 : Ctx(Ctx), STI(STI), Symbolizer(), CommentStream(nullptr) {}
6060
6161 virtual ~MCDisassembler();
6262
8282 uint64_t address,
8383 raw_ostream &vStream,
8484 raw_ostream &cStream) const = 0;
85 private:
86 MCContext &Ctx;
8587
8688 protected:
8789 // Subtarget information, for instruction decoding predicates if required.
101103 /// This takes ownership of \p Symzer, and deletes the previously set one.
102104 void setSymbolizer(std::unique_ptr Symzer);
103105
106 MCContext& getContext() const { return Ctx; }
107
104108 const MCSubtargetInfo& getSubtargetInfo() const { return STI; }
105109
106110 // Marked mutable because we cache it inside the disassembler, rather than
107107 MCAsmParser &P,
108108 const MCInstrInfo &MII);
109109 typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T,
110 const MCSubtargetInfo &STI);
110 const MCSubtargetInfo &STI,
111 MCContext &Ctx);
111112 typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
112113 unsigned SyntaxVariant,
113114 const MCAsmInfo &MAI,
376377 return AsmPrinterCtorFn(TM, Streamer);
377378 }
378379
379 MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI) const {
380 MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI,
381 MCContext &Ctx) const {
380382 if (!MCDisassemblerCtorFn)
381383 return nullptr;
382 return MCDisassemblerCtorFn(*this, STI);
384 return MCDisassemblerCtorFn(*this, STI, Ctx);
383385 }
384386
385387 MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant,
6969 return 0;
7070
7171 // Set up disassembler.
72 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI);
72 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI, *Ctx);
7373 if (!DisAsm)
7474 return 0;
7575
3737 namespace {
3838 /// AArch64 disassembler for all AArch64 platforms.
3939 class AArch64Disassembler : public MCDisassembler {
40 OwningPtr RegInfo;
4140 public:
4241 /// Initializes the disassembler.
4342 ///
44 AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
45 : MCDisassembler(STI), RegInfo(Info) {
43 AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
44 : MCDisassembler(STI, Ctx) {
4645 }
4746
4847 ~AArch64Disassembler() {}
5453 uint64_t address,
5554 raw_ostream &vStream,
5655 raw_ostream &cStream) const;
57
58 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
5956 };
6057
6158 }
296293
297294 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
298295 const AArch64Disassembler *Dis = static_cast(D);
299 return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
296 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
297 return RegInfo->getRegClass(RC).getRegister(RegNo);
300298 }
301299
302300 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
990988 }
991989
992990 static MCDisassembler *createAArch64Disassembler(const Target &T,
993 const MCSubtargetInfo &STI) {
994 return new AArch64Disassembler(STI, T.createMCRegInfo(""));
991 const MCSubtargetInfo &STI,
992 MCContext &Ctx) {
993 return new AArch64Disassembler(STI, Ctx);
995994 }
996995
997996 extern "C" void LLVMInitializeAArch64Disassembler() {
8989 public:
9090 /// Constructor - Initializes the disassembler.
9191 ///
92 ARMDisassembler(const MCSubtargetInfo &STI) :
93 MCDisassembler(STI) {
92 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
93 MCDisassembler(STI, Ctx) {
9494 }
9595
9696 ~ARMDisassembler() {
108108 public:
109109 /// Constructor - Initializes the disassembler.
110110 ///
111 ThumbDisassembler(const MCSubtargetInfo &STI) :
112 MCDisassembler(STI) {
111 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
112 MCDisassembler(STI, Ctx) {
113113 }
114114
115115 ~ThumbDisassembler() {
399399 uint64_t Address, const void *Decoder);
400400 #include "ARMGenDisassemblerTables.inc"
401401
402 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
403 return new ARMDisassembler(STI);
404 }
405
406 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
407 return new ThumbDisassembler(STI);
402 static MCDisassembler *createARMDisassembler(const Target &T,
403 const MCSubtargetInfo &STI,
404 MCContext &Ctx) {
405 return new ARMDisassembler(STI, Ctx);
406 }
407
408 static MCDisassembler *createThumbDisassembler(const Target &T,
409 const MCSubtargetInfo &STI,
410 MCContext &Ctx) {
411 return new ThumbDisassembler(STI, Ctx);
408412 }
409413
410414 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
183183 #define Fail llvm::MCDisassembler::Fail
184184
185185 static MCDisassembler *createARM64Disassembler(const Target &T,
186 const MCSubtargetInfo &STI) {
187 return new ARM64Disassembler(STI);
186 const MCSubtargetInfo &STI,
187 MCContext &Ctx) {
188 return new ARM64Disassembler(STI, Ctx);
188189 }
189190
190191 DecodeStatus ARM64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
2222
2323 class ARM64Disassembler : public MCDisassembler {
2424 public:
25 ARM64Disassembler(const MCSubtargetInfo &STI) : MCDisassembler(STI) {}
25 ARM64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
26 : MCDisassembler(STI, Ctx) {}
2627
2728 ~ARM64Disassembler() {}
2829
1313 #include "Mips.h"
1414 #include "MipsRegisterInfo.h"
1515 #include "MipsSubtarget.h"
16 #include "llvm/MC/MCContext.h"
1617 #include "llvm/MC/MCDisassembler.h"
1718 #include "llvm/MC/MCFixedLenDisassembler.h"
1819 #include "llvm/MC/MCInst.h"
3233 public:
3334 /// Constructor - Initializes the disassembler.
3435 ///
35 MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
36 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
3637 bool bigEndian) :
37 MCDisassembler(STI), RegInfo(Info),
38 MCDisassembler(STI, Ctx),
3839 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
3940
4041 virtual ~MipsDisassemblerBase() {}
4142
42 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
43
4443 bool isN64() const { return IsN64; }
4544
4645 private:
47 OwningPtr RegInfo;
4846 bool IsN64;
4947 protected:
5048 bool isBigEndian;
5654 public:
5755 /// Constructor - Initializes the disassembler.
5856 ///
59 MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
57 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
6058 bool bigEndian) :
61 MipsDisassemblerBase(STI, Info, bigEndian) {
59 MipsDisassemblerBase(STI, Ctx, bigEndian) {
6260 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
6361 }
6462
7775 public:
7876 /// Constructor - Initializes the disassembler.
7977 ///
80 Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
78 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
8179 bool bigEndian) :
82 MipsDisassemblerBase(STI, Info, bigEndian) {}
80 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
8381
8482 /// getInstruction - See MCDisassembler.
8583 virtual DecodeStatus getInstruction(MCInst &instr,
274272
275273 static MCDisassembler *createMipsDisassembler(
276274 const Target &T,
277 const MCSubtargetInfo &STI) {
278 return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
275 const MCSubtargetInfo &STI,
276 MCContext &Ctx) {
277 return new MipsDisassembler(STI, Ctx, true);
279278 }
280279
281280 static MCDisassembler *createMipselDisassembler(
282281 const Target &T,
283 const MCSubtargetInfo &STI) {
284 return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
282 const MCSubtargetInfo &STI,
283 MCContext &Ctx) {
284 return new MipsDisassembler(STI, Ctx, false);
285285 }
286286
287287 static MCDisassembler *createMips64Disassembler(
288288 const Target &T,
289 const MCSubtargetInfo &STI) {
290 return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
289 const MCSubtargetInfo &STI,
290 MCContext &Ctx) {
291 return new Mips64Disassembler(STI, Ctx, true);
291292 }
292293
293294 static MCDisassembler *createMips64elDisassembler(
294295 const Target &T,
295 const MCSubtargetInfo &STI) {
296 return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
296 const MCSubtargetInfo &STI,
297 MCContext &Ctx) {
298 return new Mips64Disassembler(STI, Ctx, false);
297299 }
298300
299301 extern "C" void LLVMInitializeMipsDisassembler() {
470472
471473 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
472474 const MipsDisassemblerBase *Dis = static_cast(D);
473 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
475 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
476 return *(RegInfo->getRegClass(RC).begin() + RegNo);
474477 }
475478
476479 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
2121 namespace {
2222 class PPCDisassembler : public MCDisassembler {
2323 public:
24 PPCDisassembler(const MCSubtargetInfo &STI)
25 : MCDisassembler(STI) {}
24 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
25 : MCDisassembler(STI, Ctx) {}
2626 virtual ~PPCDisassembler() {}
2727
2828 // Override MCDisassembler.
3636 } // end anonymous namespace
3737
3838 static MCDisassembler *createPPCDisassembler(const Target &T,
39 const MCSubtargetInfo &STI) {
40 return new PPCDisassembler(STI);
39 const MCSubtargetInfo &STI,
40 MCContext &Ctx) {
41 return new PPCDisassembler(STI, Ctx);
4142 }
4243
4344 extern "C" void LLVMInitializePowerPCDisassembler() {
3131 public:
3232 /// Constructor - Initializes the disassembler.
3333 ///
34 SparcDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
35 MCDisassembler(STI), RegInfo(Info)
34 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
35 MCDisassembler(STI, Ctx)
3636 {}
3737 virtual ~SparcDisassembler() {}
38
39 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
4038
4139 /// getInstruction - See MCDisassembler.
4240 virtual DecodeStatus getInstruction(MCInst &instr,
4543 uint64_t address,
4644 raw_ostream &vStream,
4745 raw_ostream &cStream) const;
48 private:
49 OwningPtr RegInfo;
5046 };
5147
5248 }
5753
5854 static MCDisassembler *createSparcDisassembler(
5955 const Target &T,
60 const MCSubtargetInfo &STI) {
61 return new SparcDisassembler(STI, T.createMCRegInfo(""));
56 const MCSubtargetInfo &STI,
57 MCContext &Ctx) {
58 return new SparcDisassembler(STI, Ctx);
6259 }
6360
6461
2121 namespace {
2222 class SystemZDisassembler : public MCDisassembler {
2323 public:
24 SystemZDisassembler(const MCSubtargetInfo &STI)
25 : MCDisassembler(STI) {}
24 SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
25 : MCDisassembler(STI, Ctx) {}
2626 virtual ~SystemZDisassembler() {}
2727
2828 // Override MCDisassembler.
3434 } // end anonymous namespace
3535
3636 static MCDisassembler *createSystemZDisassembler(const Target &T,
37 const MCSubtargetInfo &STI) {
38 return new SystemZDisassembler(STI);
37 const MCSubtargetInfo &STI,
38 MCContext &Ctx) {
39 return new SystemZDisassembler(STI, Ctx);
3940 }
4041
4142 extern "C" void LLVMInitializeSystemZDisassembler() {
7575
7676 X86GenericDisassembler::X86GenericDisassembler(
7777 const MCSubtargetInfo &STI,
78 MCContext &Ctx,
7879 std::unique_ptr MII)
79 : MCDisassembler(STI), MII(std::move(MII)) {
80 : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
8081 switch (STI.getFeatureBits() &
8182 (X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) {
8283 case X86::Mode16Bit:
799800 }
800801
801802 static MCDisassembler *createX86Disassembler(const Target &T,
802 const MCSubtargetInfo &STI) {
803 const MCSubtargetInfo &STI,
804 MCContext &Ctx) {
803805 std::unique_ptr MII(T.createMCInstrInfo());
804 return new X86Disassembler::X86GenericDisassembler(STI, std::move(MII));
806 return new X86Disassembler::X86GenericDisassembler(STI, Ctx, std::move(MII));
805807 }
806808
807809 extern "C" void LLVMInitializeX86Disassembler() {
104104 public:
105105 /// Constructor - Initializes the disassembler.
106106 ///
107 X86GenericDisassembler(const MCSubtargetInfo &STI,
107 X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
108108 std::unique_ptr MII);
109109 public:
110110
1313
1414 #include "XCore.h"
1515 #include "XCoreRegisterInfo.h"
16 #include "llvm/MC/MCContext.h"
1617 #include "llvm/MC/MCDisassembler.h"
1718 #include "llvm/MC/MCFixedLenDisassembler.h"
1819 #include "llvm/MC/MCInst.h"
2829
2930 /// \brief A disassembler class for XCore.
3031 class XCoreDisassembler : public MCDisassembler {
31 OwningPtr RegInfo;
3232 public:
33 XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
34 MCDisassembler(STI), RegInfo(Info) {}
33 XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
34 MCDisassembler(STI, Ctx) {}
3535
3636 /// \brief See MCDisassembler.
3737 virtual DecodeStatus getInstruction(MCInst &instr,
4141 raw_ostream &vStream,
4242 raw_ostream &cStream) const;
4343
44 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
4544 };
4645 }
4746
8079
8180 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
8281 const XCoreDisassembler *Dis = static_cast(D);
83 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
82 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
83 return *(RegInfo->getRegClass(RC).begin() + RegNo);
8484 }
8585
8686 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
787787 }
788788
789789 static MCDisassembler *createXCoreDisassembler(const Target &T,
790 const MCSubtargetInfo &STI) {
791 return new XCoreDisassembler(STI, T.createMCRegInfo(""));
790 const MCSubtargetInfo &STI,
791 MCContext &Ctx) {
792 return new XCoreDisassembler(STI, Ctx);
792793 }
793794
794795 extern "C" void LLVMInitializeXCoreDisassembler() {
1313
1414 #include "Disassembler.h"
1515 #include "llvm/ADT/Triple.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
1618 #include "llvm/MC/MCDisassembler.h"
1719 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCRegisterInfo.h"
1821 #include "llvm/MC/MCStreamer.h"
1922 #include "llvm/MC/MCSubtargetInfo.h"
2023 #include "llvm/Support/MemoryBuffer.h"
157160 MemoryBuffer &Buffer,
158161 SourceMgr &SM,
159162 raw_ostream &Out) {
160 std::unique_ptr DisAsm(T.createMCDisassembler(STI));
163
164 std::unique_ptr MRI(T.createMCRegInfo(Triple));
165 if (!MRI) {
166 errs() << "error: no register info for target " << Triple << "\n";
167 return -1;
168 }
169
170 std::unique_ptr MAI(T.createMCAsmInfo(*MRI, Triple));
171 if (!MAI) {
172 errs() << "error: no assembly info for target " << Triple << "\n";
173 return -1;
174 }
175
176 // Set up the MCContext for creating symbols and MCExpr's.
177 MCContext Ctx(MAI.get(), MRI.get(), 0);
178
179 std::unique_ptr DisAsm(
180 T.createMCDisassembler(STI, Ctx));
161181 if (!DisAsm) {
162182 errs() << "error: no disassembler for target " << Triple << "\n";
163183 return -1;
1616 #include "llvm/ADT/Triple.h"
1717 #include "llvm/DebugInfo/DIContext.h"
1818 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCContext.h"
1920 #include "llvm/MC/MCDisassembler.h"
2021 #include "llvm/MC/MCInst.h"
2122 #include "llvm/MC/MCInstPrinter.h"
224225 TheTarget->createMCAsmInfo(*MRI, TripleName));
225226 std::unique_ptr STI(
226227 TheTarget->createMCSubtargetInfo(TripleName, "", ""));
228 MCContext Ctx(AsmInfo.get(), MRI.get(), 0);
227229 std::unique_ptr DisAsm(
228 TheTarget->createMCDisassembler(*STI));
230 TheTarget->createMCDisassembler(*STI, Ctx));
229231 int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
230232 std::unique_ptr IP(TheTarget->createMCInstPrinter(
231233 AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI, *STI));
308308 return;
309309 }
310310
311 std::unique_ptr<MCDisassembler> DisAsm(TheTarget->createMCDisassembler(*STI));
311 std::unique_ptr<const MCObjectFileInfo> MOFI(new MCObjectFileInfo);
312 MCContext Ctx(AsmInfo.get(), MRI.get(), MOFI.get());
313
314 std::unique_ptr DisAsm(
315 TheTarget->createMCDisassembler(*STI, Ctx));
316
312317 if (!DisAsm) {
313318 errs() << "error: no disassembler for target " << TripleName << "\n";
314319 return;
315320 }
316321
317 std::unique_ptr MOFI;
318 std::unique_ptr Ctx;
319322
320323 if (Symbolize) {
321 MOFI.reset(new MCObjectFileInfo);
322 Ctx.reset(new MCContext(AsmInfo.get(), MRI.get(), MOFI.get()));
323324 std::unique_ptr RelInfo(
324 TheTarget->createMCRelocationInfo(TripleName, *Ctx.get()));
325 TheTarget->createMCRelocationInfo(TripleName, Ctx));
325326 if (RelInfo) {
326327 std::unique_ptr Symzer(
327 MCObjectSymbolizer::createObjectSymbolizer(*Ctx.get(),
328 std::move(RelInfo), Obj));
328 MCObjectSymbolizer::createObjectSymbolizer(Ctx, std::move(RelInfo),
329 Obj));
329330 if (Symzer)
330331 DisAsm->setSymbolizer(std::move(Symzer));
331332 }