llvm.org GIT mirror llvm / 5047d76
Pseudo CMOV instructions don't clobber EFLAGS. The explanation about a 0 argument being materialized as xor is no longer valid. Rematerialization will check if EFLAGS is live before clobbering it. The code produced by X86TargetLowering::EmitLoweredSelect does not clobber EFLAGS. This causes one less testb instruction to be generated in the cmov.ll test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139057 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
3 changed file(s) with 9 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
348348 //===----------------------------------------------------------------------===//
349349 // Conditional Move Pseudo Instructions
350350
351 let Constraints = "$src1 = $dst" in {
352
353 // Conditional moves
354 let Uses = [EFLAGS] in {
355
356351 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
357352 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
358353 // however that requires promoting the operands, and can induce additional
359 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
360 // clobber EFLAGS, because if one of the operands is zero, the expansion
361 // could involve an xor.
362 let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
354 // i8 register pressure.
355 let usesCustomInserter = 1, Uses = [EFLAGS] in {
363356 def CMOV_GR8 : I<0, Pseudo,
364357 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
365358 "#CMOV_GR8 PSEUDO!",
399392 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
400393 EFLAGS))]>;
401394 } // Predicates = [NoCMov]
402 } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
403 } // Uses = [EFLAGS]
404
405 } // Constraints = "$src1 = $dst" in
395 } // UsesCustomInserter = 1, Uses = [EFLAGS]
406396
407397
408398 //===----------------------------------------------------------------------===//
8989 ; CHECK: test4:
9090 ; CHECK: g_100
9191 ; CHECK: testb
92 ; CHECK: testb %al, %al
93 ; CHECK-NEXT: setne %al
92 ; CHECK-NOT: xor
93 ; CHECK: setne
9494 ; CHECK-NEXT: testb
9595
9696 func_4.exit.i: ; preds = %bb.i.i.i, %entry
4646 }
4747
4848 ; CHECK: test1:
49 ; CHECK: movl %{{.*}}, (%rdi,%rcx,4)
50 ; CHECK: movl %{{.*}}, 8(%rdi,%rcx,4)
51 ; CHECK: movl %{{.*}}, 4(%rdi,%rcx,4)
52 ; CHECK: movl %{{.*}}, 12(%rdi,%rcx,4)
49 ; CHECK: movl %{{.*}}, (%[[RDI:...]],%[[RCX:...]],4)
50 ; CHECK: movl %{{.*}}, 8(%[[RDI]],%[[RCX]],4)
51 ; CHECK: movl %{{.*}}, 4(%[[RDI]],%[[RCX]],4)
52 ; CHECK: movl %{{.*}}, 12(%[[RDI]],%[[RCX]],4)
5353
5454 define void @test1(i32* nocapture %array, i32 %r0, i8 signext %k, i8 signext %i0) nounwind {
5555 bb.nph: