llvm.org GIT mirror llvm / 4ffff9e
Added the llvm.readport and llvm.writeport intrinsics for x86. These do I/O port instructions on x86. The specific code sequence is tailored to the parameters and return value of the intrinsic call. Added the ability for implicit defintions to be printed in the Instruction Printer. Added the ability for RawFrm instruction to print implict uses and defintions with correct comma output. This required adjustment to some methods so that a leading comma would or would not be printed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12782 91177308-0d34-0410-b5e6-96231b3b80d8 John Criswell 16 years ago
7 changed file(s) with 330 addition(s) and 49 deletion(s). Raw diff Collapse all Expand all
15011501 case Intrinsic::frameaddress:
15021502 case Intrinsic::memcpy:
15031503 case Intrinsic::memset:
1504 case Intrinsic::readport:
1505 case Intrinsic::writeport:
15041506 // We directly implement these intrinsics
15051507 break;
15061508 default:
16611663 BuildMI(BB, Opcode, 0);
16621664 return;
16631665 }
1666
1667 case Intrinsic::readport:
1668 //
1669 // First, determine that the size of the operand falls within the
1670 // acceptable range for this architecture.
1671 //
1672 assert (((CI.getOperand(1)->getType()->getPrimitiveSize()) == 2) &&
1673 "llvm.readport operand size is not a 16 bit value!");
1674
1675 //
1676 // Now, move the I/O port address into the DX register and use the IN
1677 // instruction to get the input data.
1678 //
1679 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1)));
1680 switch (CI.getCalledFunction()->getReturnType()->getPrimitiveSize()) {
1681 case 1:
1682 BuildMI(BB, X86::IN8, 1);
1683 break;
1684 case 2:
1685 BuildMI(BB, X86::IN16, 1);
1686 break;
1687 case 4:
1688 BuildMI(BB, X86::IN32, 1);
1689 break;
1690 default:
1691 assert (0 && "Cannot do input on this data type");
1692 }
1693 return;
1694
1695 case Intrinsic::writeport:
1696 //
1697 // First, determine that the size of the operand falls within the
1698 // acceptable range for this architecture.
1699 //
1700 assert (((CI.getOperand(1)->getType()->getPrimitiveSize()) == 2) &&
1701 "llvm.readport operand size is not a 16 bit value!");
1702
1703 //
1704 // Now, move the I/O port address into the DX register and the value to
1705 // write into the AL/AX/EAX register.
1706 //
1707 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1)));
1708 switch (CI.getOperand(2)->getType()->getPrimitiveSize()) {
1709 case 1:
1710 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(2)));
1711 BuildMI(BB, X86::OUT8, 1);
1712 break;
1713 case 2:
1714 BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(2)));
1715 BuildMI(BB, X86::OUT16, 1);
1716 break;
1717 case 4:
1718 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(2)));
1719 BuildMI(BB, X86::OUT32, 1);
1720 break;
1721 default:
1722 assert (0 && "Cannot do input on this data type");
1723 }
1724 return;
16641725
16651726 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
16661727 }
104104 }
105105
106106 void printImplUsesBefore(const TargetInstrDescriptor &Desc);
107 void printImplUsesAfter(const TargetInstrDescriptor &Desc);
107 bool printImplUsesAfter(const TargetInstrDescriptor &Desc, const bool LC);
108 bool printImplDefsAfter(const TargetInstrDescriptor &Desc, const bool LC);
108109 void printMachineInstruction(const MachineInstr *MI);
109110 void printOp(const MachineOperand &MO,
110111 bool elideOffsetKeyword = false);
545546 /// printImplUsesAfter - Emit the implicit-use registers for the instruction
546547 /// described by DESC, if its PrintImplUsesAfter flag is set.
547548 ///
548 void Printer::printImplUsesAfter(const TargetInstrDescriptor &Desc) {
549 /// Inputs:
550 /// Comma - List of registers will need a leading comma.
551 /// Desc - Description of the Instruction.
552 ///
553 /// Return value:
554 /// true - Emitted one or more registers.
555 /// false - Emitted no registers.
556 ///
557 bool Printer::printImplUsesAfter(const TargetInstrDescriptor &Desc,
558 const bool Comma = true) {
549559 const MRegisterInfo &RI = *TM.getRegisterInfo();
550560 if (Desc.TSFlags & X86II::PrintImplUsesAfter) {
551 for (const unsigned *p = Desc.ImplicitUses; *p; ++p) {
561 bool emitted = false;
562 const unsigned *p = Desc.ImplicitUses;
563 if (*p) {
564 O << (Comma ? ", %" : "%") << RI.get (*p).Name;
565 emitted = true;
566 ++p;
567 }
568 while (*p) {
552569 // Bug Workaround: See note in Printer::doInitialization about %.
553570 O << ", %" << RI.get(*p).Name;
554 }
555 }
571 ++p;
572 }
573 return emitted;
574 }
575 return false;
576 }
577
578 /// printImplDefsAfter - Emit the implicit-definition registers for the
579 /// instruction described by DESC, if its PrintImplDefsAfter flag is set.
580 ///
581 /// Inputs:
582 /// Comma - List of registers will need a leading comma.
583 /// Desc - Description of the Instruction
584 ///
585 /// Return value:
586 /// true - Emitted one or more registers.
587 /// false - Emitted no registers.
588 ///
589 bool Printer::printImplDefsAfter(const TargetInstrDescriptor &Desc,
590 const bool Comma = true) {
591 const MRegisterInfo &RI = *TM.getRegisterInfo();
592 if (Desc.TSFlags & X86II::PrintImplDefsAfter) {
593 bool emitted = false;
594 const unsigned *p = Desc.ImplicitDefs;
595 if (*p) {
596 O << (Comma ? ", %" : "%") << RI.get (*p).Name;
597 emitted = true;
598 ++p;
599 }
600 while (*p) {
601 // Bug Workaround: See note in Printer::doInitialization about %.
602 O << ", %" << RI.get(*p).Name;
603 ++p;
604 }
605 return emitted;
606 }
607 return false;
556608 }
557609
558610 /// printMachineInstruction -- Print out a single X86 LLVM instruction
574626 printOp(MI->getOperand(0));
575627 O << " = phi ";
576628 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
577 if (i != 1) O << ", ";
578 O << "[";
579 printOp(MI->getOperand(i));
580 O << ", ";
581 printOp(MI->getOperand(i+1));
582 O << "]";
629 if (i != 1) O << ", ";
630 O << "[";
631 printOp(MI->getOperand(i));
632 O << ", ";
633 printOp(MI->getOperand(i+1));
634 O << "]";
583635 }
584636 } else {
585637 unsigned i = 0;
586638 if (MI->getNumOperands() && MI->getOperand(0).isDef()) {
587 printOp(MI->getOperand(0));
588 O << " = ";
589 ++i;
639 printOp(MI->getOperand(0));
640 O << " = ";
641 ++i;
590642 }
591643 O << TII.getName(MI->getOpcode());
592644
593645 for (unsigned e = MI->getNumOperands(); i != e; ++i) {
594 O << " ";
595 if (MI->getOperand(i).isDef()) O << "*";
596 printOp(MI->getOperand(i));
597 if (MI->getOperand(i).isDef()) O << "*";
646 O << " ";
647 if (MI->getOperand(i).isDef()) O << "*";
648 printOp(MI->getOperand(i));
649 if (MI->getOperand(i).isDef()) O << "*";
598650 }
599651 }
600652 O << "\n";
601653 return;
602654
603655 case X86II::RawFrm:
656 {
657 bool LeadingComma = false;
658
604659 // The accepted forms of Raw instructions are:
605660 // 1. nop - No operand required
606661 // 2. jmp foo - PC relative displacement operand
616671
617672 if (MI->getNumOperands() == 1) {
618673 printOp(MI->getOperand(0), true); // Don't print "OFFSET"...
619 }
674 LeadingComma = true;
675 }
676 LeadingComma = printImplDefsAfter(Desc, LeadingComma) || LeadingComma;
677 printImplUsesAfter(Desc, LeadingComma);
620678 O << "\n";
621679 return;
680 }
622681
623682 case X86II::AddRegFrm: {
624683 // There are currently two forms of acceptable AddRegFrm instructions.
3232
3333 // Define how we want to layout our TargetSpecific information field... This
3434 // should be kept up-to-date with the fields in the X86InstrInfo.h file.
35 let TSFlagsFields = ["FormBits" , "hasOpSizePrefix" , "Prefix", "MemTypeBits",
36 "ImmTypeBits", "FPFormBits", "printImplicitUsesAfter",
37 "printImplicitUsesBefore", "Opcode"];
38 let TSFlagsShifts = [0, 5, 6, 10, 13,
39 15, 18, 19,
40 20];
35 let TSFlagsFields = ["FormBits",
36 "hasOpSizePrefix",
37 "Prefix",
38 "MemTypeBits",
39 "ImmTypeBits",
40 "FPFormBits",
41 "printImplicitUsesAfter",
42 "printImplicitUsesBefore",
43 "printImplicitDefsAfter",
44 "Opcode"];
45 let TSFlagsShifts = [0,
46 5,
47 6,
48 10,
49 13,
50 15,
51 18,
52 19,
53 20,
54 21];
4155 }
4256
4357 def X86 : Target {
104104 }
105105
106106 void printImplUsesBefore(const TargetInstrDescriptor &Desc);
107 void printImplUsesAfter(const TargetInstrDescriptor &Desc);
107 bool printImplUsesAfter(const TargetInstrDescriptor &Desc, const bool LC);
108 bool printImplDefsAfter(const TargetInstrDescriptor &Desc, const bool LC);
108109 void printMachineInstruction(const MachineInstr *MI);
109110 void printOp(const MachineOperand &MO,
110111 bool elideOffsetKeyword = false);
545546 /// printImplUsesAfter - Emit the implicit-use registers for the instruction
546547 /// described by DESC, if its PrintImplUsesAfter flag is set.
547548 ///
548 void Printer::printImplUsesAfter(const TargetInstrDescriptor &Desc) {
549 /// Inputs:
550 /// Comma - List of registers will need a leading comma.
551 /// Desc - Description of the Instruction.
552 ///
553 /// Return value:
554 /// true - Emitted one or more registers.
555 /// false - Emitted no registers.
556 ///
557 bool Printer::printImplUsesAfter(const TargetInstrDescriptor &Desc,
558 const bool Comma = true) {
549559 const MRegisterInfo &RI = *TM.getRegisterInfo();
550560 if (Desc.TSFlags & X86II::PrintImplUsesAfter) {
551 for (const unsigned *p = Desc.ImplicitUses; *p; ++p) {
561 bool emitted = false;
562 const unsigned *p = Desc.ImplicitUses;
563 if (*p) {
564 O << (Comma ? ", %" : "%") << RI.get (*p).Name;
565 emitted = true;
566 ++p;
567 }
568 while (*p) {
552569 // Bug Workaround: See note in Printer::doInitialization about %.
553570 O << ", %" << RI.get(*p).Name;
554 }
555 }
571 ++p;
572 }
573 return emitted;
574 }
575 return false;
576 }
577
578 /// printImplDefsAfter - Emit the implicit-definition registers for the
579 /// instruction described by DESC, if its PrintImplDefsAfter flag is set.
580 ///
581 /// Inputs:
582 /// Comma - List of registers will need a leading comma.
583 /// Desc - Description of the Instruction
584 ///
585 /// Return value:
586 /// true - Emitted one or more registers.
587 /// false - Emitted no registers.
588 ///
589 bool Printer::printImplDefsAfter(const TargetInstrDescriptor &Desc,
590 const bool Comma = true) {
591 const MRegisterInfo &RI = *TM.getRegisterInfo();
592 if (Desc.TSFlags & X86II::PrintImplDefsAfter) {
593 bool emitted = false;
594 const unsigned *p = Desc.ImplicitDefs;
595 if (*p) {
596 O << (Comma ? ", %" : "%") << RI.get (*p).Name;
597 emitted = true;
598 ++p;
599 }
600 while (*p) {
601 // Bug Workaround: See note in Printer::doInitialization about %.
602 O << ", %" << RI.get(*p).Name;
603 ++p;
604 }
605 return emitted;
606 }
607 return false;
556608 }
557609
558610 /// printMachineInstruction -- Print out a single X86 LLVM instruction
574626 printOp(MI->getOperand(0));
575627 O << " = phi ";
576628 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
577 if (i != 1) O << ", ";
578 O << "[";
579 printOp(MI->getOperand(i));
580 O << ", ";
581 printOp(MI->getOperand(i+1));
582 O << "]";
629 if (i != 1) O << ", ";
630 O << "[";
631 printOp(MI->getOperand(i));
632 O << ", ";
633 printOp(MI->getOperand(i+1));
634 O << "]";
583635 }
584636 } else {
585637 unsigned i = 0;
586638 if (MI->getNumOperands() && MI->getOperand(0).isDef()) {
587 printOp(MI->getOperand(0));
588 O << " = ";
589 ++i;
639 printOp(MI->getOperand(0));
640 O << " = ";
641 ++i;
590642 }
591643 O << TII.getName(MI->getOpcode());
592644
593645 for (unsigned e = MI->getNumOperands(); i != e; ++i) {
594 O << " ";
595 if (MI->getOperand(i).isDef()) O << "*";
596 printOp(MI->getOperand(i));
597 if (MI->getOperand(i).isDef()) O << "*";
646 O << " ";
647 if (MI->getOperand(i).isDef()) O << "*";
648 printOp(MI->getOperand(i));
649 if (MI->getOperand(i).isDef()) O << "*";
598650 }
599651 }
600652 O << "\n";
601653 return;
602654
603655 case X86II::RawFrm:
656 {
657 bool LeadingComma = false;
658
604659 // The accepted forms of Raw instructions are:
605660 // 1. nop - No operand required
606661 // 2. jmp foo - PC relative displacement operand
616671
617672 if (MI->getNumOperands() == 1) {
618673 printOp(MI->getOperand(0), true); // Don't print "OFFSET"...
619 }
674 LeadingComma = true;
675 }
676 LeadingComma = printImplDefsAfter(Desc, LeadingComma) || LeadingComma;
677 printImplUsesAfter(Desc, LeadingComma);
620678 O << "\n";
621679 return;
680 }
622681
623682 case X86II::AddRegFrm: {
624683 // There are currently two forms of acceptable AddRegFrm instructions.
15011501 case Intrinsic::frameaddress:
15021502 case Intrinsic::memcpy:
15031503 case Intrinsic::memset:
1504 case Intrinsic::readport:
1505 case Intrinsic::writeport:
15041506 // We directly implement these intrinsics
15051507 break;
15061508 default:
16611663 BuildMI(BB, Opcode, 0);
16621664 return;
16631665 }
1666
1667 case Intrinsic::readport:
1668 //
1669 // First, determine that the size of the operand falls within the
1670 // acceptable range for this architecture.
1671 //
1672 assert (((CI.getOperand(1)->getType()->getPrimitiveSize()) == 2) &&
1673 "llvm.readport operand size is not a 16 bit value!");
1674
1675 //
1676 // Now, move the I/O port address into the DX register and use the IN
1677 // instruction to get the input data.
1678 //
1679 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1)));
1680 switch (CI.getCalledFunction()->getReturnType()->getPrimitiveSize()) {
1681 case 1:
1682 BuildMI(BB, X86::IN8, 1);
1683 break;
1684 case 2:
1685 BuildMI(BB, X86::IN16, 1);
1686 break;
1687 case 4:
1688 BuildMI(BB, X86::IN32, 1);
1689 break;
1690 default:
1691 assert (0 && "Cannot do input on this data type");
1692 }
1693 return;
1694
1695 case Intrinsic::writeport:
1696 //
1697 // First, determine that the size of the operand falls within the
1698 // acceptable range for this architecture.
1699 //
1700 assert (((CI.getOperand(1)->getType()->getPrimitiveSize()) == 2) &&
1701 "llvm.readport operand size is not a 16 bit value!");
1702
1703 //
1704 // Now, move the I/O port address into the DX register and the value to
1705 // write into the AL/AX/EAX register.
1706 //
1707 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1)));
1708 switch (CI.getOperand(2)->getType()->getPrimitiveSize()) {
1709 case 1:
1710 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(2)));
1711 BuildMI(BB, X86::OUT8, 1);
1712 break;
1713 case 2:
1714 BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(2)));
1715 BuildMI(BB, X86::OUT16, 1);
1716 break;
1717 case 4:
1718 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(2)));
1719 BuildMI(BB, X86::OUT32, 1);
1720 break;
1721 default:
1722 assert (0 && "Cannot do input on this data type");
1723 }
1724 return;
16641725
16651726 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
16661727 }
120120 Mem128 = 6 << MemShift,
121121
122122 //===------------------------------------------------------------------===//
123 // This tow-bit field describes the size of an immediate operand. Zero is
123 // This two-bit field describes the size of an immediate operand. Zero is
124124 // unused so that we can tell if we forgot to set a value.
125125 ImmShift = 13,
126126 ImmMask = 7 << ImmShift,
168168 // before the normal operands.
169169 PrintImplUsesBefore = 1 << 19,
170170
171 OpcodeShift = 20,
171 // PrintImplDefsAfter - Print out implicit defs in the assembly output
172 // after the normal operands.
173 PrintImplDefsAfter = 1 << 20,
174
175 OpcodeShift = 21,
172176 OpcodeMask = 0xFF << OpcodeShift,
173 // Bits 25 -> 31 are unused
177 // Bits 26 -> 31 are unused
174178 };
175179 }
176180
8181 ImmType ImmT = i;
8282 bits<2> ImmTypeBits = ImmT.Value;
8383
84 //
8485 // Attributes specific to X86 instructions...
86 //
8587 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
86 bit printImplicitUsesBefore = 0; // Should we print implicit uses before this inst?
87 bit printImplicitUsesAfter = 0; // Should we print implicit uses after this inst?
88
89 // Flag whether implicit register usage is printed before/after the
90 // instruction
91 bit printImplicitUsesBefore = 0;
92 bit printImplicitUsesAfter = 0;
93
94 // Flag whether implicit register definitions are printed before/after the
95 // instruction
96 bit printImplicitDefsBefore = 0;
97 bit printImplicitDefsAfter = 0;
8898
8999 bits<4> Prefix = 0; // Which prefix byte does this inst have?
90100 FPFormat FPForm; // What flavor of FP instruction is this?
140150
141151 // Helper for shift instructions
142152 class UsesCL { list Uses = [CL]; bit printImplicitUsesAfter = 1; }
153 class PrintImpUsesAfter {bit printImplicitUsesAfter = 1;}
154 class PrintImpDefsAfter {bit printImplicitDefsAfter = 1;}
143155
144156 //===----------------------------------------------------------------------===//
145157 // Instruction list...
231243 Imp<[AX,ECX,EDI], [ECX,EDI]>;
232244 def REP_STOSD : I<"rep stosd", 0xAB, RawFrm>, REP,
233245 Imp<[EAX,ECX,EDI], [ECX,EDI]>;
246
247 //===----------------------------------------------------------------------===//
248 // Input/Output Instructions...
249 //
250 def IN8 : I<"in", 0xEC, RawFrm>, Imp<[DX],[AL]>, PrintImpUsesAfter, PrintImpDefsAfter; // in AL = I/O address DX
251 def IN16 : I<"in", 0xED, RawFrm>, Imp<[DX],[AX]>, PrintImpUsesAfter, PrintImpDefsAfter; // in AX = I/O address DX
252 def IN32 : I<"in", 0xED, RawFrm>, Imp<[DX],[EAX]>, PrintImpUsesAfter, PrintImpDefsAfter; // in EAX = I/O address DX
253
254 def OUT8 : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>, PrintImpUsesAfter;
255 def OUT16 : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, PrintImpUsesAfter;
256 def OUT32 : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>, PrintImpUsesAfter;
234257
235258 //===----------------------------------------------------------------------===//
236259 // Move Instructions...