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Add testcases for all AVX 256-bit intrinsics added in the last couple days git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110854 91177308-0d34-0410-b5e6-96231b3b80d8 Bruno Cardoso Lopes 9 years ago
1 changed file(s) with 751 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
19531953 }
19541954 declare <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16>, <8 x i16>) nounwind readnone
19551955
1956
1957 define <4 x double> @test_x86_avx_addsub_pd_256(<4 x double> %a0, <4 x double> %a1) {
1958 ; CHECK: vaddsubpd
1959 %res = call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
1960 ret <4 x double> %res
1961 }
1962 declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
1963
1964
1965 define <8 x float> @test_x86_avx_addsub_ps_256(<8 x float> %a0, <8 x float> %a1) {
1966 ; CHECK: vaddsubps
1967 %res = call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
1968 ret <8 x float> %res
1969 }
1970 declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
1971
1972
1973 define <4 x double> @test_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) {
1974 ; CHECK: vblendpd
1975 %res = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 7) ; <<4 x double>> [#uses=1]
1976 ret <4 x double> %res
1977 }
1978 declare <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double>, <4 x double>, i32) nounwind readnone
1979
1980
1981 define <8 x float> @test_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) {
1982 ; CHECK: vblendps
1983 %res = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 7) ; <<8 x float>> [#uses=1]
1984 ret <8 x float> %res
1985 }
1986 declare <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float>, <8 x float>, i32) nounwind readnone
1987
1988
1989 define <4 x double> @test_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) {
1990 ; CHECK: vblendvpd
1991 %res = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) ; <<4 x double>> [#uses=1]
1992 ret <4 x double> %res
1993 }
1994 declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>) nounwind readnone
1995
1996
1997 define <8 x float> @test_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {
1998 ; CHECK: vblendvps
1999 %res = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) ; <<8 x float>> [#uses=1]
2000 ret <8 x float> %res
2001 }
2002 declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
2003
2004
2005 define <4 x double> @test_x86_avx_cmp_pd_256(<4 x double> %a0, <4 x double> %a1) {
2006 ; CHECK: vcmpordpd
2007 %res = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> %a0, <4 x double> %a1, i8 7) ; <<4 x double>> [#uses=1]
2008 ret <4 x double> %res
2009 }
2010 declare <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone
2011
2012
2013 define <8 x float> @test_x86_avx_cmp_ps_256(<8 x float> %a0, <8 x float> %a1) {
2014 ; CHECK: vcmpordps
2015 %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
2016 ret <8 x float> %res
2017 }
2018 declare <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
2019
2020
2021 define <4 x float> @test_x86_avx_cvt_pd2_ps_256(<4 x double> %a0) {
2022 ; CHECK: vcvtpd2psy
2023 %res = call <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double> %a0) ; <<4 x float>> [#uses=1]
2024 ret <4 x float> %res
2025 }
2026 declare <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double>) nounwind readnone
2027
2028
2029 define <4 x i32> @test_x86_avx_cvt_pd2dq_256(<4 x double> %a0) {
2030 ; CHECK: vcvtpd2dqy
2031 %res = call <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1]
2032 ret <4 x i32> %res
2033 }
2034 declare <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double>) nounwind readnone
2035
2036
2037 define <4 x double> @test_x86_avx_cvt_ps2_pd_256(<4 x float> %a0) {
2038 ; CHECK: vcvtps2pd
2039 %res = call <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float> %a0) ; <<4 x double>> [#uses=1]
2040 ret <4 x double> %res
2041 }
2042 declare <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float>) nounwind readnone
2043
2044
2045 define <8 x i32> @test_x86_avx_cvt_ps2dq_256(<8 x float> %a0) {
2046 ; CHECK: vcvtps2dq
2047 %res = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1]
2048 ret <8 x i32> %res
2049 }
2050 declare <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float>) nounwind readnone
2051
2052
2053 define <4 x double> @test_x86_avx_cvtdq2_pd_256(<4 x i32> %a0) {
2054 ; CHECK: vcvtdq2pd
2055 %res = call <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32> %a0) ; <<4 x double>> [#uses=1]
2056 ret <4 x double> %res
2057 }
2058 declare <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32>) nounwind readnone
2059
2060
2061 define <8 x float> @test_x86_avx_cvtdq2_ps_256(<8 x i32> %a0) {
2062 ; CHECK: vcvtdq2ps
2063 %res = call <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32> %a0) ; <<8 x float>> [#uses=1]
2064 ret <8 x float> %res
2065 }
2066 declare <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32>) nounwind readnone
2067
2068
2069 define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) {
2070 ; CHECK: vcvttpd2dqy
2071 %res = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1]
2072 ret <4 x i32> %res
2073 }
2074 declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind readnone
2075
2076
2077 define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) {
2078 ; CHECK: vcvttps2dq
2079 %res = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1]
2080 ret <8 x i32> %res
2081 }
2082 declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind readnone
2083
2084
2085 define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) {
2086 ; CHECK: vdpps
2087 %res = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i32 7) ; <<8 x float>> [#uses=1]
2088 ret <8 x float> %res
2089 }
2090 declare <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float>, <8 x float>, i32) nounwind readnone
2091
2092
2093 define <4 x double> @test_x86_avx_hadd_pd_256(<4 x double> %a0, <4 x double> %a1) {
2094 ; CHECK: vhaddpd
2095 %res = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
2096 ret <4 x double> %res
2097 }
2098 declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>) nounwind readnone
2099
2100
2101 define <8 x float> @test_x86_avx_hadd_ps_256(<8 x float> %a0, <8 x float> %a1) {
2102 ; CHECK: vhaddps
2103 %res = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
2104 ret <8 x float> %res
2105 }
2106 declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>) nounwind readnone
2107
2108
2109 define <4 x double> @test_x86_avx_hsub_pd_256(<4 x double> %a0, <4 x double> %a1) {
2110 ; CHECK: vhsubpd
2111 %res = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
2112 ret <4 x double> %res
2113 }
2114 declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
2115
2116
2117 define <8 x float> @test_x86_avx_hsub_ps_256(<8 x float> %a0, <8 x float> %a1) {
2118 ; CHECK: vhsubps
2119 %res = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
2120 ret <8 x float> %res
2121 }
2122 declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
2123
2124
2125 define <32 x i8> @test_x86_avx_ldu_dq_256(i8* %a0) {
2126 ; CHECK: vlddqu
2127 %res = call <32 x i8> @llvm.x86.avx.ldu.dq.256(i8* %a0) ; <<32 x i8>> [#uses=1]
2128 ret <32 x i8> %res
2129 }
2130 declare <32 x i8> @llvm.x86.avx.ldu.dq.256(i8*) nounwind readonly
2131
2132
2133 define <32 x i8> @test_x86_avx_loadu_dq_256(i8* %a0) {
2134 ; CHECK: vmovdqu
2135 %res = call <32 x i8> @llvm.x86.avx.loadu.dq.256(i8* %a0) ; <<32 x i8>> [#uses=1]
2136 ret <32 x i8> %res
2137 }
2138 declare <32 x i8> @llvm.x86.avx.loadu.dq.256(i8*) nounwind readonly
2139
2140
2141 define <4 x double> @test_x86_avx_loadu_pd_256(i8* %a0) {
2142 ; CHECK: vmovupd
2143 %res = call <4 x double> @llvm.x86.avx.loadu.pd.256(i8* %a0) ; <<4 x double>> [#uses=1]
2144 ret <4 x double> %res
2145 }
2146 declare <4 x double> @llvm.x86.avx.loadu.pd.256(i8*) nounwind readonly
2147
2148
2149 define <8 x float> @test_x86_avx_loadu_ps_256(i8* %a0) {
2150 ; CHECK: vmovups
2151 %res = call <8 x float> @llvm.x86.avx.loadu.ps.256(i8* %a0) ; <<8 x float>> [#uses=1]
2152 ret <8 x float> %res
2153 }
2154 declare <8 x float> @llvm.x86.avx.loadu.ps.256(i8*) nounwind readonly
2155
2156
2157 define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x double> %a1) {
2158 ; CHECK: vmaskmovpd
2159 %res = call <2 x double> @llvm.x86.avx.maskload.pd(i8* %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
2160 ret <2 x double> %res
2161 }
2162 declare <2 x double> @llvm.x86.avx.maskload.pd(i8*, <2 x double>) nounwind readonly
2163
2164
2165 define <4 x double> @test_x86_avx_maskload_pd_256(i8* %a0, <4 x double> %a1) {
2166 ; CHECK: vmaskmovpd
2167 %res = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
2168 ret <4 x double> %res
2169 }
2170 declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8*, <4 x double>) nounwind readonly
2171
2172
2173 define <4 x float> @test_x86_avx_maskload_ps(i8* %a0, <4 x float> %a1) {
2174 ; CHECK: vmaskmovps
2175 %res = call <4 x float> @llvm.x86.avx.maskload.ps(i8* %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
2176 ret <4 x float> %res
2177 }
2178 declare <4 x float> @llvm.x86.avx.maskload.ps(i8*, <4 x float>) nounwind readonly
2179
2180
2181 define <8 x float> @test_x86_avx_maskload_ps_256(i8* %a0, <8 x float> %a1) {
2182 ; CHECK: vmaskmovps
2183 %res = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
2184 ret <8 x float> %res
2185 }
2186 declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x float>) nounwind readonly
2187
2188
2189 define void @test_x86_avx_maskstore_pd(i8* %a0, <2 x double> %a1, <2 x double> %a2) {
2190 ; CHECK: vmaskmovpd
2191 call void @llvm.x86.avx.maskstore.pd(i8* %a0, <2 x double> %a1, <2 x double> %a2)
2192 ret void
2193 }
2194 declare void @llvm.x86.avx.maskstore.pd(i8*, <2 x double>, <2 x double>) nounwind
2195
2196
2197 define void @test_x86_avx_maskstore_pd_256(i8* %a0, <4 x double> %a1, <4 x double> %a2) {
2198 ; CHECK: vmaskmovpd
2199 call void @llvm.x86.avx.maskstore.pd.256(i8* %a0, <4 x double> %a1, <4 x double> %a2)
2200 ret void
2201 }
2202 declare void @llvm.x86.avx.maskstore.pd.256(i8*, <4 x double>, <4 x double>) nounwind
2203
2204
2205 define void @test_x86_avx_maskstore_ps(i8* %a0, <4 x float> %a1, <4 x float> %a2) {
2206 ; CHECK: vmaskmovps
2207 call void @llvm.x86.avx.maskstore.ps(i8* %a0, <4 x float> %a1, <4 x float> %a2)
2208 ret void
2209 }
2210 declare void @llvm.x86.avx.maskstore.ps(i8*, <4 x float>, <4 x float>) nounwind
2211
2212
2213 define void @test_x86_avx_maskstore_ps_256(i8* %a0, <8 x float> %a1, <8 x float> %a2) {
2214 ; CHECK: vmaskmovps
2215 call void @llvm.x86.avx.maskstore.ps.256(i8* %a0, <8 x float> %a1, <8 x float> %a2)
2216 ret void
2217 }
2218 declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x float>, <8 x float>) nounwind
2219
2220
2221 define <4 x double> @test_x86_avx_max_pd_256(<4 x double> %a0, <4 x double> %a1) {
2222 ; CHECK: vmaxpd
2223 %res = call <4 x double> @llvm.x86.avx.max.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
2224 ret <4 x double> %res
2225 }
2226 declare <4 x double> @llvm.x86.avx.max.pd.256(<4 x double>, <4 x double>) nounwind readnone
2227
2228
2229 define <8 x float> @test_x86_avx_max_ps_256(<8 x float> %a0, <8 x float> %a1) {
2230 ; CHECK: vmaxps
2231 %res = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
2232 ret <8 x float> %res
2233 }
2234 declare <8 x float> @llvm.x86.avx.max.ps.256(<8 x float>, <8 x float>) nounwind readnone
2235
2236
2237 define <4 x double> @test_x86_avx_min_pd_256(<4 x double> %a0, <4 x double> %a1) {
2238 ; CHECK: vminpd
2239 %res = call <4 x double> @llvm.x86.avx.min.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
2240 ret <4 x double> %res
2241 }
2242 declare <4 x double> @llvm.x86.avx.min.pd.256(<4 x double>, <4 x double>) nounwind readnone
2243
2244
2245 define <8 x float> @test_x86_avx_min_ps_256(<8 x float> %a0, <8 x float> %a1) {
2246 ; CHECK: vminps
2247 %res = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
2248 ret <8 x float> %res
2249 }
2250 declare <8 x float> @llvm.x86.avx.min.ps.256(<8 x float>, <8 x float>) nounwind readnone
2251
2252
2253 define i32 @test_x86_avx_movmsk_pd_256(<4 x double> %a0) {
2254 ; CHECK: vmovmskpd
2255 %res = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %a0) ; [#uses=1]
2256 ret i32 %res
2257 }
2258 declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>) nounwind readnone
2259
2260
2261 define i32 @test_x86_avx_movmsk_ps_256(<8 x float> %a0) {
2262 ; CHECK: vmovmskps
2263 %res = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %a0) ; [#uses=1]
2264 ret i32 %res
2265 }
2266 declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone
2267
2268
2269 define void @test_x86_avx_movnt_dq_256(i8* %a0, <4 x i64> %a1) {
2270 ; CHECK: vmovntdq
2271 call void @llvm.x86.avx.movnt.dq.256(i8* %a0, <4 x i64> %a1)
2272 ret void
2273 }
2274 declare void @llvm.x86.avx.movnt.dq.256(i8*, <4 x i64>) nounwind
2275
2276
2277 define void @test_x86_avx_movnt_pd_256(i8* %a0, <4 x double> %a1) {
2278 ; CHECK: vmovntpd
2279 call void @llvm.x86.avx.movnt.pd.256(i8* %a0, <4 x double> %a1)
2280 ret void
2281 }
2282 declare void @llvm.x86.avx.movnt.pd.256(i8*, <4 x double>) nounwind
2283
2284
2285 define void @test_x86_avx_movnt_ps_256(i8* %a0, <8 x float> %a1) {
2286 ; CHECK: vmovntps
2287 call void @llvm.x86.avx.movnt.ps.256(i8* %a0, <8 x float> %a1)
2288 ret void
2289 }
2290 declare void @llvm.x86.avx.movnt.ps.256(i8*, <8 x float>) nounwind
2291
2292
2293 define i32 @test_x86_avx_ptestc_256(<4 x i64> %a0, <4 x i64> %a1) {
2294 ; CHECK: vptest
2295 ; CHECK: setb
2296 ; CHECK: movzbl
2297 %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a0, <4 x i64> %a1) ; [#uses=1]
2298 ret i32 %res
2299 }
2300 declare i32 @llvm.x86.avx.ptestc.256(<4 x i64>, <4 x i64>) nounwind readnone
2301
2302
2303 define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64> %a1) {
2304 ; CHECK: vptest
2305 ; CHECK: seta
2306 ; CHECK: movzbl
2307 %res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x i64> %a1) ; [#uses=1]
2308 ret i32 %res
2309 }
2310 declare i32 @llvm.x86.avx.ptestnzc.256(<4 x i64>, <4 x i64>) nounwind readnone
2311
2312
2313 define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) {
2314 ; CHECK: vptest
2315 ; CHECK: sete
2316 ; CHECK: movzbl
2317 %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x i64> %a1) ; [#uses=1]
2318 ret i32 %res
2319 }
2320 declare i32 @llvm.x86.avx.ptestz.256(<4 x i64>, <4 x i64>) nounwind readnone
2321
2322
2323 define <8 x float> @test_x86_avx_rcp_ps_256(<8 x float> %a0) {
2324 ; CHECK: vrcpps
2325 %res = call <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
2326 ret <8 x float> %res
2327 }
2328 declare <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float>) nounwind readnone
2329
2330
2331 define <4 x double> @test_x86_avx_round_pd_256(<4 x double> %a0) {
2332 ; CHECK: vroundpd
2333 %res = call <4 x double> @llvm.x86.avx.round.pd.256(<4 x double> %a0, i32 7) ; <<4 x double>> [#uses=1]
2334 ret <4 x double> %res
2335 }
2336 declare <4 x double> @llvm.x86.avx.round.pd.256(<4 x double>, i32) nounwind readnone
2337
2338
2339 define <8 x float> @test_x86_avx_round_ps_256(<8 x float> %a0) {
2340 ; CHECK: vroundps
2341 %res = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> %a0, i32 7) ; <<8 x float>> [#uses=1]
2342 ret <8 x float> %res
2343 }
2344 declare <8 x float> @llvm.x86.avx.round.ps.256(<8 x float>, i32) nounwind readnone
2345
2346
2347 define <8 x float> @test_x86_avx_rsqrt_ps_256(<8 x float> %a0) {
2348 ; CHECK: vrsqrtps
2349 %res = call <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
2350 ret <8 x float> %res
2351 }
2352 declare <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float>) nounwind readnone
2353
2354
2355 define <4 x double> @test_x86_avx_sqrt_pd_256(<4 x double> %a0) {
2356 ; CHECK: vsqrtpd
2357 %res = call <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double> %a0) ; <<4 x double>> [#uses=1]
2358 ret <4 x double> %res
2359 }
2360 declare <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double>) nounwind readnone
2361
2362
2363 define <8 x float> @test_x86_avx_sqrt_ps_256(<8 x float> %a0) {
2364 ; CHECK: vsqrtps
2365 %res = call <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
2366 ret <8 x float> %res
2367 }
2368 declare <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float>) nounwind readnone
2369
2370
2371 define void @test_x86_avx_storeu_dq_256(i8* %a0, <32 x i8> %a1) {
2372 ; CHECK: vmovdqu
2373 call void @llvm.x86.avx.storeu.dq.256(i8* %a0, <32 x i8> %a1)
2374 ret void
2375 }
2376 declare void @llvm.x86.avx.storeu.dq.256(i8*, <32 x i8>) nounwind
2377
2378
2379 define void @test_x86_avx_storeu_pd_256(i8* %a0, <4 x double> %a1) {
2380 ; CHECK: vmovupd
2381 call void @llvm.x86.avx.storeu.pd.256(i8* %a0, <4 x double> %a1)
2382 ret void
2383 }
2384 declare void @llvm.x86.avx.storeu.pd.256(i8*, <4 x double>) nounwind
2385
2386
2387 define void @test_x86_avx_storeu_ps_256(i8* %a0, <8 x float> %a1) {
2388 ; CHECK: vmovups
2389 call void @llvm.x86.avx.storeu.ps.256(i8* %a0, <8 x float> %a1)
2390 ret void
2391 }
2392 declare void @llvm.x86.avx.storeu.ps.256(i8*, <8 x float>) nounwind
2393
2394
2395 define <4 x double> @test_x86_avx_vbroadcast_sd_256(i8* %a0) {
2396 ; CHECK: vbroadcastsd
2397 %res = call <4 x double> @llvm.x86.avx.vbroadcast.sd.256(i8* %a0) ; <<4 x double>> [#uses=1]
2398 ret <4 x double> %res
2399 }
2400 declare <4 x double> @llvm.x86.avx.vbroadcast.sd.256(i8*) nounwind readonly
2401
2402
2403 define <4 x double> @test_x86_avx_vbroadcastf128_pd_256(i8* %a0) {
2404 ; CHECK: vbroadcastf128
2405 %res = call <4 x double> @llvm.x86.avx.vbroadcastf128.pd.256(i8* %a0) ; <<4 x double>> [#uses=1]
2406 ret <4 x double> %res
2407 }
2408 declare <4 x double> @llvm.x86.avx.vbroadcastf128.pd.256(i8*) nounwind readonly
2409
2410
2411 define <8 x float> @test_x86_avx_vbroadcastf128_ps_256(i8* %a0) {
2412 ; CHECK: vbroadcastf128
2413 %res = call <8 x float> @llvm.x86.avx.vbroadcastf128.ps.256(i8* %a0) ; <<8 x float>> [#uses=1]
2414 ret <8 x float> %res
2415 }
2416 declare <8 x float> @llvm.x86.avx.vbroadcastf128.ps.256(i8*) nounwind readonly
2417
2418
2419 define <4 x float> @test_x86_avx_vbroadcastss(i8* %a0) {
2420 ; CHECK: vbroadcastss
2421 %res = call <4 x float> @llvm.x86.avx.vbroadcastss(i8* %a0) ; <<4 x float>> [#uses=1]
2422 ret <4 x float> %res
2423 }
2424 declare <4 x float> @llvm.x86.avx.vbroadcastss(i8*) nounwind readonly
2425
2426
2427 define <8 x float> @test_x86_avx_vbroadcastss_256(i8* %a0) {
2428 ; CHECK: vbroadcastss
2429 %res = call <8 x float> @llvm.x86.avx.vbroadcastss.256(i8* %a0) ; <<8 x float>> [#uses=1]
2430 ret <8 x float> %res
2431 }
2432 declare <8 x float> @llvm.x86.avx.vbroadcastss.256(i8*) nounwind readonly
2433
2434
2435 define <2 x double> @test_x86_avx_vextractf128_pd_256(<4 x double> %a0) {
2436 ; CHECK: vextractf128
2437 %res = call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a0, i8 7) ; <<2 x double>> [#uses=1]
2438 ret <2 x double> %res
2439 }
2440 declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
2441
2442
2443 define <4 x float> @test_x86_avx_vextractf128_ps_256(<8 x float> %a0) {
2444 ; CHECK: vextractf128
2445 %res = call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a0, i8 7) ; <<4 x float>> [#uses=1]
2446 ret <4 x float> %res
2447 }
2448 declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
2449
2450
2451 define <4 x i32> @test_x86_avx_vextractf128_si_256(<8 x i32> %a0) {
2452 ; CHECK: vextractf128
2453 %res = call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %a0, i8 7) ; <<4 x i32>> [#uses=1]
2454 ret <4 x i32> %res
2455 }
2456 declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone
2457
2458
2459 define <4 x double> @test_x86_avx_vinsertf128_pd_256(<4 x double> %a0, <2 x double> %a1) {
2460 ; CHECK: vinsertf128
2461 %res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %a0, <2 x double> %a1, i8 7) ; <<4 x double>> [#uses=1]
2462 ret <4 x double> %res
2463 }
2464 declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone
2465
2466
2467 define <8 x float> @test_x86_avx_vinsertf128_ps_256(<8 x float> %a0, <4 x float> %a1) {
2468 ; CHECK: vinsertf128
2469 %res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %a0, <4 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
2470 ret <8 x float> %res
2471 }
2472 declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone
2473
2474
2475 define <8 x i32> @test_x86_avx_vinsertf128_si_256(<8 x i32> %a0, <4 x i32> %a1) {
2476 ; CHECK: vinsertf128
2477 %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 7) ; <<8 x i32>> [#uses=1]
2478 ret <8 x i32> %res
2479 }
2480 declare <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32>, <4 x i32>, i8) nounwind readnone
2481
2482
2483 define <4 x double> @test_x86_avx_vperm2f128_pd_256(<4 x double> %a0, <4 x double> %a1) {
2484 ; CHECK: vperm2f128
2485 %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 7) ; <<4 x double>> [#uses=1]
2486 ret <4 x double> %res
2487 }
2488 declare <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone
2489
2490
2491 define <8 x float> @test_x86_avx_vperm2f128_ps_256(<8 x float> %a0, <8 x float> %a1) {
2492 ; CHECK: vperm2f128
2493 %res = call <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
2494 ret <8 x float> %res
2495 }
2496 declare <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
2497
2498
2499 define <8 x i32> @test_x86_avx_vperm2f128_si_256(<8 x i32> %a0, <8 x i32> %a1) {
2500 ; CHECK: vperm2f128
2501 %res = call <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32> %a0, <8 x i32> %a1, i8 7) ; <<8 x i32>> [#uses=1]
2502 ret <8 x i32> %res
2503 }
2504 declare <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32>, <8 x i32>, i8) nounwind readnone
2505
2506
2507 define <2 x double> @test_x86_avx_vpermil_pd(<2 x double> %a0) {
2508 ; CHECK: vpermilpd
2509 %res = call <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double> %a0, i8 7) ; <<2 x double>> [#uses=1]
2510 ret <2 x double> %res
2511 }
2512 declare <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double>, i8) nounwind readnone
2513
2514
2515 define <4 x double> @test_x86_avx_vpermil_pd_256(<4 x double> %a0) {
2516 ; CHECK: vpermilpd
2517 %res = call <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double> %a0, i8 7) ; <<4 x double>> [#uses=1]
2518 ret <4 x double> %res
2519 }
2520 declare <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double>, i8) nounwind readnone
2521
2522
2523 define <4 x float> @test_x86_avx_vpermil_ps(<4 x float> %a0) {
2524 ; CHECK: vpermilps
2525 %res = call <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float> %a0, i8 7) ; <<4 x float>> [#uses=1]
2526 ret <4 x float> %res
2527 }
2528 declare <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float>, i8) nounwind readnone
2529
2530
2531 define <8 x float> @test_x86_avx_vpermil_ps_256(<8 x float> %a0) {
2532 ; CHECK: vpermilps
2533 %res = call <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float> %a0, i8 7) ; <<8 x float>> [#uses=1]
2534 ret <8 x float> %res
2535 }
2536 declare <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float>, i8) nounwind readnone
2537
2538
2539 define <2 x double> @test_x86_avx_vpermilvar_pd(<2 x double> %a0, <2 x i64> %a1) {
2540 ; CHECK: vpermilpd
2541 %res = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> %a1) ; <<2 x double>> [#uses=1]
2542 ret <2 x double> %res
2543 }
2544 declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>) nounwind readnone
2545
2546
2547 define <4 x double> @test_x86_avx_vpermilvar_pd_256(<4 x double> %a0, <4 x i64> %a1) {
2548 ; CHECK: vpermilpd
2549 %res = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> %a1) ; <<4 x double>> [#uses=1]
2550 ret <4 x double> %res
2551 }
2552 declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i64>) nounwind readnone
2553
2554
2555 define <4 x float> @test_x86_avx_vpermilvar_ps(<4 x float> %a0, <4 x i32> %a1) {
2556 ; CHECK: vpermilps
2557 %res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a1) ; <<4 x float>> [#uses=1]
2558 ret <4 x float> %res
2559 }
2560 declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>) nounwind readnone
2561
2562
2563 define <8 x float> @test_x86_avx_vpermilvar_ps_256(<8 x float> %a0, <8 x i32> %a1) {
2564 ; CHECK: vpermilps
2565 %res = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> %a1) ; <<8 x float>> [#uses=1]
2566 ret <8 x float> %res
2567 }
2568 declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>) nounwind readnone
2569
2570
2571 define i32 @test_x86_avx_vtestc_pd(<2 x double> %a0, <2 x double> %a1) {
2572 ; CHECK: vtestpd
2573 ; CHECK: setb
2574 ; CHECK: movzbl
2575 %res = call i32 @llvm.x86.avx.vtestc.pd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
2576 ret i32 %res
2577 }
2578 declare i32 @llvm.x86.avx.vtestc.pd(<2 x double>, <2 x double>) nounwind readnone
2579
2580
2581 define i32 @test_x86_avx_vtestc_pd_256(<4 x double> %a0, <4 x double> %a1) {
2582 ; CHECK: vtestpd
2583 ; CHECK: setb
2584 ; CHECK: movzbl
2585 %res = call i32 @llvm.x86.avx.vtestc.pd.256(<4 x double> %a0, <4 x double> %a1) ; [#uses=1]
2586 ret i32 %res
2587 }
2588 declare i32 @llvm.x86.avx.vtestc.pd.256(<4 x double>, <4 x double>) nounwind readnone
2589
2590
2591 define i32 @test_x86_avx_vtestc_ps(<4 x float> %a0, <4 x float> %a1) {
2592 ; CHECK: vtestps
2593 ; CHECK: setb
2594 ; CHECK: movzbl
2595 %res = call i32 @llvm.x86.avx.vtestc.ps(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
2596 ret i32 %res
2597 }
2598 declare i32 @llvm.x86.avx.vtestc.ps(<4 x float>, <4 x float>) nounwind readnone
2599
2600
2601 define i32 @test_x86_avx_vtestc_ps_256(<8 x float> %a0, <8 x float> %a1) {
2602 ; CHECK: vtestps
2603 ; CHECK: setb
2604 ; CHECK: movzbl
2605 %res = call i32 @llvm.x86.avx.vtestc.ps.256(<8 x float> %a0, <8 x float> %a1) ; [#uses=1]
2606 ret i32 %res
2607 }
2608 declare i32 @llvm.x86.avx.vtestc.ps.256(<8 x float>, <8 x float>) nounwind readnone
2609
2610
2611 define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x double> %a1) {
2612 ; CHECK: vtestpd
2613 ; CHECK: seta
2614 ; CHECK: movzbl
2615 %res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
2616 ret i32 %res
2617 }
2618 declare i32 @llvm.x86.avx.vtestnzc.pd(<2 x double>, <2 x double>) nounwind readnone
2619
2620
2621 define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x double> %a1) {
2622 ; CHECK: vtestpd
2623 ; CHECK: seta
2624 ; CHECK: movzbl
2625 %res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0, <4 x double> %a1) ; [#uses=1]
2626 ret i32 %res
2627 }
2628 declare i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double>, <4 x double>) nounwind readnone
2629
2630
2631 define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float> %a1) {
2632 ; CHECK: vtestps
2633 ; CHECK: seta
2634 ; CHECK: movzbl
2635 %res = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
2636 ret i32 %res
2637 }
2638 declare i32 @llvm.x86.avx.vtestnzc.ps(<4 x float>, <4 x float>) nounwind readnone
2639
2640
2641 define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x float> %a1) {
2642 ; CHECK: vtestps
2643 ; CHECK: seta
2644 ; CHECK: movzbl
2645 %res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0, <8 x float> %a1) ; [#uses=1]
2646 ret i32 %res
2647 }
2648 declare i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float>, <8 x float>) nounwind readnone
2649
2650
2651 define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double> %a1) {
2652 ; CHECK: vtestpd
2653 ; CHECK: sete
2654 ; CHECK: movzbl
2655 %res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
2656 ret i32 %res
2657 }
2658 declare i32 @llvm.x86.avx.vtestz.pd(<2 x double>, <2 x double>) nounwind readnone
2659
2660
2661 define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x double> %a1) {
2662 ; CHECK: vtestpd
2663 ; CHECK: sete
2664 ; CHECK: movzbl
2665 %res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4 x double> %a1) ; [#uses=1]
2666 ret i32 %res
2667 }
2668 declare i32 @llvm.x86.avx.vtestz.pd.256(<4 x double>, <4 x double>) nounwind readnone
2669
2670
2671 define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float> %a1) {
2672 ; CHECK: vtestps
2673 ; CHECK: sete
2674 ; CHECK: movzbl
2675 %res = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
2676 ret i32 %res
2677 }
2678 declare i32 @llvm.x86.avx.vtestz.ps(<4 x float>, <4 x float>) nounwind readnone
2679
2680
2681 define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x float> %a1) {
2682 ; CHECK: vtestps
2683 ; CHECK: sete
2684 ; CHECK: movzbl
2685 %res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8 x float> %a1) ; [#uses=1]
2686 ret i32 %res
2687 }
2688 declare i32 @llvm.x86.avx.vtestz.ps.256(<8 x float>, <8 x float>) nounwind readnone
2689
2690
2691 define void @test_x86_avx_vzeroall() {
2692 ; CHECK: vzeroall
2693 call void @llvm.x86.avx.vzeroall()
2694 ret void
2695 }
2696 declare void @llvm.x86.avx.vzeroall() nounwind
2697
2698
2699 define void @test_x86_avx_vzeroupper() {
2700 ; CHECK: vzeroupper
2701 call void @llvm.x86.avx.vzeroupper()
2702 ret void
2703 }
2704 declare void @llvm.x86.avx.vzeroupper() nounwind
2705
2706