llvm.org GIT mirror llvm / 4fc4fab
Bug fix; add super-registers sets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36296 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
1 changed file(s) with 58 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
106106 return true;
107107 }
108108
109 static void addSubReg(Record *R, Record *S,
110 std::map > &SubRegs,
111 std::map > &Aliases,
112 RegisterInfoEmitter &RIE) {
109 static void addSuperReg(Record *R, Record *S,
110 std::map > &SubRegs,
111 std::map > &SuperRegs,
112 std::map > &Aliases,
113 RegisterInfoEmitter &RIE) {
113114 if (R == S) {
114115 cerr << "Error: recursive sub-register relationship between"
115116 << " register " << RIE.getQualifiedName(R)
116117 << " and its sub-registers?\n";
117118 abort();
118119 }
120 if (!SuperRegs[R].insert(S).second)
121 return;
122 SubRegs[S].insert(R);
123 Aliases[R].insert(S);
124 Aliases[S].insert(R);
125 if (SuperRegs.count(S))
126 for (std::set::iterator I = SuperRegs[S].begin(),
127 E = SuperRegs[S].end(); I != E; ++I)
128 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
129 }
130
131 static void addSubSuperReg(Record *R, Record *S,
132 std::map > &SubRegs,
133 std::map > &SuperRegs,
134 std::map > &Aliases,
135 RegisterInfoEmitter &RIE) {
136 if (R == S) {
137 cerr << "Error: recursive sub-register relationship between"
138 << " register " << RIE.getQualifiedName(R)
139 << " and its sub-registers?\n";
140 abort();
141 }
119142
120143 if (!SubRegs[R].insert(S).second)
121144 return;
145 addSuperReg(S, R, SubRegs, SuperRegs, Aliases, RIE);
122146 Aliases[R].insert(S);
123147 Aliases[S].insert(R);
124148 if (SubRegs.count(S))
125149 for (std::set::iterator I = SubRegs[S].begin(),
126150 E = SubRegs[S].end(); I != E; ++I)
127 addSubReg(R, *I, SubRegs, Aliases, RIE);
151 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
128152 }
129153
130154 // RegisterInfoEmitter::run - Main register file description emitter.
293317 << "RegClass,\n";
294318 OS << " };\n";
295319
296 // Emit register sub-registers / aliases...
320 // Emit register sub-registers / super-registers, aliases...
297321 std::map > RegisterSubRegs;
322 std::map > RegisterSuperRegs;
298323 std::map > RegisterAliases;
299324 const std::vector &Regs = Target.getRegisters();
300325
319344 }
320345 }
321346
347 // Process sub-register sets.
322348 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
323349 Record *R = Regs[i].TheDef;
324350 std::vector LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
329355 cerr << "Warning: register " << getQualifiedName(SubReg)
330356 << " specified as a sub-register of " << getQualifiedName(R)
331357 << " multiple times!\n";
332 addSubReg(R, SubReg, RegisterSubRegs, RegisterAliases, *this);
358 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
359 RegisterAliases, *this);
333360 }
334361 }
335362
364391 OS << getQualifiedName(*ASI) << ", ";
365392 OS << "0 };\n";
366393 }
394
395 if (!RegisterSuperRegs.empty())
396 OS << "\n\n // Register Super-registers Sets...\n";
397
398 // Emit the empty super-registers list
399 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
400 // Loop over all of the registers which have super-registers, emitting the
401 // super-registers list to memory.
402 for (std::map >::iterator
403 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
404 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
405 for (std::set::iterator ASI = I->second.begin(),
406 E = I->second.end(); ASI != E; ++ASI)
407 OS << getQualifiedName(*ASI) << ", ";
408 OS << "0 };\n";
409 }
410
367411 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
368 OS << " { \"NOREG\",\t0,\t0 },\n";
369
412 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
370413
371414 // Now that register alias and sub-registers sets have been emitted, emit the
372415 // register descriptors now.
384427 else
385428 OS << "Empty_AliasSet,\t";
386429 if (RegisterSubRegs.count(Reg.TheDef))
387 OS << Reg.getName() << "_SubRegsSet },\n";
430 OS << Reg.getName() << "_SubRegsSet,\t";
388431 else
389 OS << "Empty_SubRegsSet },\n";
432 OS << "Empty_SubRegsSet,\t";
433 if (RegisterSuperRegs.count(Reg.TheDef))
434 OS << Reg.getName() << "_SuperRegsSet },\n";
435 else
436 OS << "Empty_SuperRegsSet },\n";
390437 }
391438 OS << " };\n"; // End of register descriptors...
392439 OS << "}\n\n"; // End of anonymous namespace...