llvm.org GIT mirror llvm / 4f70921
This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci, as pldw does not have a literal variant (i.e. pc relative version) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187804 91177308-0d34-0410-b5e6-96231b3b80d8 Mihai Popa 7 years ago
4 changed file(s) with 36 addition(s) and 32 deletion(s). Raw diff Collapse all Expand all
16031603
16041604 let DecoderMethod = "DecodeT2LoadShift";
16051605 }
1606
1607 // pci variant is very similar to i12, but supports negative offsets
1608 // from the PC.
1609 def pci : T2Iso<(outs), (ins t2ldrlabel:$addr), IIC_Preload, opc,
1610 "\t$addr",
1611 [(ARMPreload (ARMWrapper tconstpool:$addr),
1612 (i32 write), (i32 instr))]>,
1613 Sched<[WritePreLd]> {
1614 let Inst{31-25} = 0b1111100;
1615 let Inst{24} = instr;
1616 let Inst{22} = 0;
1617 let Inst{21} = write;
1618 let Inst{20} = 1;
1619 let Inst{19-16} = 0b1111;
1620 let Inst{15-12} = 0b1111;
1621
1622 bits<13> addr;
1623 let Inst{23} = addr{12}; // add = (U == '1')
1624 let Inst{11-0} = addr{11-0}; // imm12
1625
1626 let DecoderMethod = "DecodeT2LoadLabel";
1627 }
1628 }
1629
1630 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1631 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1632 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1606 }
1607
1608 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1609 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1610 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1611
1612 // pci variant is very similar to i12, but supports negative offsets
1613 // from the PC. Only PLD and PLI have pci variants (not PLDW)
1614 class T2Iplpci inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
1615 IIC_Preload, opc, "\t$addr",
1616 [(ARMPreload (ARMWrapper tconstpool:$addr),
1617 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
1618 let Inst{31-25} = 0b1111100;
1619 let Inst{24} = inst;
1620 let Inst{22-20} = 0b001;
1621 let Inst{19-16} = 0b1111;
1622 let Inst{15-12} = 0b1111;
1623
1624 bits<13> addr;
1625 let Inst{23} = addr{12}; // add = (U == '1')
1626 let Inst{11-0} = addr{11-0}; // imm12
1627
1628 let DecoderMethod = "DecodeT2LoadLabel";
1629 }
1630
1631 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
1632 def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
16331633
16341634 //===----------------------------------------------------------------------===//
16351635 // Load / store multiple Instructions.
44244424 // PLD/PLDW/PLI with alternate literal form.
44254425 def : t2InstAlias<"pld${p} $addr",
44264426 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
4427 def : InstAlias<"pldw${p} $addr",
4428 (t2PLDWpci t2ldr_pcrel_imm12:$addr, pred:$p)>,
4429 Requires<[IsThumb2,HasV7,HasMP]>;
44304427 def : InstAlias<"pli${p} $addr",
44314428 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p)>,
44324429 Requires<[IsThumb2,HasV7]>;
33533353 switch (Inst.getOpcode()) {
33543354 case ARM::t2PLDi8:
33553355 case ARM::t2PLIi8:
3356 case ARM::t2PLDWi8:
33563357 break;
33573358 default:
33583359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
34163417
34173418 switch (Inst.getOpcode()) {
34183419 case ARM::t2PLDi12:
3420 case ARM::t2PLDWi12:
34193421 case ARM::t2PLIi12:
34203422 break;
34213423 default:
155155 @ CHECK-ERRORS: yield
156156 @ CHECK-ERRORS: ^
157157
158 @------------------------------------------------------------------------------
159 @ PLDW required mp-extensions
160 @------------------------------------------------------------------------------
161 pldw [r0, #4]
162 @ CHECK-ERRORS: error: instruction requires: mp-extensions
22 @------------------------------------------------------------------------------
33 @ PLD(literal)
44 @------------------------------------------------------------------------------
5 pldw [pc,#-4095]
6 @ CHECK: pldw [pc, #-4095] @ encoding: [0x3f,0xf8,0xff,0xff]
5 pldw [r0, #257]
6 @ CHECK: pldw [r0, #257] @ encoding: [0xb0,0xf8,0x01,0xf1]