llvm.org GIT mirror llvm / 4f529ec
[ARM] GlobalISel: Fixup r307365 Rename member DebugLoc -> DbgLoc (so it doesn't conflict with the class name). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307366 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 3 years ago
1 changed file(s) with 10 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
330330 const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI,
331331 const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
332332 : MBB(*MIB->getParent()), InsertBefore(std::next(MIB->getIterator())),
333 DebugLoc(MIB->getDebugLoc()), TII(TII), MRI(MRI), TRI(TRI), RBI(RBI),
333 DbgLoc(MIB->getDebugLoc()), TII(TII), MRI(MRI), TRI(TRI), RBI(RBI),
334334 Selector(Selector) {}
335335
336336 // The opcode used for performing the comparison.
357357 }
358358
359359 void putConstant(unsigned DestReg, unsigned Constant) {
360 (void)BuildMI(MBB, InsertBefore, DebugLoc, TII.get(ARM::MOVi))
360 (void)BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::MOVi))
361361 .addDef(DestReg)
362362 .addImm(Constant)
363363 .add(predOps(ARMCC::AL))
368368 unsigned RHSReg, unsigned PrevRes) {
369369
370370 // Perform the comparison.
371 auto CmpI = BuildMI(MBB, InsertBefore, DebugLoc, TII.get(ComparisonOpcode))
371 auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ComparisonOpcode))
372372 .addUse(LHSReg)
373373 .addUse(RHSReg)
374374 .add(predOps(ARMCC::AL));
377377
378378 // Read the comparison flags (if necessary).
379379 if (ReadFlagsOpcode != ARM::INSTRUCTION_LIST_END) {
380 auto ReadI =
381 BuildMI(MBB, InsertBefore, DebugLoc, TII.get(ReadFlagsOpcode))
382 .add(predOps(ARMCC::AL));
380 auto ReadI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ReadFlagsOpcode))
381 .add(predOps(ARMCC::AL));
383382 if (!Selector.constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI))
384383 return false;
385384 }
386385
387386 // Select either 1 or the previous result based on the value of the flags.
388 auto Mov1I = BuildMI(MBB, InsertBefore, DebugLoc, TII.get(SetResultOpcode))
387 auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(SetResultOpcode))
389388 .addDef(ResReg)
390389 .addUse(PrevRes)
391390 .addImm(1)
435434
436435 MachineBasicBlock &MBB;
437436 MachineBasicBlock::instr_iterator InsertBefore;
438 const DebugLoc &DebugLoc;
437 const DebugLoc &DbgLoc;
439438
440439 const ARMBaseInstrInfo &TII;
441440 MachineRegisterInfo &MRI;
526525 const RegisterBankInfo &RBI) const {
527526 auto &MBB = *MIB->getParent();
528527 auto InsertBefore = std::next(MIB->getIterator());
529 auto &DebugLoc = MIB->getDebugLoc();
528 auto &DbgLoc = MIB->getDebugLoc();
530529
531530 // Compare the condition to 0.
532531 auto CondReg = MIB->getOperand(1).getReg();
533532 assert(MRI.getType(CondReg).getSizeInBits() == 1 &&
534533 RBI.getRegBank(CondReg, MRI, TRI)->getID() == ARM::GPRRegBankID &&
535534 "Unsupported types for select operation");
536 auto CmpI = BuildMI(MBB, InsertBefore, DebugLoc, TII.get(ARM::CMPri))
535 auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::CMPri))
537536 .addUse(CondReg)
538537 .addImm(0)
539538 .add(predOps(ARMCC::AL));
551550 RBI.getRegBank(TrueReg, MRI, TRI)->getID() == ARM::GPRRegBankID &&
552551 RBI.getRegBank(FalseReg, MRI, TRI)->getID() == ARM::GPRRegBankID &&
553552 "Unsupported types for select operation");
554 auto Mov1I = BuildMI(MBB, InsertBefore, DebugLoc, TII.get(ARM::MOVCCr))
553 auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::MOVCCr))
555554 .addDef(ResReg)
556555 .addUse(TrueReg)
557556 .addUse(FalseReg)