llvm.org GIT mirror llvm / 4f38b38
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for several things other than Neon vector lane numbers. For inline assembly operands with a "c" print code, check that they really are immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79676 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
5 changed file(s) with 20 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
326326 let MIOperandInfo = (ops GPR, i32imm);
327327 }
328328
329 def lane_cst : Operand {
330 let PrintMethod = "printLaneOperand";
329 def nohash_imm : Operand {
330 let PrintMethod = "printNoHashImmediate";
331331 }
332332
333333 //===----------------------------------------------------------------------===//
580580 []>;
581581
582582 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
583 (ins i32imm:$label, lane_cst:$id, pred:$p),
583 (ins i32imm:$label, nohash_imm:$id, pred:$p),
584584 Pseudo, IIC_iALUi,
585585 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
586586 "(${label}_${id}-(",
16571657 // VMOV : Vector Get Lane (move scalar to ARM core register)
16581658
16591659 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1660 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1660 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
16611661 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
16621662 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
16631663 imm:$lane))]>;
16641664 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1665 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1665 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
16661666 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
16671667 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
16681668 imm:$lane))]>;
16691669 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1670 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1670 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
16711671 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
16721672 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
16731673 imm:$lane))]>;
16741674 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1675 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1675 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
16761676 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
16771677 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
16781678 imm:$lane))]>;
16791679 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1680 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1680 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
16811681 NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
16821682 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
16831683 imm:$lane))]>;
17141714
17151715 let Constraints = "$src1 = $dst" in {
17161716 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1717 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1717 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
17181718 NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
17191719 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
17201720 GPR:$src2, imm:$lane))]>;
17211721 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1722 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1722 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
17231723 NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
17241724 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
17251725 GPR:$src2, imm:$lane))]>;
17261726 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1727 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1727 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
17281728 NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
17291729 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
17301730 GPR:$src2, imm:$lane))]>;
17871787
17881788 class VDUPLND op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
17891789 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1790 (outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1790 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
17911791 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
17921792 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
17931793
17941794 class VDUPLNQ op19_18, bits<2> op17_16, string OpcodeStr,
17951795 ValueType ResTy, ValueType OpTy>
17961796 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1797 (outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1797 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
17981798 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
17991799 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
18001800
631631 "adr$p $dst, #$label", []>;
632632
633633 def tLEApcrelJT : T1I<(outs tGPR:$dst),
634 (ins i32imm:$label, lane_cst:$id, pred:$p),
634 (ins i32imm:$label, nohash_imm:$id, pred:$p),
635635 IIC_iALUi, "adr$p $dst, #${label}_${id}", []>;
636636
637637 //===----------------------------------------------------------------------===//
430430 "adr$p.w $dst, #$label", []>;
431431
432432 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
433 (ins i32imm:$label, lane_cst:$id, pred:$p), IIC_iALUi,
433 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
434434 "adr$p.w $dst, #${label}_${id}", []>;
435435
436436 // ADD r, sp, {so_imm|i12}
163163 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
164164 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
165165 void printTBAddrMode(const MachineInstr *MI, int OpNum);
166 void printLaneOperand(const MachineInstr *MI, int OpNum);
166 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
167167
168168 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
169169 unsigned AsmVariant, const char *ExtraCode);
10091009 O << ']';
10101010 }
10111011
1012 void ARMAsmPrinter::printLaneOperand(const MachineInstr *MI, int OpNum) {
1012 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
10131013 O << MI->getOperand(OpNum).getImm();
10141014 }
10151015
10281028 }
10291029 // Fallthrough
10301030 case 'c': // Don't print "#" before an immediate operand.
1031 printLaneOperand(MI, OpNum);
1031 if (!MI->getOperand(OpNum).isImm())
1032 return true;
1033 printNoHashImmediate(MI, OpNum);
10321034 return false;
10331035 case 'P': // Print a VFP double precision register.
10341036 printOperand(MI, OpNum);