llvm.org GIT mirror llvm / 4ed822d
[MCA] Don't assume that createMCInstrAnalysis() always returns a valid pointer. Class InstrBuilder wrongly assumed that llvm targets were always able to return a non-null pointer when createMCInstrAnalysis() was called on them. This was causing crashes when simulating executions for targets that don't provide an MCInstrAnalysis object. This patch fixes the issue by making MCInstrAnalysis optional. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349352 91177308-0d34-0410-b5e6-96231b3b80d8 Andrea Di Biagio 9 months ago
5 changed file(s) with 91 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
3939 const MCSubtargetInfo &STI;
4040 const MCInstrInfo &MCII;
4141 const MCRegisterInfo &MRI;
42 const MCInstrAnalysis &MCIA;
42 const MCInstrAnalysis *MCIA;
4343 SmallVector ProcResourceMasks;
4444
4545 DenseMap> Descriptors;
6060
6161 public:
6262 InstrBuilder(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
63 const MCRegisterInfo &RI, const MCInstrAnalysis &IA);
63 const MCRegisterInfo &RI, const MCInstrAnalysis *IA);
6464
6565 void clear() {
6666 VariantDescriptors.shrink_and_clear();
2727 InstrBuilder::InstrBuilder(const llvm::MCSubtargetInfo &sti,
2828 const llvm::MCInstrInfo &mcii,
2929 const llvm::MCRegisterInfo &mri,
30 const llvm::MCInstrAnalysis &mcia)
30 const llvm::MCInstrAnalysis *mcia)
3131 : STI(sti), MCII(mcii), MRI(mri), MCIA(mcia), FirstCallInst(true),
3232 FirstReturnInst(true) {
3333 computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks);
586586 // Check if this is a dependency breaking instruction.
587587 APInt Mask;
588588
589 unsigned ProcID = STI.getSchedModel().getProcessorID();
590 bool IsZeroIdiom = MCIA.isZeroIdiom(MCI, Mask, ProcID);
591 bool IsDepBreaking =
592 IsZeroIdiom || MCIA.isDependencyBreaking(MCI, Mask, ProcID);
593 if (MCIA.isOptimizableRegisterMove(MCI, ProcID))
594 NewIS->setOptimizableMove();
589 bool IsZeroIdiom = false;
590 bool IsDepBreaking = false;
591 if (MCIA) {
592 unsigned ProcID = STI.getSchedModel().getProcessorID();
593 IsZeroIdiom = MCIA->isZeroIdiom(MCI, Mask, ProcID);
594 IsDepBreaking =
595 IsZeroIdiom || MCIA->isDependencyBreaking(MCI, Mask, ProcID);
596 if (MCIA->isOptimizableRegisterMove(MCI, ProcID))
597 NewIS->setOptimizableMove();
598 }
595599
596600 // Initialize Reads first.
597601 for (const ReadDescriptor &RD : D.Reads) {
648652
649653 // Now query the MCInstrAnalysis object to obtain information about which
650654 // register writes implicitly clear the upper portion of a super-register.
651 MCIA.clearsSuperRegisters(MRI, MCI, WriteMask);
655 if (MCIA)
656 MCIA->clearsSuperRegisters(MRI, MCI, WriteMask);
652657
653658 // Initialize writes.
654659 unsigned WriteIndex = 0;
0 if not 'SystemZ' in config.root.targets:
1 config.unsupported = True
2
0 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
1 # RUN: llvm-mca -mtriple=s390x-linux-gnu -mcpu=z14 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
2
3 stmg %r6, %r15, 48(%r15)
4 lmg %r6, %r15, 48(%r15)
5
6 # CHECK: Iterations: 100
7 # CHECK-NEXT: Instructions: 200
8 # CHECK-NEXT: Total Cycles: 1003
9 # CHECK-NEXT: Total uOps: 600
10
11 # CHECK: Dispatch Width: 6
12 # CHECK-NEXT: uOps Per Cycle: 0.60
13 # CHECK-NEXT: IPC: 0.20
14 # CHECK-NEXT: Block RThroughput: 3.5
15
16 # CHECK: Instruction Info:
17 # CHECK-NEXT: [1]: #uOps
18 # CHECK-NEXT: [2]: Latency
19 # CHECK-NEXT: [3]: RThroughput
20 # CHECK-NEXT: [4]: MayLoad
21 # CHECK-NEXT: [5]: MayStore
22 # CHECK-NEXT: [6]: HasSideEffects (U)
23
24 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
25 # CHECK-NEXT: 3 1 1.50 * stmg %r6, %r15, 48(%r15)
26 # CHECK-NEXT: 3 10 2.50 * lmg %r6, %r15, 48(%r15)
27
28 # CHECK: Resources:
29 # CHECK-NEXT: [0.0] - Z14_FXaUnit
30 # CHECK-NEXT: [0.1] - Z14_FXaUnit
31 # CHECK-NEXT: [1.0] - Z14_FXbUnit
32 # CHECK-NEXT: [1.1] - Z14_FXbUnit
33 # CHECK-NEXT: [2.0] - Z14_LSUnit
34 # CHECK-NEXT: [2.1] - Z14_LSUnit
35 # CHECK-NEXT: [3] - Z14_MCD
36 # CHECK-NEXT: [4.0] - Z14_VBUnit
37 # CHECK-NEXT: [4.1] - Z14_VBUnit
38 # CHECK-NEXT: [5.0] - Z14_VecFPdUnit
39 # CHECK-NEXT: [5.1] - Z14_VecFPdUnit
40 # CHECK-NEXT: [6.0] - Z14_VecUnit
41 # CHECK-NEXT: [6.1] - Z14_VecUnit
42
43 # CHECK: Resource pressure per iteration:
44 # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1]
45 # CHECK-NEXT: - - 1.50 1.50 2.06 4.94 - - - - - - -
46
47 # CHECK: Resource pressure by instruction:
48 # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] Instructions:
49 # CHECK-NEXT: - - 1.50 1.50 1.96 0.04 - - - - - - - stmg %r6, %r15, 48(%r15)
50 # CHECK-NEXT: - - - - 0.10 4.90 - - - - - - - lmg %r6, %r15, 48(%r15)
51
52 # CHECK: Timeline view:
53 # CHECK-NEXT: 0123456789 012
54 # CHECK-NEXT: Index 0123456789 0123456789
55
56 # CHECK: [0,0] DeER . . . . . . . stmg %r6, %r15, 48(%r15)
57 # CHECK-NEXT: [0,1] DeeeeeeeeeeER . . . . . lmg %r6, %r15, 48(%r15)
58 # CHECK-NEXT: [1,0] .D=========eER . . . . . stmg %r6, %r15, 48(%r15)
59 # CHECK-NEXT: [1,1] .D=========eeeeeeeeeeER . . . lmg %r6, %r15, 48(%r15)
60 # CHECK-NEXT: [2,0] . D==================eER . . . stmg %r6, %r15, 48(%r15)
61 # CHECK-NEXT: [2,1] . D==================eeeeeeeeeeER lmg %r6, %r15, 48(%r15)
62
63 # CHECK: Average Wait times (based on the timeline view):
64 # CHECK-NEXT: [0]: Executions
65 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
66 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
67 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
68
69 # CHECK: [0] [1] [2] [3]
70 # CHECK-NEXT: 0. 3 10.0 0.3 0.0 stmg %r6, %r15, 48(%r15)
71 # CHECK-NEXT: 1. 3 10.0 0.3 0.0 lmg %r6, %r15, 48(%r15)
377377 Width = DispatchWidth;
378378
379379 // Create an instruction builder.
380 mca::InstrBuilder IB(*STI, *MCII, *MRI, *MCIA);
380 mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get());
381381
382382 // Create a context to control ownership of the pipeline hardware.
383383 mca::Context MCA(*MRI, *STI);