llvm.org GIT mirror llvm / 4ec858e
Have TargetRegisterInfo::getLargestLegalSuperClass take a MachineFunction argument so that it can look up the subtarget rather than using a cached one in some Targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231888 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 5 years ago
13 changed file(s) with 33 addition(s) and 24 deletion(s). Raw diff Collapse all Expand all
621621 /// legal to use in the current sub-target and has the same spill size.
622622 /// The returned register class can be used to create virtual registers which
623623 /// means that all its registers can be copied and spilled.
624 virtual const TargetRegisterClass*
625 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
624 virtual const TargetRegisterClass *
625 getLargestLegalSuperClass(const TargetRegisterClass *RC,
626 const MachineFunction &) const {
626627 /// The default implementation is very conservative and doesn't allow the
627628 /// register allocator to inflate register classes.
628629 return RC;
6464 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
6565 const TargetRegisterClass *OldRC = getRegClass(Reg);
6666 const TargetRegisterClass *NewRC =
67 getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC);
67 getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF);
6868
6969 // Stop early if there is no room to grow.
7070 if (NewRC == OldRC)
926926 TII->getRegClass(MCID, MONum, TRI, *MF)) {
927927 if (SubIdx) {
928928 const TargetRegisterClass *SuperRC =
929 TRI->getLargestLegalSuperClass(RC);
929 TRI->getLargestLegalSuperClass(RC, *MF);
930930 if (!SuperRC) {
931931 report("No largest legal super class exists.", MO, MONum);
932932 return;
15531553
15541554 DEBUG(dbgs() << "Split around " << Uses.size() << " individual instrs.\n");
15551555
1556 const TargetRegisterClass *SuperRC = TRI->getLargestLegalSuperClass(CurRC);
1556 const TargetRegisterClass *SuperRC =
1557 TRI->getLargestLegalSuperClass(CurRC, *MF);
15571558 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
15581559 // Split around every non-copy instruction if this split will relax
15591560 // the constraints on the virtual register.
130130 RCI.NumRegs = StressRA;
131131
132132 // Check if RC is a proper sub-class.
133 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
133 if (const TargetRegisterClass *Super =
134 TRI->getLargestLegalSuperClass(RC, *MF))
134135 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
135136 RCI.ProperSubClass = true;
136137
149149 return Reserved;
150150 }
151151
152 const TargetRegisterClass*
153 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
154 const {
152 const TargetRegisterClass *
153 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
154 const MachineFunction &) const {
155155 const TargetRegisterClass *Super = RC;
156156 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
157157 do {
123123 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
124124
125125 const TargetRegisterClass *
126 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
126 getLargestLegalSuperClass(const TargetRegisterClass *RC,
127 const MachineFunction &MF) const override;
127128
128129 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
129130 MachineFunction &MF) const override;
4141 : ARMBaseRegisterInfo(sti) {
4242 }
4343
44 const TargetRegisterClass*
45 Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
46 const {
44 const TargetRegisterClass *
45 Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
46 const MachineFunction &MF) const {
4747 if (ARM::tGPRRegClass.hasSubClassEq(RC))
4848 return &ARM::tGPRRegClass;
49 return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC);
49 return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC, MF);
5050 }
5151
5252 const TargetRegisterClass *
2626 Thumb1RegisterInfo(const ARMSubtarget &STI);
2727
2828 const TargetRegisterClass *
29 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
29 getLargestLegalSuperClass(const TargetRegisterClass *RC,
30 const MachineFunction &MF) const override;
3031
3132 const TargetRegisterClass *
3233 getPointerRegClass(const MachineFunction &MF,
287287 }
288288 }
289289
290 const TargetRegisterClass *PPCRegisterInfo::getLargestLegalSuperClass(
291 const TargetRegisterClass *RC) const {
290 const TargetRegisterClass *
291 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
292 const MachineFunction &MF) const {
292293 if (Subtarget.hasVSX()) {
293294 // With VSX, we can inflate various sub-register classes to the full VSX
294295 // register set.
299300 return &PPC::VSRCRegClass;
300301 }
301302
302 return TargetRegisterInfo::getLargestLegalSuperClass(RC);
303 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
303304 }
304305
305306 //===----------------------------------------------------------------------===//
3939 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
4040 MachineFunction &MF) const override;
4141
42 const TargetRegisterClass*
43 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
42 const TargetRegisterClass *
43 getLargestLegalSuperClass(const TargetRegisterClass *RC,
44 const MachineFunction &MF) const override;
4445
4546 /// Code Generation virtual methods...
4647 const MCPhysReg *
119119 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
120120 }
121121
122 const TargetRegisterClass*
123 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
122 const TargetRegisterClass *
123 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
124 const MachineFunction &MF) const {
124125 // Don't allow super-classes of GR8_NOREX. This class is only used after
125126 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
126127 // to the full GR8 register class in 64-bit mode, so we cannot allow the
7575 getSubClassWithSubReg(const TargetRegisterClass *RC,
7676 unsigned Idx) const override;
7777
78 const TargetRegisterClass*
79 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
78 const TargetRegisterClass *
79 getLargestLegalSuperClass(const TargetRegisterClass *RC,
80 const MachineFunction &MF) const override;
8081
8182 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
8283 /// values.