llvm.org GIT mirror llvm / 4e6cb18
[AArch64][GlobalISel] Add support for narrowScalar of G_ZEXT We do this by merging the source with the high bits set to 0. Differential Revision: https://reviews.llvm.org/D66181 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369480 91177308-0d34-0410-b5e6-96231b3b80d8 Amara Emerson 1 year, 30 days ago
6 changed file(s) with 95 addition(s) and 29 deletion(s). Raw diff Collapse all Expand all
611611 MIRBuilder.buildConstant(LLT::scalar(64), NarrowTy.getSizeInBits() - 1);
612612 auto Shift = MIRBuilder.buildAShr(NarrowTy, SrcReg, ShiftAmt);
613613 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)});
614 MI.eraseFromParent();
615 return Legalized;
616 }
617 case TargetOpcode::G_ZEXT: {
618 if (TypeIdx != 0)
619 return UnableToLegalize;
620
621 if (SizeOp0 % NarrowTy.getSizeInBits() != 0)
622 return UnableToLegalize;
623
624 // Generate a merge where the bottom bits are taken from the source, and
625 // zero everything else.
626 Register ZeroReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0);
627 unsigned NumParts = SizeOp0 / NarrowTy.getSizeInBits();
628 SmallVector Srcs = {MI.getOperand(1).getReg()};
629 for (unsigned Part = 1; Part < NumParts; ++Part)
630 Srcs.push_back(ZeroReg);
631 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
614632 MI.eraseFromParent();
615633 return Legalized;
616634 }
340340 unsigned DstSize = Query.Types[0].getSizeInBits();
341341
342342 if (DstSize == 128 && !Query.Types[0].isVector())
343 return false; // Extending to a scalar s128 is not legal.
343 return false; // Extending to a scalar s128 needs narrowing.
344344
345345 // Make sure that we have something that will fit in a register, and
346346 // make sure it's a power of 2.
362362
363363 return true;
364364 };
365 getActionDefinitionsBuilder({G_ZEXT, G_ANYEXT}).legalIf(ExtLegalFunc);
366 getActionDefinitionsBuilder(G_SEXT)
365 getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
367366 .legalIf(ExtLegalFunc)
368367 .clampScalar(0, s64, s64); // Just for s128, others are handled above.
369368
4545 if (X86::GR8RegClass.hasSubClassEq(&RC) ||
4646 X86::GR16RegClass.hasSubClassEq(&RC) ||
4747 X86::GR32RegClass.hasSubClassEq(&RC) ||
48 X86::GR64RegClass.hasSubClassEq(&RC))
48 X86::GR64RegClass.hasSubClassEq(&RC) ||
49 X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) ||
50 X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC))
4951 return getRegBank(X86::GPRRegBankID);
5052
5153 if (X86::FR32XRegClass.hasSubClassEq(&RC) ||
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test/CodeGen/AArch64/GlobalISel/legalize-sext-128.mir less more
None # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
2 ---
3 name: narrow_s128
4 tracksRegLiveness: true
5 body: |
6 bb.1:
7 liveins: $x0, $x1
8
9 ; CHECK-LABEL: name: narrow_s128
10 ; CHECK: liveins: $x0, $x1
11 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
12 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
13 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
14 ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
15 ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](s64)
16 ; CHECK: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store 16)
17 ; CHECK: RET_ReallyLR
18 %0:_(s64) = COPY $x0
19 %1:_(p0) = COPY $x1
20 %2:_(s128) = G_SEXT %0(s64)
21 G_STORE %2(s128), %1(p0) :: (store 16)
22 RET_ReallyLR
23
24 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
2 ---
3 name: narrow_sext_s128
4 tracksRegLiveness: true
5 body: |
6 bb.1:
7 liveins: $x0, $x1
8
9 ; CHECK-LABEL: name: narrow_sext_s128
10 ; CHECK: liveins: $x0, $x1
11 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
12 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
13 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
14 ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
15 ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](s64)
16 ; CHECK: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store 16)
17 ; CHECK: RET_ReallyLR
18 %0:_(s64) = COPY $x0
19 %1:_(p0) = COPY $x1
20 %2:_(s128) = G_SEXT %0(s64)
21 G_STORE %2(s128), %1(p0) :: (store 16)
22 RET_ReallyLR
23
24 ...
25 ---
26 name: narrow_zext_s128
27 tracksRegLiveness: true
28 body: |
29 bb.1:
30 liveins: $x0, $x1
31
32 ; CHECK-LABEL: name: narrow_zext_s128
33 ; CHECK: liveins: $x0, $x1
34 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
35 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
36 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
37 ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64)
38 ; CHECK: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store 16)
39 ; CHECK: RET_ReallyLR
40 %0:_(s64) = COPY $x0
41 %1:_(p0) = COPY $x1
42 %2:_(s128) = G_ZEXT %0(s64)
43 G_STORE %2(s128), %1(p0) :: (store 16)
44 RET_ReallyLR
45
46 ...
47 ---
48 name: narrow_zext_s192
49 tracksRegLiveness: true
50 body: |
51 bb.1:
52 liveins: $x0, $x1
53
54 ; CHECK-LABEL: name: narrow_zext_s192
55 ; CHECK: liveins: $x0, $x1
56 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
57 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
58 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
59 ; CHECK: [[MV:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64), [[C]](s64)
60 ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s192)
61 ; CHECK: G_STORE [[UV]](s64), [[COPY1]](p0) :: (store 8)
62 ; CHECK: RET_ReallyLR
63 %0:_(s64) = COPY $x0
64 %1:_(p0) = COPY $x1
65 %2:_(s192) = G_ZEXT %0(s64)
66 %3:_(s64), %4:_(s64), %5:_(s64) = G_UNMERGE_VALUES %2(s192)
67 G_STORE %3, %1(p0) :: (store 8)
68 RET_ReallyLR
69
70 ...
226226 # DEBUG-NEXT: .. the first uncovered type index: 2, OK
227227 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
228228 # DEBUG-NEXT: G_SEXT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
229 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
229230 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
230231 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
231232 # DEBUG-NEXT: G_SEXT_INREG (opcode {{[0-9]+}}): 1 type index, 1 imm index