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[mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions Differential Revision: http://reviews.llvm.org/D17334 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265002 91177308-0d34-0410-b5e6-96231b3b80d8 Zlatko Buljan 4 years ago
13 changed file(s) with 145 addition(s) and 29 deletion(s). Raw diff Collapse all Expand all
4343 bool hasMips32r6() const {
4444 return STI.getFeatureBits()[Mips::FeatureMips32r6];
4545 }
46 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
4647
4748 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
4849
918919 return Result;
919920 }
920921
921 if (hasMips32r6()) {
922 DEBUG(dbgs() << "Trying MicroMips32r6FPU table (32-bit opcodes):\n");
923 Result = decodeInstruction(DecoderTableMicroMips32r6FPU32, Instr, Insn,
922 if (hasMips32r6() && isFP64()) {
923 DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n");
924 Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn,
924925 Address, this, STI);
925926 if (Result != MCDisassembler::Fail) {
926927 Size = 4;
6464 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
6565 class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
6666 class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
67 class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>;
68 class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>;
69 class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>;
70 class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>;
71 class MFHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfhc1", 0b11000000>;
72 class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>;
6773 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
6874 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
6975 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
616622 HARDFLOAT, FGR_64;
617623 class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd>;
618624
625 class MFC0_MMR6_DESC_BASE
626 RegisterOperand SrcRC> {
627 dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
628 dag OutOperandList = (outs DstRC:$rt);
629 string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
630 list Pattern = [];
631 Format f = FrmFR;
632 string BaseOpcode = opstr;
633 }
634 class MFC1_MMR6_DESC_BASE
635 RegisterOperand SrcRC,
636 InstrItinClass Itin = NoItinerary,
637 SDPatternOperator OpNode = null_frag> : MipsR6Inst {
638 dag InOperandList = (ins SrcRC:$fs);
639 dag OutOperandList = (outs DstRC:$rt);
640 string AsmString = !strconcat(opstr, "\t$rt, $fs");
641 list Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))];
642 Format f = FrmFR;
643 InstrItinClass Itinerary = Itin;
644 string BaseOpcode = opstr;
645 }
646 class MFC2_MMR6_DESC_BASE
647 RegisterOperand SrcRC> {
648 dag InOperandList = (ins SrcRC:$impl);
649 dag OutOperandList = (outs DstRC:$rt);
650 string AsmString = !strconcat(opstr, "\t$rt, $impl");
651 list Pattern = [];
652 Format f = FrmFR;
653 string BaseOpcode = opstr;
654 }
655 class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd>;
656 class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
657 II_MFC1, bitconvert>, HARDFLOAT;
658 class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd>;
659 class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd>;
660 class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd,
661 II_MFHC1>, HARDFLOAT, FGR_32;
662 class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd,
663 II_MFHC1>, HARDFLOAT, FGR_64;
664 class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd>;
665
619666 /// Floating Point Instructions
620667 class FARITH_MMR6_DESC_BASE
621668 InstrItinClass Itin, bit isComm,
10821129 def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
10831130 def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
10841131 def MTHC1_D32_MMR6 : StdMMR6Rel, MTHC1_D32_MMR6_DESC, MTHC1_MMR6_ENC, ISA_MICROMIPS32R6;
1085 let DecoderNamespace = "MicroMips32r6FPU" in {
1132 let DecoderNamespace = "MicroMips32r6FP64" in {
10861133 def MTHC1_D64_MMR6 : R6MMR6Rel, MTHC1_D64_MMR6_DESC, MTHC1_MMR6_ENC,
10871134 ISA_MICROMIPS32R6;
10881135 }
10891136 def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1137 def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
1138 def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6;
1139 def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6;
1140 def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1141 def MFHC1_D32_MMR6 : StdMMR6Rel, MFHC1_D32_MMR6_DESC, MFHC1_MMR6_ENC,
1142 ISA_MICROMIPS32R6;
1143 let DecoderNamespace = "MicroMips32r6FP64" in {
1144 def MFHC1_D64_MMR6 : StdMMR6Rel, MFHC1_D64_MMR6_DESC, MFHC1_MMR6_ENC,
1145 ISA_MICROMIPS32R6;
1146 }
1147 def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6;
10901148 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
10911149 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
10921150 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
13321390 def : MipsInstAlias<"mthc0 $rt, $rs",
13331391 (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
13341392 ISA_MICROMIPS32R6;
1393 def : MipsInstAlias<"mfc0 $rt, $rs",
1394 (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1395 ISA_MICROMIPS32R6;
1396 def : MipsInstAlias<"mfhc0 $rt, $rs",
1397 (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1398 ISA_MICROMIPS32R6;
13351399
13361400 //===----------------------------------------------------------------------===//
13371401 //
3333 class DMTC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmtc0", 0b01011>;
3434 class DMTC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmtc1", 0b10110000>;
3535 class DMTC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmtc2", 0b0111110100>;
36 class DMFC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmfc0", 0b00011>;
37 class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>;
38 class DMFC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmfc2", 0b0110110100>;
3639
3740 //===----------------------------------------------------------------------===//
3841 //
105108 II_DMTC1, bitconvert>;
106109 class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd>;
107110
111 class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd>;
112 class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd,
113 II_DMFC1, bitconvert>;
114 class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd>;
115
108116 //===----------------------------------------------------------------------===//
109117 //
110118 // Instruction Definitions
143151 ISA_MICROMIPS64R6;
144152 def DMTC2_MM64R6 : StdMMR6Rel, DMTC2_MM64R6_ENC, DMTC2_MM64R6_DESC,
145153 ISA_MICROMIPS64R6;
154 def DMFC0_MM64R6 : StdMMR6Rel, DMFC0_MM64R6_ENC, DMFC0_MM64R6_DESC,
155 ISA_MICROMIPS64R6;
156 def DMFC1_MM64R6 : StdMMR6Rel, DMFC1_MM64R6_DESC, DMFC1_MM64R6_ENC,
157 ISA_MICROMIPS64R6;
158 def DMFC2_MM64R6 : StdMMR6Rel, DMFC2_MM64R6_ENC, DMFC2_MM64R6_DESC,
159 ISA_MICROMIPS64R6;
146160 }
147161
148162 //===----------------------------------------------------------------------===//
150164 //===----------------------------------------------------------------------===//
151165 def : MipsInstAlias<"dmtc0 $rt, $rd",
152166 (DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
167 def : MipsInstAlias<"dmfc0 $rt, $rd",
168 (DMFC0_MM64R6 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>,
169 ISA_MICROMIPS64R6;
113113 II_MFC1, bitconvert>, MFC1_FM_MM<0x80>;
114114 def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
115115 II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>;
116 def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
117 MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
118116
119117 def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
120118 MADDS_FM_MM<0x1>;
146144 fsqrt>, ROUND_W_FM_MM<0, 0x28>;
147145 def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
148146 MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
147 def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
148 MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
149149 }
627627 ISA_MIPS3;
628628
629629 // Two operand (implicit 0 selector) versions:
630 def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>;
631630 let AdditionalPredicates = [NotInMicroMips] in {
632631 def : MipsInstAlias<"dmtc0 $rt, $rd",
633632 (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
633 def : MipsInstAlias<"dmfc0 $rt, $rd",
634 (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>;
634635 }
635636 def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
636637 def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
366366 bitconvert>, MFC1_FM<0>;
367367 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
368368 bitconvert>, MFC1_FM<4>;
369 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
370 MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
371 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
372 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
373 let DecoderNamespace = "Mips64";
369 let AdditionalPredicates = [NotInMicroMips] in {
370 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
371 MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
372 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
373 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
374 let DecoderNamespace = "Mips64";
375 }
374376 }
375377 let AdditionalPredicates = [NotInMicroMips] in {
376378 def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
380382 let DecoderNamespace = "Mips64";
381383 }
382384 }
383 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
384 bitconvert>, MFC1_FM<1>, ISA_MIPS3;
385385 let AdditionalPredicates = [NotInMicroMips] in {
386386 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
387387 bitconvert>, MFC1_FM<5>, ISA_MIPS3;
388 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
389 bitconvert>, MFC1_FM<1>, ISA_MIPS3;
388390 }
389391
390392 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
19071907 EXT_FM<4>;
19081908
19091909 /// Move Control Registers From/To CPU Registers
1910 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
19111910 let AdditionalPredicates = [NotInMicroMips] in {
19121911 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>,
1912 ISA_MIPS32;
1913 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>,
19131914 ISA_MIPS32;
19141915 }
19151916 def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
267267 0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1
268268 0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12
269269 0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14
270 0x00 0x67 0x00 0xfc # CHECK: mfc0 $3, $7, 0
271 0x00 0x67 0x18 0xfc # CHECK: mfc0 $3, $7, 3
272 0x54 0xaa 0x20 0x3b # CHECK: mfc1 $5, $f10
273 0x01 0xe5 0x4d 0x3c # CHECK: mfc2 $15, $5
274 0x02 0x95 0x00 0xf4 # CHECK: mfhc0 $20, $21, 0
275 0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1
276 0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6
277 0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16
188188 0x5a 0x32 0x2a 0xfc # CHECK: dmtc0 $17, $18, 5
189189 0x56 0x74 0x2c 0x3b # CHECK: dmtc1 $19, $f20
190190 0x02 0xb6 0x7d 0x3c # CHECK: dmtc2 $21, $22
191 0x5a 0x51 0x00 0xfc # CHECK: dmfc0 $18, $17
192 0x59 0x21 0x08 0xfc # CHECK: dmfc0 $9, $1, 1
193 0x55 0x24 0x24 0x3b # CHECK: dmfc1 $9, $f4
194 0x01 0xd2 0x6d 0x3c # CHECK: dmfc2 $14, $18
113113 mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
114114 mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
115115 mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
116 mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
117 mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
118 mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
119 mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
258258 deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]
259259 tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c]
260260 tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c]
261 mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc]
262 mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc]
263 mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b]
264 mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c]
265 mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4]
266 mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4]
267 mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b]
268 mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c]
261 mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc]
262 mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc]
263 mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b]
264 mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c]
265 mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4]
266 mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4]
267 mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b]
268 mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c]
269 mfc0 $3, $7 # CHECK: mfc0 $3, $7, 0 # encoding: [0x00,0x67,0x00,0xfc]
270 mfc0 $3, $7, 3 # CHECK: mfc0 $3, $7, 3 # encoding: [0x00,0x67,0x18,0xfc]
271 mfc1 $5, $f10 # CHECK: mfc1 $5, $f10 # encoding: [0x54,0xaa,0x20,0x3b]
272 mfc2 $15, $5 # CHECK: mfc2 $15, $5 # encoding: [0x01,0xe5,0x4d,0x3c]
273 mfhc0 $20, $21 # CHECK: mfhc0 $20, $21, 0 # encoding: [0x02,0x95,0x00,0xf4]
274 mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4]
275 mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b]
276 mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c]
137137 swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
138138 swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
139139 swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
140 mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
141 mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
142 mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
143 mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
144 dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
145 dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
140 mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
141 mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
142 mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
143 mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
144 dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
145 dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
146 dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
147 dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
170170 dmtc0 $17, $18, 5 # CHECK: dmtc0 $17, $18, 5 # encoding: [0x5a,0x32,0x2a,0xfc]
171171 dmtc1 $19, $f20 # CHECK: dmtc1 $19, $f20 # encoding: [0x56,0x74,0x2c,0x3b]
172172 dmtc2 $21, $22 # CHECK: dmtc2 $21, $22 # encoding: [0x02,0xb6,0x7d,0x3c]
173 dmfc0 $18, $17 # CHECK: dmfc0 $18, $17, 0 # encoding: [0x5a,0x51,0x00,0xfc]
174 dmfc0 $9, $1, 1 # CHECK: dmfc0 $9, $1, 1 # encoding: [0x59,0x21,0x08,0xfc]
175 dmfc1 $9, $f4 # CHECK: dmfc1 $9, $f4 # encoding: [0x55,0x24,0x24,0x3b]
176 dmfc2 $14, $18 # CHECK: dmfc2 $14, $18 # encoding: [0x01,0xd2,0x6d,0x3c]
173177
174178 1: