llvm.org GIT mirror llvm / 4dca57f
[ARM] Add MVE vector instructions that take a scalar input. This adds the `MVE_qDest_rSrc` superclass and all its instances, plus a few other instructions that also take a scalar input register or two. I've also belatedly added custom diagnostic messages to the operand classes for odd- and even-numbered GPRs, which required matching changes in two of the existing MVE assembly test files. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62678 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364040 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 1 year, 1 month ago
10 changed file(s) with 1580 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
458458 rot_imm_XFORM> {
459459 let PrintMethod = "printRotImmOperand";
460460 let ParserMatchClass = RotImmAsmOperand;
461 }
462
463 // Power-of-two operand for MVE VIDUP and friends, which encode
464 // {1,2,4,8} as its log to base 2, i.e. as {0,1,2,3} respectively
465 def MVE_VIDUP_imm_asmoperand : AsmOperandClass {
466 let Name = "VIDUP_imm";
467 let PredicateMethod = "isPowerTwoInRange<1,8>";
468 let RenderMethod = "addPowerTwoOperands";
469 let DiagnosticString = "vector increment immediate must be 1, 2, 4 or 8";
470 }
471 def MVE_VIDUP_imm : Operand {
472 let EncoderMethod = "getPowerTwoOpValue";
473 let DecoderMethod = "DecodePowerTwoOperand<0,3>";
474 let ParserMatchClass = MVE_VIDUP_imm_asmoperand;
461475 }
462476
463477 // Vector indexing
14831483 : MVE_VMOV_lane_base
14841484 "vmov", suffix, dir.ops, dir.cstr, []> {
14851485 bits<4> Qd;
1486 bits<5> Rt;
1486 bits<4> Rt;
14871487
14881488 let Inst{31-24} = 0b11101110;
14891489 let Inst{23} = U;
26812681
26822682 // end of mve_qDest_qSrc
26832683
2684 // start of mve_qDest_rSrc
2685
2686 class MVE_qr_base
2687 string suffix, string ops, vpred_ops vpred, string cstr,
2688 list pattern=[]>
2689 : MVE_p {
2690 bits<4> Qd;
2691 bits<4> Qn;
2692 bits<4> Rm;
2693
2694 let Inst{25-23} = 0b100;
2695 let Inst{22} = Qd{3};
2696 let Inst{19-17} = Qn{2-0};
2697 let Inst{15-13} = Qd{2-0};
2698 let Inst{11-9} = 0b111;
2699 let Inst{7} = Qn{3};
2700 let Inst{6} = 0b1;
2701 let Inst{4} = 0b0;
2702 let Inst{3-0} = Rm{3-0};
2703 }
2704
2705 class MVE_qDest_rSrc pattern=[]>
2706 : MVE_qr_base<(outs MQPR:$Qd), (ins MQPR:$Qn, rGPR:$Rm),
2707 NoItinerary, iname, suffix, "$Qd, $Qn, $Rm", vpred_r, "",
2708 pattern>;
2709
2710 class MVE_qDestSrc_rSrc pattern=[]>
2711 : MVE_qr_base<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qn, rGPR:$Rm),
2712 NoItinerary, iname, suffix, "$Qd, $Qn, $Rm", vpred_n, "$Qd = $Qd_src",
2713 pattern>;
2714
2715 class MVE_qDest_single_rSrc pattern=[]>
2716 : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qd_src, rGPR:$Rm), NoItinerary, iname,
2717 suffix, "$Qd, $Rm", vpred_n, "$Qd = $Qd_src", pattern> {
2718 bits<4> Qd;
2719 bits<4> Rm;
2720
2721 let Inst{22} = Qd{3};
2722 let Inst{15-13} = Qd{2-0};
2723 let Inst{3-0} = Rm{3-0};
2724 }
2725
2726 class MVE_VADDSUB_qr size,
2727 bit bit_5, bit bit_12, bit bit_16,
2728 bit bit_28, list pattern=[]>
2729 : MVE_qDest_rSrc {
2730
2731 let Inst{28} = bit_28;
2732 let Inst{21-20} = size;
2733 let Inst{16} = bit_16;
2734 let Inst{12} = bit_12;
2735 let Inst{8} = 0b1;
2736 let Inst{5} = bit_5;
2737 }
2738
2739 multiclass MVE_VADDSUB_qr_sizes
2740 bit bit_5, bit bit_12, bit bit_16,
2741 bit bit_28, list pattern=[]> {
2742 def "8" : MVE_VADDSUB_qr
2743 bit_5, bit_12, bit_16, bit_28>;
2744 def "16" : MVE_VADDSUB_qr
2745 bit_5, bit_12, bit_16, bit_28>;
2746 def "32" : MVE_VADDSUB_qr
2747 bit_5, bit_12, bit_16, bit_28>;
2748 }
2749
2750 defm MVE_VADD_qr_i : MVE_VADDSUB_qr_sizes<"vadd", "i", 0b0, 0b0, 0b1, 0b0>;
2751 defm MVE_VQADD_qr_s : MVE_VADDSUB_qr_sizes<"vqadd", "s", 0b1, 0b0, 0b0, 0b0>;
2752 defm MVE_VQADD_qr_u : MVE_VADDSUB_qr_sizes<"vqadd", "u", 0b1, 0b0, 0b0, 0b1>;
2753
2754 defm MVE_VSUB_qr_i : MVE_VADDSUB_qr_sizes<"vsub", "i", 0b0, 0b1, 0b1, 0b0>;
2755 defm MVE_VQSUB_qr_s : MVE_VADDSUB_qr_sizes<"vqsub", "s", 0b1, 0b1, 0b0, 0b0>;
2756 defm MVE_VQSUB_qr_u : MVE_VADDSUB_qr_sizes<"vqsub", "u", 0b1, 0b1, 0b0, 0b1>;
2757
2758 class MVE_VQDMULL_qr
2759 bit T, list pattern=[]>
2760 : MVE_qDest_rSrc {
2761
2762 let Inst{28} = size;
2763 let Inst{21-20} = 0b11;
2764 let Inst{16} = 0b0;
2765 let Inst{12} = T;
2766 let Inst{8} = 0b1;
2767 let Inst{5} = 0b1;
2768 }
2769
2770 multiclass MVE_VQDMULL_qr_halves {
2771 def bh : MVE_VQDMULL_qr<"vqdmullb", suffix, size, 0b0>;
2772 def th : MVE_VQDMULL_qr<"vqdmullt", suffix, size, 0b1>;
2773 }
2774
2775 defm MVE_VQDMULL_qr_s16 : MVE_VQDMULL_qr_halves<"s16", 0b0>;
2776 defm MVE_VQDMULL_qr_s32 : MVE_VQDMULL_qr_halves<"s32", 0b1>;
2777
2778 class MVE_VxADDSUB_qr
2779 bit bit_28, bits<2> bits_21_20, bit subtract,
2780 list pattern=[]>
2781 : MVE_qDest_rSrc {
2782
2783 let Inst{28} = bit_28;
2784 let Inst{21-20} = bits_21_20;
2785 let Inst{16} = 0b0;
2786 let Inst{12} = subtract;
2787 let Inst{8} = 0b1;
2788 let Inst{5} = 0b0;
2789 }
2790
2791 def MVE_VHADD_qr_s8 : MVE_VxADDSUB_qr<"vhadd", "s8", 0b0, 0b00, 0b0>;
2792 def MVE_VHADD_qr_s16 : MVE_VxADDSUB_qr<"vhadd", "s16", 0b0, 0b01, 0b0>;
2793 def MVE_VHADD_qr_s32 : MVE_VxADDSUB_qr<"vhadd", "s32", 0b0, 0b10, 0b0>;
2794 def MVE_VHADD_qr_u8 : MVE_VxADDSUB_qr<"vhadd", "u8", 0b1, 0b00, 0b0>;
2795 def MVE_VHADD_qr_u16 : MVE_VxADDSUB_qr<"vhadd", "u16", 0b1, 0b01, 0b0>;
2796 def MVE_VHADD_qr_u32 : MVE_VxADDSUB_qr<"vhadd", "u32", 0b1, 0b10, 0b0>;
2797
2798 def MVE_VHSUB_qr_s8 : MVE_VxADDSUB_qr<"vhsub", "s8", 0b0, 0b00, 0b1>;
2799 def MVE_VHSUB_qr_s16 : MVE_VxADDSUB_qr<"vhsub", "s16", 0b0, 0b01, 0b1>;
2800 def MVE_VHSUB_qr_s32 : MVE_VxADDSUB_qr<"vhsub", "s32", 0b0, 0b10, 0b1>;
2801 def MVE_VHSUB_qr_u8 : MVE_VxADDSUB_qr<"vhsub", "u8", 0b1, 0b00, 0b1>;
2802 def MVE_VHSUB_qr_u16 : MVE_VxADDSUB_qr<"vhsub", "u16", 0b1, 0b01, 0b1>;
2803 def MVE_VHSUB_qr_u32 : MVE_VxADDSUB_qr<"vhsub", "u32", 0b1, 0b10, 0b1>;
2804
2805 let Predicates = [HasMVEFloat] in {
2806 def MVE_VADD_qr_f32 : MVE_VxADDSUB_qr<"vadd", "f32", 0b0, 0b11, 0b0>;
2807 def MVE_VADD_qr_f16 : MVE_VxADDSUB_qr<"vadd", "f16", 0b1, 0b11, 0b0>;
2808
2809 def MVE_VSUB_qr_f32 : MVE_VxADDSUB_qr<"vsub", "f32", 0b0, 0b11, 0b1>;
2810 def MVE_VSUB_qr_f16 : MVE_VxADDSUB_qr<"vsub", "f16", 0b1, 0b11, 0b1>;
2811 }
2812
2813 class MVE_VxSHL_qr size,
2814 bit bit_7, bit bit_17, list pattern=[]>
2815 : MVE_qDest_single_rSrc {
2816
2817 let Inst{28} = U;
2818 let Inst{25-23} = 0b100;
2819 let Inst{21-20} = 0b11;
2820 let Inst{19-18} = size;
2821 let Inst{17} = bit_17;
2822 let Inst{16} = 0b1;
2823 let Inst{12-8} = 0b11110;
2824 let Inst{7} = bit_7;
2825 let Inst{6-4} = 0b110;
2826 }
2827
2828 multiclass MVE_VxSHL_qr_types {
2829 def s8 : MVE_VxSHL_qr;
2830 def s16 : MVE_VxSHL_qr;
2831 def s32 : MVE_VxSHL_qr;
2832 def u8 : MVE_VxSHL_qr;
2833 def u16 : MVE_VxSHL_qr;
2834 def u32 : MVE_VxSHL_qr;
2835 }
2836
2837 defm MVE_VSHL_qr : MVE_VxSHL_qr_types<"vshl", 0b0, 0b0>;
2838 defm MVE_VRSHL_qr : MVE_VxSHL_qr_types<"vrshl", 0b0, 0b1>;
2839 defm MVE_VQSHL_qr : MVE_VxSHL_qr_types<"vqshl", 0b1, 0b0>;
2840 defm MVE_VQRSHL_qr : MVE_VxSHL_qr_types<"vqrshl", 0b1, 0b1>;
2841
2842 class MVE_VBRSR size, list pattern=[]>
2843 : MVE_qDest_rSrc {
2844
2845 let Inst{28} = 0b1;
2846 let Inst{21-20} = size;
2847 let Inst{16} = 0b1;
2848 let Inst{12} = 0b1;
2849 let Inst{8} = 0b0;
2850 let Inst{5} = 0b1;
2851 }
2852
2853 def MVE_VBRSR8 : MVE_VBRSR<"vbrsr", "8", 0b00>;
2854 def MVE_VBRSR16 : MVE_VBRSR<"vbrsr", "16", 0b01>;
2855 def MVE_VBRSR32 : MVE_VBRSR<"vbrsr", "32", 0b10>;
2856
2857 class MVE_VMUL_qr_int
2858 bits<2> size, list pattern=[]>
2859 : MVE_qDest_rSrc {
2860
2861 let Inst{28} = 0b0;
2862 let Inst{21-20} = size;
2863 let Inst{16} = 0b1;
2864 let Inst{12} = 0b1;
2865 let Inst{8} = 0b0;
2866 let Inst{5} = 0b1;
2867 }
2868
2869 def MVE_VMUL_qr_i8 : MVE_VMUL_qr_int<"vmul", "i8", 0b00>;
2870 def MVE_VMUL_qr_i16 : MVE_VMUL_qr_int<"vmul", "i16", 0b01>;
2871 def MVE_VMUL_qr_i32 : MVE_VMUL_qr_int<"vmul", "i32", 0b10>;
2872
2873 class MVE_VxxMUL_qr
2874 bit bit_28, bits<2> bits_21_20, list pattern=[]>
2875 : MVE_qDest_rSrc {
2876
2877 let Inst{28} = bit_28;
2878 let Inst{21-20} = bits_21_20;
2879 let Inst{16} = 0b1;
2880 let Inst{12} = 0b0;
2881 let Inst{8} = 0b0;
2882 let Inst{5} = 0b1;
2883 }
2884
2885 def MVE_VQDMULH_qr_s8 : MVE_VxxMUL_qr<"vqdmulh", "s8", 0b0, 0b00>;
2886 def MVE_VQDMULH_qr_s16 : MVE_VxxMUL_qr<"vqdmulh", "s16", 0b0, 0b01>;
2887 def MVE_VQDMULH_qr_s32 : MVE_VxxMUL_qr<"vqdmulh", "s32", 0b0, 0b10>;
2888
2889 def MVE_VQRDMULH_qr_s8 : MVE_VxxMUL_qr<"vqrdmulh", "s8", 0b1, 0b00>;
2890 def MVE_VQRDMULH_qr_s16 : MVE_VxxMUL_qr<"vqrdmulh", "s16", 0b1, 0b01>;
2891 def MVE_VQRDMULH_qr_s32 : MVE_VxxMUL_qr<"vqrdmulh", "s32", 0b1, 0b10>;
2892
2893 let Predicates = [HasMVEFloat] in {
2894 def MVE_VMUL_qr_f16 : MVE_VxxMUL_qr<"vmul", "f16", 0b1, 0b11>;
2895 def MVE_VMUL_qr_f32 : MVE_VxxMUL_qr<"vmul", "f32", 0b0, 0b11>;
2896 }
2897
2898 class MVE_VFMAMLA_qr
2899 bit bit_28, bits<2> bits_21_20, bit S,
2900 list pattern=[]>
2901 : MVE_qDestSrc_rSrc {
2902
2903 let Inst{28} = bit_28;
2904 let Inst{21-20} = bits_21_20;
2905 let Inst{16} = 0b1;
2906 let Inst{12} = S;
2907 let Inst{8} = 0b0;
2908 let Inst{5} = 0b0;
2909 }
2910
2911 def MVE_VMLA_qr_s8 : MVE_VFMAMLA_qr<"vmla", "s8", 0b0, 0b00, 0b0>;
2912 def MVE_VMLA_qr_s16 : MVE_VFMAMLA_qr<"vmla", "s16", 0b0, 0b01, 0b0>;
2913 def MVE_VMLA_qr_s32 : MVE_VFMAMLA_qr<"vmla", "s32", 0b0, 0b10, 0b0>;
2914 def MVE_VMLA_qr_u8 : MVE_VFMAMLA_qr<"vmla", "u8", 0b1, 0b00, 0b0>;
2915 def MVE_VMLA_qr_u16 : MVE_VFMAMLA_qr<"vmla", "u16", 0b1, 0b01, 0b0>;
2916 def MVE_VMLA_qr_u32 : MVE_VFMAMLA_qr<"vmla", "u32", 0b1, 0b10, 0b0>;
2917
2918 def MVE_VMLAS_qr_s8 : MVE_VFMAMLA_qr<"vmlas", "s8", 0b0, 0b00, 0b1>;
2919 def MVE_VMLAS_qr_s16 : MVE_VFMAMLA_qr<"vmlas", "s16", 0b0, 0b01, 0b1>;
2920 def MVE_VMLAS_qr_s32 : MVE_VFMAMLA_qr<"vmlas", "s32", 0b0, 0b10, 0b1>;
2921 def MVE_VMLAS_qr_u8 : MVE_VFMAMLA_qr<"vmlas", "u8", 0b1, 0b00, 0b1>;
2922 def MVE_VMLAS_qr_u16 : MVE_VFMAMLA_qr<"vmlas", "u16", 0b1, 0b01, 0b1>;
2923 def MVE_VMLAS_qr_u32 : MVE_VFMAMLA_qr<"vmlas", "u32", 0b1, 0b10, 0b1>;
2924
2925 let Predicates = [HasMVEFloat] in {
2926 def MVE_VFMA_qr_f16 : MVE_VFMAMLA_qr<"vfma", "f16", 0b1, 0b11, 0b0>;
2927 def MVE_VFMA_qr_f32 : MVE_VFMAMLA_qr<"vfma", "f32", 0b0, 0b11, 0b0>;
2928 def MVE_VFMA_qr_Sf16 : MVE_VFMAMLA_qr<"vfmas", "f16", 0b1, 0b11, 0b1>;
2929 def MVE_VFMA_qr_Sf32 : MVE_VFMAMLA_qr<"vfmas", "f32", 0b0, 0b11, 0b1>;
2930 }
2931
2932 class MVE_VQDMLAH_qr size,
2933 bit bit_5, bit bit_12, list pattern=[]>
2934 : MVE_qDestSrc_rSrc {
2935
2936 let Inst{28} = U;
2937 let Inst{21-20} = size;
2938 let Inst{16} = 0b0;
2939 let Inst{12} = bit_12;
2940 let Inst{8} = 0b0;
2941 let Inst{5} = bit_5;
2942 }
2943
2944 multiclass MVE_VQDMLAH_qr_types {
2945 def s8 : MVE_VQDMLAH_qr;
2946 def s16 : MVE_VQDMLAH_qr;
2947 def s32 : MVE_VQDMLAH_qr;
2948 def u8 : MVE_VQDMLAH_qr;
2949 def u16 : MVE_VQDMLAH_qr;
2950 def u32 : MVE_VQDMLAH_qr;
2951 }
2952
2953 defm MVE_VQDMLAH_qr : MVE_VQDMLAH_qr_types<"vqdmlah", 0b1, 0b0>;
2954 defm MVE_VQRDMLAH_qr : MVE_VQDMLAH_qr_types<"vqrdmlah", 0b0, 0b0>;
2955 defm MVE_VQDMLASH_qr : MVE_VQDMLAH_qr_types<"vqdmlash", 0b1, 0b1>;
2956 defm MVE_VQRDMLASH_qr : MVE_VQDMLAH_qr_types<"vqrdmlash", 0b0, 0b1>;
2957
2958 class MVE_VxDUP size, bit bit_12,
2959 list pattern=[]>
2960 : MVE_p<(outs MQPR:$Qd, tGPREven:$Rn),
2961 (ins tGPREven:$Rn_src, MVE_VIDUP_imm:$imm), NoItinerary,
2962 iname, suffix, "$Qd, $Rn, $imm", vpred_r, "$Rn = $Rn_src",
2963 pattern> {
2964 bits<4> Qd;
2965 bits<4> Rn;
2966 bits<2> imm;
2967
2968 let Inst{28} = 0b0;
2969 let Inst{25-23} = 0b100;
2970 let Inst{22} = Qd{3};
2971 let Inst{21-20} = size;
2972 let Inst{19-17} = Rn{3-1};
2973 let Inst{16} = 0b1;
2974 let Inst{15-13} = Qd{2-0};
2975 let Inst{12} = bit_12;
2976 let Inst{11-8} = 0b1111;
2977 let Inst{7} = imm{1};
2978 let Inst{6-1} = 0b110111;
2979 let Inst{0} = imm{0};
2980 }
2981
2982 def MVE_VIDUPu8 : MVE_VxDUP<"vidup", "u8", 0b00, 0b0>;
2983 def MVE_VIDUPu16 : MVE_VxDUP<"vidup", "u16", 0b01, 0b0>;
2984 def MVE_VIDUPu32 : MVE_VxDUP<"vidup", "u32", 0b10, 0b0>;
2985
2986 def MVE_VDDUPu8 : MVE_VxDUP<"vddup", "u8", 0b00, 0b1>;
2987 def MVE_VDDUPu16 : MVE_VxDUP<"vddup", "u16", 0b01, 0b1>;
2988 def MVE_VDDUPu32 : MVE_VxDUP<"vddup", "u32", 0b10, 0b1>;
2989
2990 class MVE_VxWDUP size, bit bit_12,
2991 list pattern=[]>
2992 : MVE_p<(outs MQPR:$Qd, tGPREven:$Rn),
2993 (ins tGPREven:$Rn_src, tGPROdd:$Rm, MVE_VIDUP_imm:$imm), NoItinerary,
2994 iname, suffix, "$Qd, $Rn, $Rm, $imm", vpred_r, "$Rn = $Rn_src",
2995 pattern> {
2996 bits<4> Qd;
2997 bits<4> Rm;
2998 bits<4> Rn;
2999 bits<2> imm;
3000
3001 let Inst{28} = 0b0;
3002 let Inst{25-23} = 0b100;
3003 let Inst{22} = Qd{3};
3004 let Inst{21-20} = size;
3005 let Inst{19-17} = Rn{3-1};
3006 let Inst{16} = 0b1;
3007 let Inst{15-13} = Qd{2-0};
3008 let Inst{12} = bit_12;
3009 let Inst{11-8} = 0b1111;
3010 let Inst{7} = imm{1};
3011 let Inst{6-4} = 0b110;
3012 let Inst{3-1} = Rm{3-1};
3013 let Inst{0} = imm{0};
3014 }
3015
3016 def MVE_VIWDUPu8 : MVE_VxWDUP<"viwdup", "u8", 0b00, 0b0>;
3017 def MVE_VIWDUPu16 : MVE_VxWDUP<"viwdup", "u16", 0b01, 0b0>;
3018 def MVE_VIWDUPu32 : MVE_VxWDUP<"viwdup", "u32", 0b10, 0b0>;
3019
3020 def MVE_VDWDUPu8 : MVE_VxWDUP<"vdwdup", "u8", 0b00, 0b1>;
3021 def MVE_VDWDUPu16 : MVE_VxWDUP<"vdwdup", "u16", 0b01, 0b1>;
3022 def MVE_VDWDUPu32 : MVE_VxWDUP<"vdwdup", "u32", 0b10, 0b1>;
3023
3024 class MVE_VCTP size, list pattern=[]>
3025 : MVE_p<(outs VCCR:$P0), (ins rGPR:$Rn), NoItinerary, "vctp", suffix,
3026 "$Rn", vpred_n, "", pattern> {
3027 bits<4> Rn;
3028
3029 let Inst{28-27} = 0b10;
3030 let Inst{26-22} = 0b00000;
3031 let Inst{21-20} = size;
3032 let Inst{19-16} = Rn{3-0};
3033 let Inst{15-11} = 0b11101;
3034 let Inst{10-0} = 0b00000000001;
3035 let Unpredictable{10-0} = 0b11111111111;
3036
3037 let Constraints = "";
3038 let DecoderMethod = "DecodeMveVCTP";
3039 }
3040
3041 def MVE_VCTP8 : MVE_VCTP<"8", 0b00>;
3042 def MVE_VCTP16 : MVE_VCTP<"16", 0b01>;
3043 def MVE_VCTP32 : MVE_VCTP<"32", 0b10>;
3044 def MVE_VCTP64 : MVE_VCTP<"64", 0b11>;
3045
3046 // end of mve_qDest_rSrc
3047
26843048 class MVE_VPT size, dag iops, string asm, list pattern=[]>
26853049 : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
26863050 bits<3> fc;
335335 let AltOrderSelect = [{
336336 return MF.getSubtarget().isThumb1Only();
337337 }];
338 let DiagnosticString =
339 "operand must be an odd-numbered register in range [r1,r11]";
338340 }
339341
340342 def tGPREven : RegisterClass<"ARM", [i32], 32, (add R0, R2, R4, R6, R8, R10, R12, LR)> {
342344 let AltOrderSelect = [{
343345 return MF.getSubtarget().isThumb1Only();
344346 }];
347 let DiagnosticString = "operand must be an even-numbered register";
345348 }
346349
347350 // Condition code registers.
12751275 RegShiftedImm.SrcReg);
12761276 }
12771277 bool isRotImm() const { return Kind == k_RotateImmediate; }
1278
1279 template
1280 bool isPowerTwoInRange() const {
1281 if (!isImm()) return false;
1282 const MCConstantExpr *CE = dyn_cast(getImm());
1283 if (!CE) return false;
1284 int64_t Value = CE->getValue();
1285 return Value > 0 && countPopulation((uint64_t)Value) == 1 &&
1286 Value >= Min && Value <= Max;
1287 }
12781288 bool isModImm() const { return Kind == k_ModifiedImmediate; }
12791289
12801290 bool isModImmNot() const {
59615971 !(hasMVE() &&
59625972 (Mnemonic == "vmine" ||
59635973 Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
5974 Mnemonic == "vrshle" || Mnemonic == "vrshlt" ||
59645975 Mnemonic == "vmvne" || Mnemonic == "vorne" ||
59655976 Mnemonic == "vnege" || Mnemonic == "vnegt" ||
59665977 Mnemonic == "vmule" || Mnemonic == "vmult" ||
59865997 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
59875998 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
59885999 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5989 Mnemonic == "bxns" || Mnemonic == "blxns" ||
6000 Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" ||
6001 Mnemonic == "vmlas" ||
59906002 (Mnemonic == "movs" && isThumb()))) {
59916003 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
59926004 CarrySetting = true;
63436355 OperandVector &Operands) {
63446356 if (!hasMVE() || Operands.size() < 3)
63456357 return true;
6358
6359 if (Mnemonic.startswith("vctp"))
6360 return false;
63466361
63476362 if (Mnemonic.startswith("vmov") &&
63486363 !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") ||
504504 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
505505 uint64_t Address,
506506 const void *Decoder);
507 template
508 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
509 uint64_t Address,
510 const void *Decoder);
507511 template
508512 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
509513 uint64_t Address,
514518 uint64_t Address, const void *Decoder);
515519 template
516520 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn,
521 uint64_t Address, const void *Decoder);
522 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn,
517523 uint64_t Address, const void *Decoder);
518524 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
519525 uint64_t Address,
61226128 return S;
61236129 }
61246130
6131 template
6132 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
6133 uint64_t Address,
6134 const void *Decoder) {
6135 DecodeStatus S = MCDisassembler::Success;
6136
6137 if (Val < MinLog || Val > MaxLog)
6138 return MCDisassembler::Fail;
6139
6140 Inst.addOperand(MCOperand::createImm(1 << Val));
6141 return S;
6142 }
6143
61256144 template
61266145 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
61276146 uint64_t Address,
62546273
62556274 return S;
62566275 }
6276
6277 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
6278 const void *Decoder) {
6279 DecodeStatus S = MCDisassembler::Success;
6280 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6281 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6282 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
6283 return MCDisassembler::Fail;
6284 return S;
6285 }
423423 unsigned EncodedValue,
424424 const MCSubtargetInfo &STI) const;
425425
426 uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
427 SmallVectorImpl &Fixups,
428 const MCSubtargetInfo &STI) const;
429
426430 void EmitByte(unsigned char C, raw_ostream &OS) const {
427431 OS << (char)C;
428432 }
19121916 }
19131917 }
19141918
1919 uint32_t ARMMCCodeEmitter::
1920 getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
1921 SmallVectorImpl &Fixups,
1922 const MCSubtargetInfo &STI) const {
1923 const MCOperand &MO = MI.getOperand(OpIdx);
1924 assert(MO.isImm() && "Unexpected operand type!");
1925 return countTrailingZeros((uint64_t)MO.getImm());
1926 }
1927
19151928 #include "ARMGenMCCodeEmitter.inc"
19161929
19171930 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
0 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \
1 # RUN: | FileCheck --check-prefix=CHECK-NOFP %s
2 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
3 # RUN: | FileCheck --check-prefix=CHECK %s
4 # RUN: FileCheck --check-prefix=ERROR < %t %s
5
6 # CHECK: vsub.i8 q0, q3, r3 @ encoding: [0x07,0xee,0x43,0x1f]
7 # CHECK-NOFP: vsub.i8 q0, q3, r3 @ encoding: [0x07,0xee,0x43,0x1f]
8 vsub.i8 q0, q3, r3
9
10 # CHECK: vsub.i16 q0, q7, lr @ encoding: [0x1f,0xee,0x4e,0x1f]
11 # CHECK-NOFP: vsub.i16 q0, q7, lr @ encoding: [0x1f,0xee,0x4e,0x1f]
12 vsub.i16 q0, q7, lr
13
14 # CHECK: vsub.i32 q1, q5, r10 @ encoding: [0x2b,0xee,0x4a,0x3f]
15 # CHECK-NOFP: vsub.i32 q1, q5, r10 @ encoding: [0x2b,0xee,0x4a,0x3f]
16 vsub.i32 q1, q5, r10
17
18 # CHECK: vadd.i8 q1, q4, r7 @ encoding: [0x09,0xee,0x47,0x2f]
19 # CHECK-NOFP: vadd.i8 q1, q4, r7 @ encoding: [0x09,0xee,0x47,0x2f]
20 vadd.i8 q1, q4, r7
21
22 # CHECK: vadd.i16 q0, q6, r11 @ encoding: [0x1d,0xee,0x4b,0x0f]
23 # CHECK-NOFP: vadd.i16 q0, q6, r11 @ encoding: [0x1d,0xee,0x4b,0x0f]
24 vadd.i16 q0, q6, r11
25
26 # CHECK: vadd.i32 q0, q1, r6 @ encoding: [0x23,0xee,0x46,0x0f]
27 # CHECK-NOFP: vadd.i32 q0, q1, r6 @ encoding: [0x23,0xee,0x46,0x0f]
28 vadd.i32 q0, q1, r6
29
30 # CHECK: vqsub.s8 q2, q2, r8 @ encoding: [0x04,0xee,0x68,0x5f]
31 # CHECK-NOFP: vqsub.s8 q2, q2, r8 @ encoding: [0x04,0xee,0x68,0x5f]
32 vqsub.s8 q2, q2, r8
33
34 # CHECK: vqsub.s16 q1, q4, r0 @ encoding: [0x18,0xee,0x60,0x3f]
35 # CHECK-NOFP: vqsub.s16 q1, q4, r0 @ encoding: [0x18,0xee,0x60,0x3f]
36 vqsub.s16 q1, q4, r0
37
38 # CHECK: vqsub.s32 q0, q2, r0 @ encoding: [0x24,0xee,0x60,0x1f]
39 # CHECK-NOFP: vqsub.s32 q0, q2, r0 @ encoding: [0x24,0xee,0x60,0x1f]
40 vqsub.s32 q0, q2, r0
41
42 # CHECK: vqsub.u8 q0, q1, r2 @ encoding: [0x02,0xfe,0x62,0x1f]
43 # CHECK-NOFP: vqsub.u8 q0, q1, r2 @ encoding: [0x02,0xfe,0x62,0x1f]
44 vqsub.u8 q0, q1, r2
45
46 # CHECK: vqsub.u16 q0, q2, r6 @ encoding: [0x14,0xfe,0x66,0x1f]
47 # CHECK-NOFP: vqsub.u16 q0, q2, r6 @ encoding: [0x14,0xfe,0x66,0x1f]
48 vqsub.u16 q0, q2, r6
49
50 # CHECK: vqsub.u32 q0, q2, r2 @ encoding: [0x24,0xfe,0x62,0x1f]
51 # CHECK-NOFP: vqsub.u32 q0, q2, r2 @ encoding: [0x24,0xfe,0x62,0x1f]
52 vqsub.u32 q0, q2, r2
53
54 # CHECK: vqadd.s8 q0, q6, r1 @ encoding: [0x0c,0xee,0x61,0x0f]
55 # CHECK-NOFP: vqadd.s8 q0, q6, r1 @ encoding: [0x0c,0xee,0x61,0x0f]
56 vqadd.s8 q0, q6, r1
57
58 # CHECK: vqadd.s16 q3, q4, r2 @ encoding: [0x18,0xee,0x62,0x6f]
59 # CHECK-NOFP: vqadd.s16 q3, q4, r2 @ encoding: [0x18,0xee,0x62,0x6f]
60 vqadd.s16 q3, q4, r2
61
62 # CHECK: vqadd.s32 q0, q5, r11 @ encoding: [0x2a,0xee,0x6b,0x0f]
63 # CHECK-NOFP: vqadd.s32 q0, q5, r11 @ encoding: [0x2a,0xee,0x6b,0x0f]
64 vqadd.s32 q0, q5, r11
65
66 # CHECK: vqadd.u8 q0, q1, r8 @ encoding: [0x02,0xfe,0x68,0x0f]
67 # CHECK-NOFP: vqadd.u8 q0, q1, r8 @ encoding: [0x02,0xfe,0x68,0x0f]
68 vqadd.u8 q0, q1, r8
69
70 # CHECK: vqadd.u16 q0, q5, r9 @ encoding: [0x1a,0xfe,0x69,0x0f]
71 # CHECK-NOFP: vqadd.u16 q0, q5, r9 @ encoding: [0x1a,0xfe,0x69,0x0f]
72 vqadd.u16 q0, q5, r9
73
74 # CHECK: vqadd.u32 q0, q0, r7 @ encoding: [0x20,0xfe,0x67,0x0f]
75 # CHECK-NOFP: vqadd.u32 q0, q0, r7 @ encoding: [0x20,0xfe,0x67,0x0f]
76 vqadd.u32 q0, q0, r7
77
78 # CHECK: vqdmullb.s16 q0, q1, r6 @ encoding: [0x32,0xee,0x66,0x0f]
79 # CHECK-NOFP: vqdmullb.s16 q0, q1, r6 @ encoding: [0x32,0xee,0x66,0x0f]
80 vqdmullb.s16 q0, q1, r6
81
82 # CHECK: vqdmullb.s32 q0, q3, q7 @ encoding: [0x36,0xfe,0x0f,0x0f]
83 # CHECK-NOFP: vqdmullb.s32 q0, q3, q7 @ encoding: [0x36,0xfe,0x0f,0x0f]
84 vqdmullb.s32 q0, q3, q7
85
86 # CHECK: vqdmullt.s16 q0, q1, r0 @ encoding: [0x32,0xee,0x60,0x1f]
87 # CHECK-NOFP: vqdmullt.s16 q0, q1, r0 @ encoding: [0x32,0xee,0x60,0x1f]
88 vqdmullt.s16 q0, q1, r0
89
90 # CHECK: vqdmullt.s32 q0, q4, r5 @ encoding: [0x38,0xfe,0x65,0x1f]
91 # CHECK-NOFP: vqdmullt.s32 q0, q4, r5 @ encoding: [0x38,0xfe,0x65,0x1f]
92 vqdmullt.s32 q0, q4, r5
93
94 # CHECK: vsub.f16 q0, q3, r7 @ encoding: [0x36,0xfe,0x47,0x1f]
95 # CHECK-NOFP-NOT: vsub.f16 q0, q3, r7 @ encoding: [0x36,0xfe,0x47,0x1f]
96 vsub.f16 q0, q3, r7
97
98 # CHECK: vsub.f32 q1, q1, r10 @ encoding: [0x32,0xee,0x4a,0x3f]
99 # CHECK-NOFP-NOT: vsub.f32 q1, q1, r10 @ encoding: [0x32,0xee,0x4a,0x3f]
100 vsub.f32 q1, q1, r10
101
102 # CHECK: vadd.f16 q0, q1, lr @ encoding: [0x32,0xfe,0x4e,0x0f]
103 # CHECK-NOFP-NOT: vadd.f16 q0, q1, lr @ encoding: [0x32,0xfe,0x4e,0x0f]
104 vadd.f16 q0, q1, lr
105
106 # CHECK: vadd.f32 q1, q4, r4 @ encoding: [0x38,0xee,0x44,0x2f]
107 # CHECK-NOFP-NOT: vadd.f32 q1, q4, r4 @ encoding: [0x38,0xee,0x44,0x2f]
108 vadd.f32 q1, q4, r4
109
110 # CHECK: vhsub.s8 q0, q3, lr @ encoding: [0x06,0xee,0x4e,0x1f]
111 # CHECK-NOFP: vhsub.s8 q0, q3, lr @ encoding: [0x06,0xee,0x4e,0x1f]
112 vhsub.s8 q0, q3, lr
113
114 # CHECK: vhsub.s16 q0, q0, r6 @ encoding: [0x10,0xee,0x46,0x1f]
115 # CHECK-NOFP: vhsub.s16 q0, q0, r6 @ encoding: [0x10,0xee,0x46,0x1f]
116 vhsub.s16 q0, q0, r6
117
118 # CHECK: vhsub.s32 q1, q2, r7 @ encoding: [0x24,0xee,0x47,0x3f]
119 # CHECK-NOFP: vhsub.s32 q1, q2, r7 @ encoding: [0x24,0xee,0x47,0x3f]
120 vhsub.s32 q1, q2, r7
121
122 # CHECK: vhsub.u8 q1, q6, r5 @ encoding: [0x0c,0xfe,0x45,0x3f]
123 # CHECK-NOFP: vhsub.u8 q1, q6, r5 @ encoding: [0x0c,0xfe,0x45,0x3f]
124 vhsub.u8 q1, q6, r5
125
126 # CHECK: vhsub.u16 q0, q4, r10 @ encoding: [0x18,0xfe,0x4a,0x1f]
127 # CHECK-NOFP: vhsub.u16 q0, q4, r10 @ encoding: [0x18,0xfe,0x4a,0x1f]
128 vhsub.u16 q0, q4, r10
129
130 # CHECK: vhsub.u32 q0, q4, r12 @ encoding: [0x28,0xfe,0x4c,0x1f]
131 # CHECK-NOFP: vhsub.u32 q0, q4, r12 @ encoding: [0x28,0xfe,0x4c,0x1f]
132 vhsub.u32 q0, q4, r12
133
134 # CHECK: vhadd.s8 q0, q2, r1 @ encoding: [0x04,0xee,0x41,0x0f]
135 # CHECK-NOFP: vhadd.s8 q0, q2, r1 @ encoding: [0x04,0xee,0x41,0x0f]
136 vhadd.s8 q0, q2, r1
137
138 # CHECK: vhadd.s16 q0, q2, r1 @ encoding: [0x14,0xee,0x41,0x0f]
139 # CHECK-NOFP: vhadd.s16 q0, q2, r1 @ encoding: [0x14,0xee,0x41,0x0f]
140 vhadd.s16 q0, q2, r1
141
142 # CHECK: vhadd.s32 q0, q0, r10 @ encoding: [0x20,0xee,0x4a,0x0f]
143 # CHECK-NOFP: vhadd.s32 q0, q0, r10 @ encoding: [0x20,0xee,0x4a,0x0f]
144 vhadd.s32 q0, q0, r10
145
146 # CHECK: vhadd.u8 q0, q5, lr @ encoding: [0x0a,0xfe,0x4e,0x0f]
147 # CHECK-NOFP: vhadd.u8 q0, q5, lr @ encoding: [0x0a,0xfe,0x4e,0x0f]
148 vhadd.u8 q0, q5, lr
149
150 # CHECK: vhadd.u16 q1, q2, r2 @ encoding: [0x14,0xfe,0x42,0x2f]
151 # CHECK-NOFP: vhadd.u16 q1, q2, r2 @ encoding: [0x14,0xfe,0x42,0x2f]
152 vhadd.u16 q1, q2, r2
153
154 # CHECK: vhadd.u32 q0, q2, r11 @ encoding: [0x24,0xfe,0x4b,0x0f]
155 # CHECK-NOFP: vhadd.u32 q0, q2, r11 @ encoding: [0x24,0xfe,0x4b,0x0f]
156 vhadd.u32 q0, q2, r11
157
158 # CHECK: vqrshl.s8 q0, r0 @ encoding: [0x33,0xee,0xe0,0x1e]
159 # CHECK-NOFP: vqrshl.s8 q0, r0 @ encoding: [0x33,0xee,0xe0,0x1e]
160 vqrshl.s8 q0, r0
161
162 # CHECK: vqrshl.s16 q0, r3 @ encoding: [0x37,0xee,0xe3,0x1e]
163 # CHECK-NOFP: vqrshl.s16 q0, r3 @ encoding: [0x37,0xee,0xe3,0x1e]
164 vqrshl.s16 q0, r3
165
166 # CHECK: vqrshl.s32 q0, lr @ encoding: [0x3b,0xee,0xee,0x1e]
167 # CHECK-NOFP: vqrshl.s32 q0, lr @ encoding: [0x3b,0xee,0xee,0x1e]
168 vqrshl.s32 q0, lr
169
170 # CHECK: vqrshl.u8 q0, r0 @ encoding: [0x33,0xfe,0xe0,0x1e]
171 # CHECK-NOFP: vqrshl.u8 q0, r0 @ encoding: [0x33,0xfe,0xe0,0x1e]
172 vqrshl.u8 q0, r0
173
174 # CHECK: vqrshl.u16 q0, r2 @ encoding: [0x37,0xfe,0xe2,0x1e]
175 # CHECK-NOFP: vqrshl.u16 q0, r2 @ encoding: [0x37,0xfe,0xe2,0x1e]
176 vqrshl.u16 q0, r2
177
178 # CHECK: vqrshl.u32 q0, r3 @ encoding: [0x3b,0xfe,0xe3,0x1e]
179 # CHECK-NOFP: vqrshl.u32 q0, r3 @ encoding: [0x3b,0xfe,0xe3,0x1e]
180 vqrshl.u32 q0, r3
181
182 # CHECK: vqshl.s8 q0, r0 @ encoding: [0x31,0xee,0xe0,0x1e]
183 # CHECK-NOFP: vqshl.s8 q0, r0 @ encoding: [0x31,0xee,0xe0,0x1e]
184 vqshl.s8 q0, r0
185
186 # CHECK: vqshl.s16 q1, r1 @ encoding: [0x35,0xee,0xe1,0x3e]
187 # CHECK-NOFP: vqshl.s16 q1, r1 @ encoding: [0x35,0xee,0xe1,0x3e]
188 vqshl.s16 q1, r1
189
190 # CHECK: vqshl.s32 q0, r3 @ encoding: [0x39,0xee,0xe3,0x1e]
191 # CHECK-NOFP: vqshl.s32 q0, r3 @ encoding: [0x39,0xee,0xe3,0x1e]
192 vqshl.s32 q0, r3
193
194 # CHECK: vqshl.u8 q0, r1 @ encoding: [0x31,0xfe,0xe1,0x1e]
195 # CHECK-NOFP: vqshl.u8 q0, r1 @ encoding: [0x31,0xfe,0xe1,0x1e]
196 vqshl.u8 q0, r1
197
198 # CHECK: vqshl.u16 q0, r11 @ encoding: [0x35,0xfe,0xeb,0x1e]
199 # CHECK-NOFP: vqshl.u16 q0, r11 @ encoding: [0x35,0xfe,0xeb,0x1e]
200 vqshl.u16 q0, r11
201
202 # CHECK: vqshl.u32 q0, lr @ encoding: [0x39,0xfe,0xee,0x1e]
203 # CHECK-NOFP: vqshl.u32 q0, lr @ encoding: [0x39,0xfe,0xee,0x1e]
204 vqshl.u32 q0, lr
205
206 # CHECK: vrshl.s8 q0, r6 @ encoding: [0x33,0xee,0x66,0x1e]
207 # CHECK-NOFP: vrshl.s8 q0, r6 @ encoding: [0x33,0xee,0x66,0x1e]
208 vrshl.s8 q0, r6
209
210 # CHECK: vrshl.s16 q0, lr @ encoding: [0x37,0xee,0x6e,0x1e]
211 # CHECK-NOFP: vrshl.s16 q0, lr @ encoding: [0x37,0xee,0x6e,0x1e]
212 vrshl.s16 q0, lr
213
214 # CHECK: vrshl.s32 q0, r4 @ encoding: [0x3b,0xee,0x64,0x1e]
215 # CHECK-NOFP: vrshl.s32 q0, r4 @ encoding: [0x3b,0xee,0x64,0x1e]
216 vrshl.s32 q0, r4
217
218 # CHECK: vrshl.u8 q0, r0 @ encoding: [0x33,0xfe,0x60,0x1e]
219 # CHECK-NOFP: vrshl.u8 q0, r0 @ encoding: [0x33,0xfe,0x60,0x1e]
220 vrshl.u8 q0, r0
221
222 # CHECK: vrshl.u16 q0, r10 @ encoding: [0x37,0xfe,0x6a,0x1e]
223 # CHECK-NOFP: vrshl.u16 q0, r10 @ encoding: [0x37,0xfe,0x6a,0x1e]
224 vrshl.u16 q0, r10
225
226 # CHECK: vrshl.u32 q0, r1 @ encoding: [0x3b,0xfe,0x61,0x1e]
227 # CHECK-NOFP: vrshl.u32 q0, r1 @ encoding: [0x3b,0xfe,0x61,0x1e]
228 vrshl.u32 q0, r1
229
230 # CHECK: vshl.s8 q0, lr @ encoding: [0x31,0xee,0x6e,0x1e]
231 # CHECK-NOFP: vshl.s8 q0, lr @ encoding: [0x31,0xee,0x6e,0x1e]
232 vshl.s8 q0, lr
233
234 # CHECK: vshl.s16 q0, lr @ encoding: [0x35,0xee,0x6e,0x1e]
235 # CHECK-NOFP: vshl.s16 q0, lr @ encoding: [0x35,0xee,0x6e,0x1e]
236 vshl.s16 q0, lr
237
238 # CHECK: vshl.s32 q0, r1 @ encoding: [0x39,0xee,0x61,0x1e]
239 # CHECK-NOFP: vshl.s32 q0, r1 @ encoding: [0x39,0xee,0x61,0x1e]
240 vshl.s32 q0, r1
241
242 # CHECK: vshl.u8 q0, r10 @ encoding: [0x31,0xfe,0x6a,0x1e]
243 # CHECK-NOFP: vshl.u8 q0, r10 @ encoding: [0x31,0xfe,0x6a,0x1e]
244 vshl.u8 q0, r10
245
246 # CHECK: vshl.u16 q1, r10 @ encoding: [0x35,0xfe,0x6a,0x3e]
247 # CHECK-NOFP: vshl.u16 q1, r10 @ encoding: [0x35,0xfe,0x6a,0x3e]
248 vshl.u16 q1, r10
249
250 # CHECK: vshl.u32 q0, r12 @ encoding: [0x39,0xfe,0x6c,0x1e]
251 # CHECK-NOFP: vshl.u32 q0, r12 @ encoding: [0x39,0xfe,0x6c,0x1e]
252 vshl.u32 q0, r12
253
254 # CHECK: vbrsr.8 q0, q4, r8 @ encoding: [0x09,0xfe,0x68,0x1e]
255 # CHECK-NOFP: vbrsr.8 q0, q4, r8 @ encoding: [0x09,0xfe,0x68,0x1e]
256 vbrsr.8 q0, q4, r8
257
258 # CHECK: vbrsr.16 q0, q1, r1 @ encoding: [0x13,0xfe,0x61,0x1e]
259 # CHECK-NOFP: vbrsr.16 q0, q1, r1 @ encoding: [0x13,0xfe,0x61,0x1e]
260 vbrsr.16 q0, q1, r1
261
262 # CHECK: vbrsr.32 q0, q6, r0 @ encoding: [0x2d,0xfe,0x60,0x1e]
263 # CHECK-NOFP: vbrsr.32 q0, q6, r0 @ encoding: [0x2d,0xfe,0x60,0x1e]
264 vbrsr.32 q0, q6, r0
265
266 # CHECK: vmul.i8 q0, q0, r12 @ encoding: [0x01,0xee,0x6c,0x1e]
267 # CHECK-NOFP: vmul.i8 q0, q0, r12 @ encoding: [0x01,0xee,0x6c,0x1e]
268 vmul.i8 q0, q0, r12
269
270 # CHECK: vmul.i16 q0, q4, r7 @ encoding: [0x19,0xee,0x67,0x1e]
271 # CHECK-NOFP: vmul.i16 q0, q4, r7 @ encoding: [0x19,0xee,0x67,0x1e]
272 vmul.i16 q0, q4, r7
273
274 # CHECK: vmul.i32 q0, q1, r11 @ encoding: [0x23,0xee,0x6b,0x1e]
275 # CHECK-NOFP: vmul.i32 q0, q1, r11 @ encoding: [0x23,0xee,0x6b,0x1e]
276 vmul.i32 q0, q1, r11
277
278 # CHECK: vmul.f16 q0, q0, r10 @ encoding: [0x31,0xfe,0x6a,0x0e]
279 # CHECK-NOFP-NOT: vmul.f16 q0, q0, r10 @ encoding: [0x31,0xfe,0x6a,0x0e]
280 vmul.f16 q0, q0, r10
281
282 # CHECK: vmul.f32 q0, q1, r7 @ encoding: [0x33,0xee,0x67,0x0e]
283 # CHECK-NOFP-NOT: vmul.f32 q0, q1, r7 @ encoding: [0x33,0xee,0x67,0x0e]
284 vmul.f32 q0, q1, r7
285
286 # CHECK: vqdmulh.s8 q0, q1, r6 @ encoding: [0x03,0xee,0x66,0x0e]
287 # CHECK-NOFP: vqdmulh.s8 q0, q1, r6 @ encoding: [0x03,0xee,0x66,0x0e]
288 vqdmulh.s8 q0, q1, r6
289
290 # CHECK: vqdmulh.s16 q0, q2, r2 @ encoding: [0x15,0xee,0x62,0x0e]
291 # CHECK-NOFP: vqdmulh.s16 q0, q2, r2 @ encoding: [0x15,0xee,0x62,0x0e]
292 vqdmulh.s16 q0, q2, r2
293
294 # CHECK: vqdmulh.s32 q1, q3, r8 @ encoding: [0x27,0xee,0x68,0x2e]
295 # CHECK-NOFP: vqdmulh.s32 q1, q3, r8 @ encoding: [0x27,0xee,0x68,0x2e]
296 vqdmulh.s32 q1, q3, r8
297
298 # CHECK: vqrdmulh.s8 q0, q2, r6 @ encoding: [0x05,0xfe,0x66,0x0e]
299 # CHECK-NOFP: vqrdmulh.s8 q0, q2, r6 @ encoding: [0x05,0xfe,0x66,0x0e]
300 vqrdmulh.s8 q0, q2, r6
301
302 # CHECK: vqrdmulh.s16 q0, q0, r2 @ encoding: [0x11,0xfe,0x62,0x0e]
303 # CHECK-NOFP: vqrdmulh.s16 q0, q0, r2 @ encoding: [0x11,0xfe,0x62,0x0e]
304 vqrdmulh.s16 q0, q0, r2
305
306 # CHECK: vqrdmulh.s32 q0, q0, r2 @ encoding: [0x21,0xfe,0x62,0x0e]
307 # CHECK-NOFP: vqrdmulh.s32 q0, q0, r2 @ encoding: [0x21,0xfe,0x62,0x0e]
308 vqrdmulh.s32 q0, q0, r2
309
310 # CHECK: vfmas.f16 q0, q0, r12 @ encoding: [0x31,0xfe,0x4c,0x1e]
311 # CHECK-NOFP-NOT: vfmas.f16 q0, q0, r12 @ encoding: [0x31,0xfe,0x4c,0x1e]
312 vfmas.f16 q0, q0, r12
313
314 # CHECK: vfmas.f32 q0, q3, lr @ encoding: [0x37,0xee,0x4e,0x1e]
315 # CHECK-NOFP-NOT: vfmas.f32 q0, q3, lr @ encoding: [0x37,0xee,0x4e,0x1e]
316 vfmas.f32 q0, q3, lr
317
318 # CHECK: vmlas.s8 q0, q0, r6 @ encoding: [0x01,0xee,0x46,0x1e]
319 # CHECK-NOFP: vmlas.s8 q0, q0, r6 @ encoding: [0x01,0xee,0x46,0x1e]
320 vmlas.s8 q0, q0, r6
321
322 # CHECK: vmlas.s16 q0, q2, r9 @ encoding: [0x15,0xee,0x49,0x1e]
323 # CHECK-NOFP: vmlas.s16 q0, q2, r9 @ encoding: [0x15,0xee,0x49,0x1e]
324 vmlas.s16 q0, q2, r9
325
326 # CHECK: vmlas.s32 q0, q7, r6 @ encoding: [0x2f,0xee,0x46,0x1e]
327 # CHECK-NOFP: vmlas.s32 q0, q7, r6 @ encoding: [0x2f,0xee,0x46,0x1e]
328 vmlas.s32 q0, q7, r6
329
330 # CHECK: vmlas.u8 q0, q5, lr @ encoding: [0x0b,0xfe,0x4e,0x1e]
331 # CHECK-NOFP: vmlas.u8 q0, q5, lr @ encoding: [0x0b,0xfe,0x4e,0x1e]
332 vmlas.u8 q0, q5, lr
333
334 # CHECK: vmlas.u16 q0, q3, r12 @ encoding: [0x17,0xfe,0x4c,0x1e]
335 # CHECK-NOFP: vmlas.u16 q0, q3, r12 @ encoding: [0x17,0xfe,0x4c,0x1e]
336 vmlas.u16 q0, q3, r12
337
338 # CHECK: vmlas.u32 q1, q1, r11 @ encoding: [0x23,0xfe,0x4b,0x3e]
339 # CHECK-NOFP: vmlas.u32 q1, q1, r11 @ encoding: [0x23,0xfe,0x4b,0x3e]
340 vmlas.u32 q1, q1, r11
341
342 # CHECK: vfma.f16 q1, q1, r6 @ encoding: [0x33,0xfe,0x46,0x2e]
343 # CHECK-NOFP-NOT: vfma.f16 q1, q1, r6 @ encoding: [0x33,0xfe,0x46,0x2e]
344 vfma.f16 q1, q1, r6
345
346 # CHECK: vfmas.f32 q7, q4, r6 @ encoding: [0x39,0xee,0x46,0xfe]
347 # CHECK-NOFP-NOT: vfmas.f32 q7, q4, r6 @ encoding: [0x39,0xee,0x46,0xfe]
348 vfmas.f32 q7, q4, r6
349
350 # CHECK: vmla.s8 q0, q3, r8 @ encoding: [0x07,0xee,0x48,0x0e]
351 # CHECK-NOFP: vmla.s8 q0, q3, r8 @ encoding: [0x07,0xee,0x48,0x0e]
352 vmla.s8 q0, q3, r8
353
354 # CHECK: vmla.s16 q1, q3, r10 @ encoding: [0x17,0xee,0x4a,0x2e]
355 # CHECK-NOFP: vmla.s16 q1, q3, r10 @ encoding: [0x17,0xee,0x4a,0x2e]
356 vmla.s16 q1, q3, r10
357
358 # CHECK: vmla.s32 q1, q3, r1 @ encoding: [0x27,0xee,0x41,0x2e]
359 # CHECK-NOFP: vmla.s32 q1, q3, r1 @ encoding: [0x27,0xee,0x41,0x2e]
360 vmla.s32 q1, q3, r1
361
362 # CHECK: vmla.u8 q0, q7, r10 @ encoding: [0x0f,0xfe,0x4a,0x0e]
363 # CHECK-NOFP: vmla.u8 q0, q7, r10 @ encoding: [0x0f,0xfe,0x4a,0x0e]
364 vmla.u8 q0, q7, r10
365
366 # CHECK: vmla.u16 q0, q0, r7 @ encoding: [0x11,0xfe,0x47,0x0e]
367 # CHECK-NOFP: vmla.u16 q0, q0, r7 @ encoding: [0x11,0xfe,0x47,0x0e]
368 vmla.u16 q0, q0, r7
369
370 # CHECK: vmla.u32 q1, q6, r10 @ encoding: [0x2d,0xfe,0x4a,0x2e]
371 # CHECK-NOFP: vmla.u32 q1, q6, r10 @ encoding: [0x2d,0xfe,0x4a,0x2e]
372 vmla.u32 q1, q6, r10
373
374 # CHECK: vqdmlash.s8 q0, q0, r5 @ encoding: [0x00,0xee,0x65,0x1e]
375 # CHECK-NOFP: vqdmlash.s8 q0, q0, r5 @ encoding: [0x00,0xee,0x65,0x1e]
376 vqdmlash.s8 q0, q0, r5
377
378 # CHECK: vqdmlash.s16 q0, q5, lr @ encoding: [0x1a,0xee,0x6e,0x1e]
379 # CHECK-NOFP: vqdmlash.s16 q0, q5, lr @ encoding: [0x1a,0xee,0x6e,0x1e]
380 vqdmlash.s16 q0, q5, lr
381
382 # CHECK: vqdmlash.s32 q0, q2, r3 @ encoding: [0x24,0xee,0x63,0x1e]
383 # CHECK-NOFP: vqdmlash.s32 q0, q2, r3 @ encoding: [0x24,0xee,0x63,0x1e]
384 vqdmlash.s32 q0, q2, r3
385
386 # CHECK: vqdmlash.u8 q0, q4, r2 @ encoding: [0x08,0xfe,0x62,0x1e]
387 # CHECK-NOFP: vqdmlash.u8 q0, q4, r2 @ encoding: [0x08,0xfe,0x62,0x1e]
388 vqdmlash.u8 q0, q4, r2
389
390 # CHECK: vqdmlash.u16 q1, q4, r2 @ encoding: [0x18,0xfe,0x62,0x3e]
391 # CHECK-NOFP: vqdmlash.u16 q1, q4, r2 @ encoding: [0x18,0xfe,0x62,0x3e]
392 vqdmlash.u16 q1, q4, r2
393
394 # CHECK: vqdmlash.u32 q1, q5, r0 @ encoding: [0x2a,0xfe,0x60,0x3e]
395 # CHECK-NOFP: vqdmlash.u32 q1, q5, r0 @ encoding: [0x2a,0xfe,0x60,0x3e]
396 vqdmlash.u32 q1, q5, r0
397
398 # CHECK: vqdmlah.s8 q0, q3, r3 @ encoding: [0x06,0xee,0x63,0x0e]
399 # CHECK-NOFP: vqdmlah.s8 q0, q3, r3 @ encoding: [0x06,0xee,0x63,0x0e]
400 vqdmlah.s8 q0, q3, r3
401
402 # CHECK: vqdmlah.s16 q5, q3, r9 @ encoding: [0x16,0xee,0x69,0xae]
403 # CHECK-NOFP: vqdmlah.s16 q5, q3, r9 @ encoding: [0x16,0xee,0x69,0xae]
404 vqdmlah.s16 q5, q3, r9
405
406 # CHECK: vqdmlah.s32 q0, q1, r11 @ encoding: [0x22,0xee,0x6b,0x0e]
407 # CHECK-NOFP: vqdmlah.s32 q0, q1, r11 @ encoding: [0x22,0xee,0x6b,0x0e]
408 vqdmlah.s32 q0, q1, r11
409
410 # CHECK: vqdmlah.u8 q0, q2, lr @ encoding: [0x04,0xfe,0x6e,0x0e]
411 # CHECK-NOFP: vqdmlah.u8 q0, q2, lr @ encoding: [0x04,0xfe,0x6e,0x0e]
412 vqdmlah.u8 q0, q2, lr
413
414 # CHECK: vqdmlah.u16 q0, q3, r10 @ encoding: [0x16,0xfe,0x6a,0x0e]
415 # CHECK-NOFP: vqdmlah.u16 q0, q3, r10 @ encoding: [0x16,0xfe,0x6a,0x0e]
416 vqdmlah.u16 q0, q3, r10
417
418 # CHECK: vqdmlah.u32 q1, q5, r2 @ encoding: [0x2a,0xfe,0x62,0x2e]
419 # CHECK-NOFP: vqdmlah.u32 q1, q5, r2 @ encoding: [0x2a,0xfe,0x62,0x2e]
420 vqdmlah.u32 q1, q5, r2
421
422 # CHECK: vqrdmlash.s8 q0, q5, r10 @ encoding: [0x0a,0xee,0x4a,0x1e]
423 # CHECK-NOFP: vqrdmlash.s8 q0, q5, r10 @ encoding: [0x0a,0xee,0x4a,0x1e]
424 vqrdmlash.s8 q0, q5, r10
425
426 # CHECK: vqrdmlash.s16 q0, q3, r2 @ encoding: [0x16,0xee,0x42,0x1e]
427 # CHECK-NOFP: vqrdmlash.s16 q0, q3, r2 @ encoding: [0x16,0xee,0x42,0x1e]
428 vqrdmlash.s16 q0, q3, r2
429
430 # CHECK: vqrdmlash.s32 q0, q0, r4 @ encoding: [0x20,0xee,0x44,0x1e]
431 # CHECK-NOFP: vqrdmlash.s32 q0, q0, r4 @ encoding: [0x20,0xee,0x44,0x1e]
432 vqrdmlash.s32 q0, q0, r4
433
434 # CHECK: vqrdmlash.u8 q0, q4, r9 @ encoding: [0x08,0xfe,0x49,0x1e]
435 # CHECK-NOFP: vqrdmlash.u8 q0, q4, r9 @ encoding: [0x08,0xfe,0x49,0x1e]
436 vqrdmlash.u8 q0, q4, r9
437
438 # CHECK: vqrdmlash.u16 q0, q6, r12 @ encoding: [0x1c,0xfe,0x4c,0x1e]
439 # CHECK-NOFP: vqrdmlash.u16 q0, q6, r12 @ encoding: [0x1c,0xfe,0x4c,0x1e]
440 vqrdmlash.u16 q0, q6, r12
441
442 # CHECK: vqrdmlash.u32 q0, q3, r7 @ encoding: [0x26,0xfe,0x47,0x1e]
443 # CHECK-NOFP: vqrdmlash.u32 q0, q3, r7 @ encoding: [0x26,0xfe,0x47,0x1e]
444 vqrdmlash.u32 q0, q3, r7
445
446 # CHECK: vqrdmlah.s8 q0, q5, r11 @ encoding: [0x0a,0xee,0x4b,0x0e]
447 # CHECK-NOFP: vqrdmlah.s8 q0, q5, r11 @ encoding: [0x0a,0xee,0x4b,0x0e]
448 vqrdmlah.s8 q0, q5, r11
449
450 # CHECK: vqrdmlah.s16 q0, q2, r10 @ encoding: [0x14,0xee,0x4a,0x0e]
451 # CHECK-NOFP: vqrdmlah.s16 q0, q2, r10 @ encoding: [0x14,0xee,0x4a,0x0e]
452 vqrdmlah.s16 q0, q2, r10
453
454 # CHECK: vqrdmlah.s32 q0, q4, r11 @ encoding: [0x28,0xee,0x4b,0x0e]
455 # CHECK-NOFP: vqrdmlah.s32 q0, q4, r11 @ encoding: [0x28,0xee,0x4b,0x0e]
456 vqrdmlah.s32 q0, q4, r11
457
458 # CHECK: vqrdmlah.u8 q0, q4, r2 @ encoding: [0x08,0xfe,0x42,0x0e]
459 # CHECK-NOFP: vqrdmlah.u8 q0, q4, r2 @ encoding: [0x08,0xfe,0x42,0x0e]
460 vqrdmlah.u8 q0, q4, r2
461
462 # CHECK: vqrdmlah.u16 q0, q6, r1 @ encoding: [0x1c,0xfe,0x41,0x0e]
463 # CHECK-NOFP: vqrdmlah.u16 q0, q6, r1 @ encoding: [0x1c,0xfe,0x41,0x0e]
464 vqrdmlah.u16 q0, q6, r1
465
466 # CHECK: vqrdmlah.u32 q0, q4, r2 @ encoding: [0x28,0xfe,0x42,0x0e]
467 # CHECK-NOFP: vqrdmlah.u32 q0, q4, r2 @ encoding: [0x28,0xfe,0x42,0x0e]
468 vqrdmlah.u32 q0, q4, r2
469
470 # CHECK: viwdup.u8 q0, lr, r1, #1 @ encoding: [0x0f,0xee,0x60,0x0f]
471 # CHECK-NOFP: viwdup.u8 q0, lr, r1, #1 @ encoding: [0x0f,0xee,0x60,0x0f]
472 viwdup.u8 q0, lr, r1, #1
473
474 # CHECK: viwdup.u16 q1, r10, r1, #8 @ encoding: [0x1b,0xee,0xe1,0x2f]
475 # CHECK-NOFP: viwdup.u16 q1, r10, r1, #8 @ encoding: [0x1b,0xee,0xe1,0x2f]
476 viwdup.u16 q1, r10, r1, #8
477
478 # CHECK: viwdup.u32 q6, r10, r5, #4 @ encoding: [0x2b,0xee,0xe4,0xcf]
479 # CHECK-NOFP: viwdup.u32 q6, r10, r5, #4 @ encoding: [0x2b,0xee,0xe4,0xcf]
480 viwdup.u32 q6, r10, r5, #4
481
482 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector increment immediate must be 1, 2, 4 or 8
483 viwdup.u32 q6, r10, r5, #3
484
485 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an even-numbered register
486 viwdup.u32 q6, r3, r5, #4
487
488 # CHECK: vdwdup.u8 q0, r12, r11, #8 @ encoding: [0x0d,0xee,0xeb,0x1f]
489 # CHECK-NOFP: vdwdup.u8 q0, r12, r11, #8 @ encoding: [0x0d,0xee,0xeb,0x1f]
490 vdwdup.u8 q0, r12, r11, #8
491
492 # CHECK: vdwdup.u16 q0, r12, r1, #2 @ encoding: [0x1d,0xee,0x61,0x1f]
493 # CHECK-NOFP: vdwdup.u16 q0, r12, r1, #2 @ encoding: [0x1d,0xee,0x61,0x1f]
494 vdwdup.u16 q0, r12, r1, #2
495
496 # CHECK: vdwdup.u32 q0, r0, r7, #8 @ encoding: [0x21,0xee,0xe7,0x1f]
497 # CHECK-NOFP: vdwdup.u32 q0, r0, r7, #8 @ encoding: [0x21,0xee,0xe7,0x1f]
498 vdwdup.u32 q0, r0, r7, #8
499
500 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector increment immediate must be 1, 2, 4 or 8
501 vdwdup.u32 q0, r0, r7, #9
502
503 # CHECK: vidup.u8 q0, lr, #2 @ encoding: [0x0f,0xee,0x6f,0x0f]
504 # CHECK-NOFP: vidup.u8 q0, lr, #2 @ encoding: [0x0f,0xee,0x6f,0x0f]
505 vidup.u8 q0, lr, #2
506
507 # CHECK: vidup.u16 q0, lr, #4 @ encoding: [0x1f,0xee,0xee,0x0f]
508 # CHECK-NOFP: vidup.u16 q0, lr, #4 @ encoding: [0x1f,0xee,0xee,0x0f]
509 vidup.u16 q0, lr, #4
510
511 # CHECK: vidup.u32 q0, r12, #1 @ encoding: [0x2d,0xee,0x6e,0x0f]
512 # CHECK-NOFP: vidup.u32 q0, r12, #1 @ encoding: [0x2d,0xee,0x6e,0x0f]
513 vidup.u32 q0, r12, #1
514
515 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector increment immediate must be 1, 2, 4 or 8
516 vidup.u32 q0, r12, #3
517
518 # CHECK: vddup.u8 q0, r4, #4 @ encoding: [0x05,0xee,0xee,0x1f]
519 # CHECK-NOFP: vddup.u8 q0, r4, #4 @ encoding: [0x05,0xee,0xee,0x1f]
520 vddup.u8 q0, r4, #4
521
522 # CHECK: vddup.u16 q0, r10, #4 @ encoding: [0x1b,0xee,0xee,0x1f]
523 # CHECK-NOFP: vddup.u16 q0, r10, #4 @ encoding: [0x1b,0xee,0xee,0x1f]
524 vddup.u16 q0, r10, #4
525
526 # CHECK: vddup.u32 q2, r0, #8 @ encoding: [0x21,0xee,0xef,0x5f]
527 # CHECK-NOFP: vddup.u32 q2, r0, #8 @ encoding: [0x21,0xee,0xef,0x5f]
528 vddup.u32 q2, r0, #8
529
530 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector increment immediate must be 1, 2, 4 or 8
531 vddup.u32 q2, r0, #5
532
533 # CHECK: vctp.8 lr @ encoding: [0x0e,0xf0,0x01,0xe8]
534 # CHECK-NOFP: vctp.8 lr @ encoding: [0x0e,0xf0,0x01,0xe8]
535 vctp.8 lr
536
537 # CHECK: vctp.16 r0 @ encoding: [0x10,0xf0,0x01,0xe8]
538 # CHECK-NOFP: vctp.16 r0 @ encoding: [0x10,0xf0,0x01,0xe8]
539 vctp.16 r0
540
541 # CHECK: vctp.32 r10 @ encoding: [0x2a,0xf0,0x01,0xe8]
542 # CHECK-NOFP: vctp.32 r10 @ encoding: [0x2a,0xf0,0x01,0xe8]
543 vctp.32 r10
544
545 # CHECK: vctp.64 r1 @ encoding: [0x31,0xf0,0x01,0xe8]
546 # CHECK-NOFP: vctp.64 r1 @ encoding: [0x31,0xf0,0x01,0xe8]
547 vctp.64 r1
548
549 vpste
550 vmult.i8 q0, q1, q2
551 vmule.i16 q0, q1, q2
552 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
553 # CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
554 # CHECK: vmult.i8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x09]
555 # CHECK-NOFP: vmult.i8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x09]
556 # CHECK: vmule.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
557 # CHECK-NOFP: vmule.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
558
559 vpste
560 vmult.i16 q0, q1, q2
561 vmule.i16 q1, q2, q3
562 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
563 # CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
564 # CHECK: vmult.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
565 # CHECK-NOFP: vmult.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
566 # CHECK: vmule.i16 q1, q2, q3 @ encoding: [0x14,0xef,0x56,0x29]
567 # CHECK-NOFP: vmule.i16 q1, q2, q3 @ encoding: [0x14,0xef,0x56,0x29]
568
569 vqrshl.u32 q0, r0
570 # CHECK: vqrshl.u32 q0, r0 @ encoding: [0x3b,0xfe,0xe0,0x1e]
571 # CHECK-NOFP: vqrshl.u32 q0, r0 @ encoding: [0x3b,0xfe,0xe0,0x1e]
572
573 vpste
574 vqrshlt.u16 q0, r0
575 vqrshle.s16 q0, q1, q2
576 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
577 # CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
578 # CHECK: vqrshlt.u16 q0, r0 @ encoding: [0x37,0xfe,0xe0,0x1e]
579 # CHECK-NOFP: vqrshlt.u16 q0, r0 @ encoding: [0x37,0xfe,0xe0,0x1e]
580 # CHECK: vqrshle.s16 q0, q1, q2 @ encoding: [0x14,0xef,0x52,0x05]
581 # CHECK-NOFP: vqrshle.s16 q0, q1, q2 @ encoding: [0x14,0xef,0x52,0x05]
582
583 vpste
584 vrshlt.u16 q0, q1, q2
585 vrshle.s32 q0, r0
586 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
587 # CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
588 # CHECK: vrshlt.u16 q0, q1, q2 @ encoding: [0x14,0xff,0x42,0x05]
589 # CHECK-NOFP: vrshlt.u16 q0, q1, q2 @ encoding: [0x14,0xff,0x42,0x05]
590 # CHECK: vrshle.s32 q0, r0 @ encoding: [0x3b,0xee,0x60,0x1e]
591 # CHECK-NOFP: vrshle.s32 q0, r0 @ encoding: [0x3b,0xee,0x60,0x1e]
592
593 vpste
594 vshlt.s8 q0, r0
595 vshle.u32 q0, r0
596 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
597 # CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
598 # CHECK: vshlt.s8 q0, r0 @ encoding: [0x31,0xee,0x60,0x1e]
599 # CHECK-NOFP: vshlt.s8 q0, r0 @ encoding: [0x31,0xee,0x60,0x1e]
600 # CHECK: vshle.u32 q0, r0 @ encoding: [0x39,0xfe,0x60,0x1e]
601 # CHECK-NOFP: vshle.u32 q0, r0 @ encoding: [0x39,0xfe,0x60,0x1e]
2525 # CHECK: vaddv.s16 lr, q0 @ encoding: [0xf5,0xee,0x00,0xef]
2626 vaddv.s16 lr, q0
2727
28 # ERROR: [[@LINE+1]]:11: {{error|note}}: invalid operand for instruction
28 # ERROR: [[@LINE+1]]:11: {{error|note}}: operand must be an even-numbered register
2929 vaddv.s16 r1, q0
3030
3131 # CHECK: vpte.i8 eq, q0, q0
4848 # CHECK: vaddlv.s32 r0, r9, q2 @ encoding: [0xc9,0xee,0x04,0x0f]
4949 vaddlv.s32 r0, r9, q2
5050
51 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
51 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]
5252 vaddlv.s32 r0, r2, q2
5353
54 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
54 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an even-numbered register
5555 vaddlv.s32 r1, r3, q2
5656
5757 # CHECK: vaddlv.u32 r0, r1, q1 @ encoding: [0x89,0xfe,0x02,0x0f]
144144 # CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
145145 vrmlaldavh.u32 lr, r1, q5, q2
146146
147 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
147 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an even-numbered register
148148 vrmlaldavh.u32 r1, r3, q5, q2
149149
150 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
150 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]
151151 vrmlaldavh.u32 r2, r4, q5, q2
152152
153153 # CHECK: vrmlaldavhax.s32 lr, r1, q3, q0 @ encoding: [0x86,0xee,0x20,0xff]
2929 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
3030 asrl r0, r1, #33
3131
32 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
32 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]
3333 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
3434 asrl r0, r0, #32
3535
3737 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
3838 asrl r0, r1, r4
3939
40 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
40 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]
4141 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
4242 asrl r0, r0, r4
4343
0 # RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
1 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
2 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
3
4 # CHECK: vsub.i8 q0, q3, r3 @ encoding: [0x07,0xee,0x43,0x1f]
5 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
6 [0x07,0xee,0x43,0x1f]
7
8 # CHECK: vsub.i16 q0, q7, lr @ encoding: [0x1f,0xee,0x4e,0x1f]
9 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
10 [0x1f,0xee,0x4e,0x1f]
11
12 # CHECK: vsub.i32 q1, q5, r10 @ encoding: [0x2b,0xee,0x4a,0x3f]
13 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
14 [0x2b,0xee,0x4a,0x3f]
15
16 # CHECK: vadd.i8 q1, q4, r7 @ encoding: [0x09,0xee,0x47,0x2f]
17 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
18 [0x09,0xee,0x47,0x2f]
19
20 # CHECK: vadd.i16 q0, q6, r11 @ encoding: [0x1d,0xee,0x4b,0x0f]
21 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
22 [0x1d,0xee,0x4b,0x0f]
23
24 # CHECK: vadd.i32 q0, q1, r6 @ encoding: [0x23,0xee,0x46,0x0f]
25 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
26 [0x23,0xee,0x46,0x0f]
27
28 # CHECK: vqsub.s8 q2, q2, r8 @ encoding: [0x04,0xee,0x68,0x5f]
29 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
30 [0x04,0xee,0x68,0x5f]
31
32 # CHECK: vqsub.s16 q1, q4, r0 @ encoding: [0x18,0xee,0x60,0x3f]
33 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
34 [0x18,0xee,0x60,0x3f]
35
36 # CHECK: vqsub.s32 q0, q2, r0 @ encoding: [0x24,0xee,0x60,0x1f]
37 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
38 [0x24,0xee,0x60,0x1f]
39
40 # CHECK: vqsub.u8 q0, q1, r2 @ encoding: [0x02,0xfe,0x62,0x1f]
41 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
42 [0x02,0xfe,0x62,0x1f]
43
44 # CHECK: vqsub.u16 q0, q2, r6 @ encoding: [0x14,0xfe,0x66,0x1f]
45 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
46 [0x14,0xfe,0x66,0x1f]
47
48 # CHECK: vqsub.u32 q0, q2, r2 @ encoding: [0x24,0xfe,0x62,0x1f]
49 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
50 [0x24,0xfe,0x62,0x1f]
51
52 # CHECK: vqadd.s8 q0, q6, r1 @ encoding: [0x0c,0xee,0x61,0x0f]
53 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
54 [0x0c,0xee,0x61,0x0f]
55
56 # CHECK: vqadd.s16 q3, q4, r2 @ encoding: [0x18,0xee,0x62,0x6f]
57 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
58 [0x18,0xee,0x62,0x6f]
59
60 # CHECK: vqadd.s32 q0, q5, r11 @ encoding: [0x2a,0xee,0x6b,0x0f]
61 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
62 [0x2a,0xee,0x6b,0x0f]
63
64 # CHECK: vqadd.u8 q0, q1, r8 @ encoding: [0x02,0xfe,0x68,0x0f]
65 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
66 [0x02,0xfe,0x68,0x0f]
67
68 # CHECK: vqadd.u16 q0, q5, r9 @ encoding: [0x1a,0xfe,0x69,0x0f]
69 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
70 [0x1a,0xfe,0x69,0x0f]
71
72 # CHECK: vqadd.u32 q0, q0, r7 @ encoding: [0x20,0xfe,0x67,0x0f]
73 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
74 [0x20,0xfe,0x67,0x0f]
75
76 # CHECK: vqdmullb.s16 q0, q1, r6 @ encoding: [0x32,0xee,0x66,0x0f]
77 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
78 [0x32,0xee,0x66,0x0f]
79
80 # CHECK: vqdmullb.s32 q0, q3, q7 @ encoding: [0x36,0xfe,0x0f,0x0f]
81 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
82 [0x36,0xfe,0x0f,0x0f]
83
84 # CHECK: vqdmullt.s16 q0, q1, r0 @ encoding: [0x32,0xee,0x60,0x1f]
85 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
86 [0x32,0xee,0x60,0x1f]
87
88 # CHECK: vqdmullt.s32 q0, q4, r5 @ encoding: [0x38,0xfe,0x65,0x1f]
89 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
90 [0x38,0xfe,0x65,0x1f]
91
92 # CHECK: vsub.f16 q0, q3, r7 @ encoding: [0x36,0xfe,0x47,0x1f]
93 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
94 [0x36,0xfe,0x47,0x1f]
95
96 # CHECK: vsub.f32 q1, q1, r10 @ encoding: [0x32,0xee,0x4a,0x3f]
97 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
98 [0x32,0xee,0x4a,0x3f]
99
100 # CHECK: vadd.f16 q0, q1, lr @ encoding: [0x32,0xfe,0x4e,0x0f]
101 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
102 [0x32,0xfe,0x4e,0x0f]
103
104 # CHECK: vadd.f32 q1, q4, r4 @ encoding: [0x38,0xee,0x44,0x2f]
105 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
106 [0x38,0xee,0x44,0x2f]
107
108 # CHECK: vhsub.s8 q0, q3, lr @ encoding: [0x06,0xee,0x4e,0x1f]
109 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
110 [0x06,0xee,0x4e,0x1f]
111
112 # CHECK: vhsub.s16 q0, q0, r6 @ encoding: [0x10,0xee,0x46,0x1f]
113 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
114 [0x10,0xee,0x46,0x1f]
115
116 # CHECK: vhsub.s32 q1, q2, r7 @ encoding: [0x24,0xee,0x47,0x3f]
117 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
118 [0x24,0xee,0x47,0x3f]
119
120 # CHECK: vhsub.u8 q1, q6, r5 @ encoding: [0x0c,0xfe,0x45,0x3f]
121 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
122 [0x0c,0xfe,0x45,0x3f]
123
124 # CHECK: vhsub.u16 q0, q4, r10 @ encoding: [0x18,0xfe,0x4a,0x1f]
125 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
126 [0x18,0xfe,0x4a,0x1f]
127
128 # CHECK: vhsub.u32 q0, q4, r12 @ encoding: [0x28,0xfe,0x4c,0x1f]
129 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
130 [0x28,0xfe,0x4c,0x1f]
131
132 # CHECK: vhadd.s8 q0, q2, r1 @ encoding: [0x04,0xee,0x41,0x0f]
133 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
134 [0x04,0xee,0x41,0x0f]
135
136 # CHECK: vhadd.s16 q0, q2, r1 @ encoding: [0x14,0xee,0x41,0x0f]
137 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
138 [0x14,0xee,0x41,0x0f]
139
140 # CHECK: vhadd.s32 q0, q0, r10 @ encoding: [0x20,0xee,0x4a,0x0f]
141 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
142 [0x20,0xee,0x4a,0x0f]
143
144 # CHECK: vhadd.u8 q0, q5, lr @ encoding: [0x0a,0xfe,0x4e,0x0f]
145 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
146 [0x0a,0xfe,0x4e,0x0f]
147
148 # CHECK: vhadd.u16 q1, q2, r2 @ encoding: [0x14,0xfe,0x42,0x2f]
149 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
150 [0x14,0xfe,0x42,0x2f]
151
152 # CHECK: vhadd.u32 q0, q2, r11 @ encoding: [0x24,0xfe,0x4b,0x0f]
153 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
154 [0x24,0xfe,0x4b,0x0f]
155
156 # CHECK: vqrshl.s8 q0, r0 @ encoding: [0x33,0xee,0xe0,0x1e]
157 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
158 [0x33,0xee,0xe0,0x1e]
159
160 # CHECK: vqrshl.s16 q0, r3 @ encoding: [0x37,0xee,0xe3,0x1e]
161 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
162 [0x37,0xee,0xe3,0x1e]
163
164 # CHECK: vqrshl.s32 q0, lr @ encoding: [0x3b,0xee,0xee,0x1e]
165 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
166 [0x3b,0xee,0xee,0x1e]
167
168 # CHECK: vqrshl.u8 q0, r0 @ encoding: [0x33,0xfe,0xe0,0x1e]
169 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
170 [0x33,0xfe,0xe0,0x1e]
171
172 # CHECK: vqrshl.u16 q0, r2 @ encoding: [0x37,0xfe,0xe2,0x1e]
173 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
174 [0x37,0xfe,0xe2,0x1e]
175
176 # CHECK: vqrshl.u32 q0, r3 @ encoding: [0x3b,0xfe,0xe3,0x1e]
177 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
178 [0x3b,0xfe,0xe3,0x1e]
179
180 # CHECK: vqshl.s8 q0, r0 @ encoding: [0x31,0xee,0xe0,0x1e]
181 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
182 [0x31,0xee,0xe0,0x1e]
183
184 # CHECK: vqshl.s16 q1, r1 @ encoding: [0x35,0xee,0xe1,0x3e]
185 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
186 [0x35,0xee,0xe1,0x3e]
187
188 # CHECK: vqshl.s32 q0, r3 @ encoding: [0x39,0xee,0xe3,0x1e]
189 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
190 [0x39,0xee,0xe3,0x1e]
191
192 # CHECK: vqshl.u8 q0, r1 @ encoding: [0x31,0xfe,0xe1,0x1e]
193 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
194 [0x31,0xfe,0xe1,0x1e]
195
196 # CHECK: vqshl.u16 q0, r11 @ encoding: [0x35,0xfe,0xeb,0x1e]
197 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
198 [0x35,0xfe,0xeb,0x1e]
199
200 # CHECK: vqshl.u32 q0, lr @ encoding: [0x39,0xfe,0xee,0x1e]
201 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
202 [0x39,0xfe,0xee,0x1e]
203
204 # CHECK: vrshl.s8 q0, r6 @ encoding: [0x33,0xee,0x66,0x1e]
205 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
206 [0x33,0xee,0x66,0x1e]
207
208 # CHECK: vrshl.s16 q0, lr @ encoding: [0x37,0xee,0x6e,0x1e]
209 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
210 [0x37,0xee,0x6e,0x1e]
211
212 # CHECK: vrshl.s32 q0, r4 @ encoding: [0x3b,0xee,0x64,0x1e]
213 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
214 [0x3b,0xee,0x64,0x1e]
215
216 # CHECK: vrshl.u8 q0, r0 @ encoding: [0x33,0xfe,0x60,0x1e]
217 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
218 [0x33,0xfe,0x60,0x1e]
219
220 # CHECK: vrshl.u16 q0, r10 @ encoding: [0x37,0xfe,0x6a,0x1e]
221 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
222 [0x37,0xfe,0x6a,0x1e]
223
224 # CHECK: vrshl.u32 q0, r1 @ encoding: [0x3b,0xfe,0x61,0x1e]
225 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
226 [0x3b,0xfe,0x61,0x1e]
227
228 # CHECK: vshl.s8 q0, lr @ encoding: [0x31,0xee,0x6e,0x1e]
229 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
230 [0x31,0xee,0x6e,0x1e]
231
232 # CHECK: vshl.s16 q0, lr @ encoding: [0x35,0xee,0x6e,0x1e]
233 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
234 [0x35,0xee,0x6e,0x1e]
235
236 # CHECK: vshl.s32 q0, r1 @ encoding: [0x39,0xee,0x61,0x1e]
237 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
238 [0x39,0xee,0x61,0x1e]
239
240 # CHECK: vshl.u8 q0, r10 @ encoding: [0x31,0xfe,0x6a,0x1e]
241 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
242 [0x31,0xfe,0x6a,0x1e]
243
244 # CHECK: vshl.u16 q1, r10 @ encoding: [0x35,0xfe,0x6a,0x3e]
245 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
246 [0x35,0xfe,0x6a,0x3e]
247
248 # CHECK: vshl.u32 q0, r12 @ encoding: [0x39,0xfe,0x6c,0x1e]
249 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
250 [0x39,0xfe,0x6c,0x1e]
251
252 # CHECK: vbrsr.8 q0, q4, r8 @ encoding: [0x09,0xfe,0x68,0x1e]
253 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
254 [0x09,0xfe,0x68,0x1e]
255
256 # CHECK: vbrsr.16 q0, q1, r1 @ encoding: [0x13,0xfe,0x61,0x1e]
257 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
258 [0x13,0xfe,0x61,0x1e]
259
260 # CHECK: vbrsr.32 q0, q6, r0 @ encoding: [0x2d,0xfe,0x60,0x1e]
261 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
262 [0x2d,0xfe,0x60,0x1e]
263
264 # CHECK: vmul.i8 q0, q0, r12 @ encoding: [0x01,0xee,0x6c,0x1e]
265 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
266 [0x01,0xee,0x6c,0x1e]
267
268 # CHECK: vmul.i16 q0, q4, r7 @ encoding: [0x19,0xee,0x67,0x1e]
269 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
270 [0x19,0xee,0x67,0x1e]
271
272 # CHECK: vmul.i32 q0, q1, r11 @ encoding: [0x23,0xee,0x6b,0x1e]
273 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
274 [0x23,0xee,0x6b,0x1e]
275
276 # CHECK: vmul.f16 q0, q0, r10 @ encoding: [0x31,0xfe,0x6a,0x0e]
277 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
278 [0x31,0xfe,0x6a,0x0e]
279
280 # CHECK: vmul.f32 q0, q1, r7 @ encoding: [0x33,0xee,0x67,0x0e]
281 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
282 [0x33,0xee,0x67,0x0e]
283
284 # CHECK: vqdmulh.s8 q0, q1, r6 @ encoding: [0x03,0xee,0x66,0x0e]
285 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
286 [0x03,0xee,0x66,0x0e]
287
288 # CHECK: vqdmulh.s16 q0, q2, r2 @ encoding: [0x15,0xee,0x62,0x0e]
289 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
290 [0x15,0xee,0x62,0x0e]
291
292 # CHECK: vqdmulh.s32 q1, q3, r8 @ encoding: [0x27,0xee,0x68,0x2e]
293 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
294 [0x27,0xee,0x68,0x2e]
295
296 # CHECK: vqrdmulh.s8 q0, q2, r6 @ encoding: [0x05,0xfe,0x66,0x0e]
297 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
298 [0x05,0xfe,0x66,0x0e]
299
300 # CHECK: vqrdmulh.s16 q0, q0, r2 @ encoding: [0x11,0xfe,0x62,0x0e]
301 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
302 [0x11,0xfe,0x62,0x0e]
303
304 # CHECK: vqrdmulh.s32 q0, q0, r2 @ encoding: [0x21,0xfe,0x62,0x0e]
305 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
306 [0x21,0xfe,0x62,0x0e]
307
308 # CHECK: vfmas.f16 q0, q0, r12 @ encoding: [0x31,0xfe,0x4c,0x1e]
309 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
310 [0x31,0xfe,0x4c,0x1e]
311
312 # CHECK: vfmas.f32 q0, q3, lr @ encoding: [0x37,0xee,0x4e,0x1e]
313 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
314 [0x37,0xee,0x4e,0x1e]
315
316 # CHECK: vmlas.s8 q0, q0, r6 @ encoding: [0x01,0xee,0x46,0x1e]
317 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
318 [0x01,0xee,0x46,0x1e]
319
320 # CHECK: vmlas.s16 q0, q2, r9 @ encoding: [0x15,0xee,0x49,0x1e]
321 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
322 [0x15,0xee,0x49,0x1e]
323
324 # CHECK: vmlas.s32 q0, q7, r6 @ encoding: [0x2f,0xee,0x46,0x1e]
325 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
326 [0x2f,0xee,0x46,0x1e]
327
328 # CHECK: vmlas.u8 q0, q5, lr @ encoding: [0x0b,0xfe,0x4e,0x1e]
329 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
330 [0x0b,0xfe,0x4e,0x1e]
331
332 # CHECK: vmlas.u16 q0, q3, r12 @ encoding: [0x17,0xfe,0x4c,0x1e]
333 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
334 [0x17,0xfe,0x4c,0x1e]
335
336 # CHECK: vmlas.u32 q1, q1, r11 @ encoding: [0x23,0xfe,0x4b,0x3e]
337 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
338 [0x23,0xfe,0x4b,0x3e]
339
340 # CHECK: vfma.f16 q1, q1, r6 @ encoding: [0x33,0xfe,0x46,0x2e]
341 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
342 [0x33,0xfe,0x46,0x2e]
343
344 # CHECK: vfmas.f32 q7, q4, r6 @ encoding: [0x39,0xee,0x46,0xfe]
345 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
346 [0x39,0xee,0x46,0xfe]
347
348 # CHECK: vmla.s8 q0, q3, r8 @ encoding: [0x07,0xee,0x48,0x0e]
349 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
350 [0x07,0xee,0x48,0x0e]
351
352 # CHECK: vmla.s16 q1, q3, r10 @ encoding: [0x17,0xee,0x4a,0x2e]
353 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
354 [0x17,0xee,0x4a,0x2e]
355
356 # CHECK: vmla.s32 q1, q3, r1 @ encoding: [0x27,0xee,0x41,0x2e]
357 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
358 [0x27,0xee,0x41,0x2e]
359
360 # CHECK: vmla.u8 q0, q7, r10 @ encoding: [0x0f,0xfe,0x4a,0x0e]
361 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
362 [0x0f,0xfe,0x4a,0x0e]
363
364 # CHECK: vmla.u16 q0, q0, r7 @ encoding: [0x11,0xfe,0x47,0x0e]
365 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
366 [0x11,0xfe,0x47,0x0e]
367
368 # CHECK: vmla.u32 q1, q6, r10 @ encoding: [0x2d,0xfe,0x4a,0x2e]
369 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
370 [0x2d,0xfe,0x4a,0x2e]
371
372 # CHECK: vqdmlash.s8 q0, q0, r5 @ encoding: [0x00,0xee,0x65,0x1e]
373 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
374 [0x00,0xee,0x65,0x1e]
375
376 # CHECK: vqdmlash.s16 q0, q5, lr @ encoding: [0x1a,0xee,0x6e,0x1e]
377 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
378 [0x1a,0xee,0x6e,0x1e]
379
380 # CHECK: vqdmlash.s32 q0, q2, r3 @ encoding: [0x24,0xee,0x63,0x1e]
381 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
382 [0x24,0xee,0x63,0x1e]
383
384 # CHECK: vqdmlash.u8 q0, q4, r2 @ encoding: [0x08,0xfe,0x62,0x1e]
385 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
386 [0x08,0xfe,0x62,0x1e]
387
388 # CHECK: vqdmlash.u16 q1, q4, r2 @ encoding: [0x18,0xfe,0x62,0x3e]
389 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
390 [0x18,0xfe,0x62,0x3e]
391
392 # CHECK: vqdmlash.u32 q1, q5, r0 @ encoding: [0x2a,0xfe,0x60,0x3e]
393 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
394 [0x2a,0xfe,0x60,0x3e]
395
396 # CHECK: vqdmlah.s8 q0, q3, r3 @ encoding: [0x06,0xee,0x63,0x0e]
397 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
398 [0x06,0xee,0x63,0x0e]
399
400 # CHECK: vqdmlah.s16 q5, q3, r9 @ encoding: [0x16,0xee,0x69,0xae]
401 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
402 [0x16,0xee,0x69,0xae]
403
404 # CHECK: vqdmlah.s32 q0, q1, r11 @ encoding: [0x22,0xee,0x6b,0x0e]
405 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
406 [0x22,0xee,0x6b,0x0e]
407
408 # CHECK: vqdmlah.u8 q0, q2, lr @ encoding: [0x04,0xfe,0x6e,0x0e]
409 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
410 [0x04,0xfe,0x6e,0x0e]
411
412 # CHECK: vqdmlah.u16 q0, q3, r10 @ encoding: [0x16,0xfe,0x6a,0x0e]
413 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
414 [0x16,0xfe,0x6a,0x0e]
415
416 # CHECK: vqdmlah.u32 q1, q5, r2 @ encoding: [0x2a,0xfe,0x62,0x2e]
417 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
418 [0x2a,0xfe,0x62,0x2e]
419
420 # CHECK: vqrdmlash.s8 q0, q5, r10 @ encoding: [0x0a,0xee,0x4a,0x1e]
421 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
422 [0x0a,0xee,0x4a,0x1e]
423
424 # CHECK: vqrdmlash.s16 q0, q3, r2 @ encoding: [0x16,0xee,0x42,0x1e]
425 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
426 [0x16,0xee,0x42,0x1e]
427
428 # CHECK: vqrdmlash.s32 q0, q0, r4 @ encoding: [0x20,0xee,0x44,0x1e]
429 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
430 [0x20,0xee,0x44,0x1e]
431
432 # CHECK: vqrdmlash.u8 q0, q4, r9 @ encoding: [0x08,0xfe,0x49,0x1e]
433 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
434 [0x08,0xfe,0x49,0x1e]
435
436 # CHECK: vqrdmlash.u16 q0, q6, r12 @ encoding: [0x1c,0xfe,0x4c,0x1e]
437 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
438 [0x1c,0xfe,0x4c,0x1e]
439
440 # CHECK: vqrdmlash.u32 q0, q3, r7 @ encoding: [0x26,0xfe,0x47,0x1e]
441 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
442 [0x26,0xfe,0x47,0x1e]
443
444 # CHECK: vqrdmlah.s8 q0, q5, r11 @ encoding: [0x0a,0xee,0x4b,0x0e]
445 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
446 [0x0a,0xee,0x4b,0x0e]
447
448 # CHECK: vqrdmlah.s16 q0, q2, r10 @ encoding: [0x14,0xee,0x4a,0x0e]
449 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
450 [0x14,0xee,0x4a,0x0e]
451
452 # CHECK: vqrdmlah.s32 q0, q4, r11 @ encoding: [0x28,0xee,0x4b,0x0e]
453 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
454 [0x28,0xee,0x4b,0x0e]
455
456 # CHECK: vqrdmlah.u8 q0, q4, r2 @ encoding: [0x08,0xfe,0x42,0x0e]
457 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
458 [0x08,0xfe,0x42,0x0e]
459
460 # CHECK: vqrdmlah.u16 q0, q6, r1 @ encoding: [0x1c,0xfe,0x41,0x0e]
461 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
462 [0x1c,0xfe,0x41,0x0e]
463
464 # CHECK: vqrdmlah.u32 q0, q4, r2 @ encoding: [0x28,0xfe,0x42,0x0e]
465 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
466 [0x28,0xfe,0x42,0x0e]
467
468 # CHECK: viwdup.u8 q0, lr, r1, #1 @ encoding: [0x0f,0xee,0x60,0x0f]
469 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
470 [0x0f,0xee,0x60,0x0f]
471
472 # CHECK: viwdup.u16 q1, r10, r1, #8 @ encoding: [0x1b,0xee,0xe1,0x2f]
473 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
474 [0x1b,0xee,0xe1,0x2f]
475
476 # CHECK: viwdup.u32 q6, r10, r5, #4 @ encoding: [0x2b,0xee,0xe4,0xcf]
477 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
478 [0x2b,0xee,0xe4,0xcf]
479
480 # CHECK: vdwdup.u8 q0, r12, r11, #8 @ encoding: [0x0d,0xee,0xeb,0x1f]
481 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
482 [0x0d,0xee,0xeb,0x1f]
483
484 # CHECK: vdwdup.u16 q0, r12, r1, #2 @ encoding: [0x1d,0xee,0x61,0x1f]
485 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
486 [0x1d,0xee,0x61,0x1f]
487
488 # CHECK: vdwdup.u32 q0, r0, r7, #8 @ encoding: [0x21,0xee,0xe7,0x1f]
489 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
490 [0x21,0xee,0xe7,0x1f]
491
492 # CHECK: vidup.u8 q0, lr, #2 @ encoding: [0x0f,0xee,0x6f,0x0f]
493 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
494 [0x0f,0xee,0x6f,0x0f]
495
496 # CHECK: vidup.u16 q0, lr, #4 @ encoding: [0x1f,0xee,0xee,0x0f]
497 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
498 [0x1f,0xee,0xee,0x0f]
499
500 # CHECK: vidup.u32 q0, r12, #1 @ encoding: [0x2d,0xee,0x6e,0x0f]
501 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
502 [0x2d,0xee,0x6e,0x0f]
503
504 # CHECK: vddup.u8 q0, r4, #4 @ encoding: [0x05,0xee,0xee,0x1f]
505 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
506 [0x05,0xee,0xee,0x1f]
507
508 # CHECK: vddup.u16 q0, r10, #4 @ encoding: [0x1b,0xee,0xee,0x1f]
509 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
510 [0x1b,0xee,0xee,0x1f]
511
512 # CHECK: vddup.u32 q2, r0, #8 @ encoding: [0x21,0xee,0xef,0x5f]
513 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
514 [0x21,0xee,0xef,0x5f]
515
516 # CHECK: vctp.8 lr @ encoding: [0x0e,0xf0,0x01,0xe8]
517 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
518 [0x0e,0xf0,0x01,0xe8]
519
520 # CHECK: vctp.16 r0 @ encoding: [0x10,0xf0,0x01,0xe8]
521 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
522 [0x10,0xf0,0x01,0xe8]
523
524 # CHECK: vctp.32 r10 @ encoding: [0x2a,0xf0,0x01,0xe8]
525 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
526 [0x2a,0xf0,0x01,0xe8]
527
528 # CHECK: vctp.64 r1 @ encoding: [0x31,0xf0,0x01,0xe8]
529 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
530 [0x31,0xf0,0x01,0xe8]