llvm.org GIT mirror llvm / 4db3cff
Hide the call to InitMCInstrInfo into tblgen generated ctor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 8 years ago
29 changed file(s) with 117 addition(s) and 59 deletion(s). Raw diff Collapse all Expand all
4343 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
4444 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
4545 public:
46 TargetInstrInfo(const MCInstrDesc *desc, unsigned NumOpcodes,
47 int CallFrameSetupOpcode = -1,
48 int CallFrameDestroyOpcode = -1);
46 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1)
47 : CallFrameSetupOpcode(CFSetupOpcode),
48 CallFrameDestroyOpcode(CFDestroyOpcode) {
49 }
50
4951 virtual ~TargetInstrInfo();
5052
5153 /// getRegClass - Givem a machine instruction descriptor, returns the register
677679 /// libcodegen, not in libtarget.
678680 class TargetInstrInfoImpl : public TargetInstrInfo {
679681 protected:
680 TargetInstrInfoImpl(const MCInstrDesc *desc, unsigned NumOpcodes,
681 int CallFrameSetupOpcode = -1,
682 TargetInstrInfoImpl(int CallFrameSetupOpcode = -1,
682683 int CallFrameDestroyOpcode = -1)
683 : TargetInstrInfo(desc, NumOpcodes,
684 CallFrameSetupOpcode, CallFrameDestroyOpcode) {}
684 : TargetInstrInfo(CallFrameSetupOpcode, CallFrameDestroyOpcode) {}
685685 public:
686686 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
687687 MachineBasicBlock *NewDest) const;
3535 #include "llvm/ADT/STLExtras.h"
3636
3737 #define GET_INSTRINFO_MC_DESC
38 #define GET_INSTRINFO_CTOR
3839 #include "ARMGenInstrInfo.inc"
3940
4041 using namespace llvm;
7677 };
7778
7879 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
79 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts),
80 ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
80 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
8181 Subtarget(STI) {
8282 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
8383 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
1818 #include "llvm/Target/TargetInstrInfo.h"
1919 #include "llvm/ADT/DenseMap.h"
2020 #include "llvm/ADT/SmallSet.h"
21
22 #define GET_INSTRINFO_HEADER
23 #include "ARMGenInstrInfo.inc"
2124
2225 namespace llvm {
2326 class ARMSubtarget;
171174 };
172175 }
173176
174 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
177 class ARMBaseInstrInfo : public ARMGenInstrInfo {
175178 const ARMSubtarget &Subtarget;
176179
177180 protected:
2020 #include "llvm/Support/ErrorHandling.h"
2121
2222 #define GET_INSTRINFO_MC_DESC
23 #define GET_INSTRINFO_CTOR
2324 #include "AlphaGenInstrInfo.inc"
2425 using namespace llvm;
2526
2627 AlphaInstrInfo::AlphaInstrInfo()
27 : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts),
28 Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
29 RI(*this) { }
28 : AlphaGenInstrInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
29 RI(*this) {
30 }
3031
3132
3233 unsigned
1616 #include "llvm/Target/TargetInstrInfo.h"
1717 #include "AlphaRegisterInfo.h"
1818
19 #define GET_INSTRINFO_HEADER
20 #include "AlphaGenInstrInfo.inc"
21
1922 namespace llvm {
2023
21 class AlphaInstrInfo : public TargetInstrInfoImpl {
24 class AlphaInstrInfo : public AlphaGenInstrInfo {
2225 const AlphaRegisterInfo RI;
2326 public:
2427 AlphaInstrInfo();
1919 #include "llvm/CodeGen/MachineInstrBuilder.h"
2020 #include "llvm/Support/ErrorHandling.h"
2121
22 #define GET_INSTRINFO_CTOR
2223 #define GET_INSTRINFO_MC_DESC
2324 #include "BlackfinGenInstrInfo.inc"
2425
2526 using namespace llvm;
2627
2728 BlackfinInstrInfo::BlackfinInstrInfo(BlackfinSubtarget &ST)
28 : TargetInstrInfoImpl(BlackfinInsts, array_lengthof(BlackfinInsts),
29 BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
29 : BlackfinGenInstrInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
3030 RI(ST, *this),
3131 Subtarget(ST) {}
3232
1616 #include "llvm/Target/TargetInstrInfo.h"
1717 #include "BlackfinRegisterInfo.h"
1818
19 #define GET_INSTRINFO_HEADER
20 #include "BlackfinGenInstrInfo.inc"
21
1922 namespace llvm {
2023
21 class BlackfinInstrInfo : public TargetInstrInfoImpl {
24 class BlackfinInstrInfo : public BlackfinGenInstrInfo {
2225 const BlackfinRegisterInfo RI;
2326 const BlackfinSubtarget& Subtarget;
2427 public:
2121 #include "llvm/Support/raw_ostream.h"
2222 #include "llvm/MC/MCContext.h"
2323
24 #define GET_INSTRINFO_CTOR
2425 #define GET_INSTRINFO_MC_DESC
2526 #include "SPUGenInstrInfo.inc"
2627
5253 }
5354
5455 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
55 : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0]),
56 SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
56 : SPUGenInstrInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
5757 TM(tm),
5858 RI(*TM.getSubtargetImpl(), *this)
5959 { /* NOP */ }
1717 #include "llvm/Target/TargetInstrInfo.h"
1818 #include "SPURegisterInfo.h"
1919
20 #define GET_INSTRINFO_HEADER
21 #include "SPUGenInstrInfo.inc"
22
2023 namespace llvm {
2124 //! Cell SPU instruction information class
22 class SPUInstrInfo : public TargetInstrInfoImpl {
25 class SPUInstrInfo : public SPUGenInstrInfo {
2326 SPUTargetMachine &TM;
2427 const SPURegisterInfo RI;
2528 public:
2020 #include "llvm/Support/CommandLine.h"
2121 #include "llvm/Support/ErrorHandling.h"
2222
23 #define GET_INSTRINFO_CTOR
2324 #define GET_INSTRINFO_MC_DESC
2425 #include "MBlazeGenInstrInfo.inc"
2526
2627 using namespace llvm;
2728
2829 MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm)
29 : TargetInstrInfoImpl(MBlazeInsts, array_lengthof(MBlazeInsts),
30 MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
30 : MBlazeGenInstrInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
3131 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
3232
3333 static bool isZeroImm(const MachineOperand &op) {
1717 #include "llvm/Support/ErrorHandling.h"
1818 #include "llvm/Target/TargetInstrInfo.h"
1919 #include "MBlazeRegisterInfo.h"
20
21 #define GET_INSTRINFO_HEADER
22 #include "MBlazeGenInstrInfo.inc"
2023
2124 namespace llvm {
2225
218221 };
219222 }
220223
221 class MBlazeInstrInfo : public TargetInstrInfoImpl {
224 class MBlazeInstrInfo : public MBlazeGenInstrInfo {
222225 MBlazeTargetMachine &TM;
223226 const MBlazeRegisterInfo RI;
224227 public:
2121 #include "llvm/CodeGen/PseudoSourceValue.h"
2222 #include "llvm/Support/ErrorHandling.h"
2323
24 #define GET_INSTRINFO_CTOR
2425 #define GET_INSTRINFO_MC_DESC
2526 #include "MSP430GenInstrInfo.inc"
2627
2728 using namespace llvm;
2829
2930 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
30 : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts),
31 MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
31 : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
3232 RI(tm, *this), TM(tm) {}
3333
3434 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1515
1616 #include "llvm/Target/TargetInstrInfo.h"
1717 #include "MSP430RegisterInfo.h"
18
19 #define GET_INSTRINFO_HEADER
20 #include "MSP430GenInstrInfo.inc"
1821
1922 namespace llvm {
2023
3639 };
3740 }
3841
39 class MSP430InstrInfo : public TargetInstrInfoImpl {
42 class MSP430InstrInfo : public MSP430GenInstrInfo {
4043 const MSP430RegisterInfo RI;
4144 MSP430TargetMachine &TM;
4245 public:
1818 #include "llvm/CodeGen/MachineRegisterInfo.h"
1919 #include "llvm/Support/ErrorHandling.h"
2020
21 #define GET_INSTRINFO_CTOR
2122 #define GET_INSTRINFO_MC_DESC
2223 #include "MipsGenInstrInfo.inc"
2324
2425 using namespace llvm;
2526
2627 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
27 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts),
28 Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
28 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
2929 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
3030
3131 static bool isZeroImm(const MachineOperand &op) {
1717 #include "llvm/Support/ErrorHandling.h"
1818 #include "llvm/Target/TargetInstrInfo.h"
1919 #include "MipsRegisterInfo.h"
20
21 #define GET_INSTRINFO_HEADER
22 #include "MipsGenInstrInfo.inc"
2023
2124 namespace llvm {
2225
163166 };
164167 }
165168
166 class MipsInstrInfo : public TargetInstrInfoImpl {
169 class MipsInstrInfo : public MipsGenInstrInfo {
167170 MipsTargetMachine &TM;
168171 const MipsRegisterInfo RI;
169172 public:
2020 #include "llvm/Support/Debug.h"
2121 #include "llvm/Support/raw_ostream.h"
2222
23 #define GET_INSTRINFO_CTOR
2324 #define GET_INSTRINFO_MC_DESC
2425 #include "PTXGenInstrInfo.inc"
2526
2627 using namespace llvm;
2728
2829 PTXInstrInfo::PTXInstrInfo(PTXTargetMachine &_TM)
29 : TargetInstrInfoImpl(PTXInsts, array_lengthof(PTXInsts)),
30 : PTXGenInstrInfo(),
3031 RI(_TM, *this), TM(_TM) {}
3132
3233 static const struct map_entry {
1616 #include "PTXRegisterInfo.h"
1717 #include "llvm/Target/TargetInstrInfo.h"
1818
19 #define GET_INSTRINFO_HEADER
20 #include "PTXGenInstrInfo.inc"
21
1922 namespace llvm {
2023 class PTXTargetMachine;
2124
2326 class SDValue;
2427 class SelectionDAG;
2528
26 class PTXInstrInfo : public TargetInstrInfoImpl {
29 class PTXInstrInfo : public PTXGenInstrInfo {
2730 private:
2831 const PTXRegisterInfo RI;
2932 PTXTargetMachine &TM;
2727 #include "llvm/Support/raw_ostream.h"
2828 #include "llvm/MC/MCAsmInfo.h"
2929
30 #define GET_INSTRINFO_CTOR
3031 #define GET_INSTRINFO_MC_DESC
3132 #include "PPCGenInstrInfo.inc"
3233
3839 using namespace llvm;
3940
4041 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
41 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts),
42 PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
42 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
4343 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
4444
4545 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
1616 #include "PPC.h"
1717 #include "llvm/Target/TargetInstrInfo.h"
1818 #include "PPCRegisterInfo.h"
19
20 #define GET_INSTRINFO_HEADER
21 #include "PPCGenInstrInfo.inc"
1922
2023 namespace llvm {
2124
6063 } // end namespace PPCII
6164
6265
63 class PPCInstrInfo : public TargetInstrInfoImpl {
66 class PPCInstrInfo : public PPCGenInstrInfo {
6467 PPCTargetMachine &TM;
6568 const PPCRegisterInfo RI;
6669
2020 #include "llvm/Support/ErrorHandling.h"
2121 #include "SparcMachineFunctionInfo.h"
2222
23 #define GET_INSTRINFO_CTOR
2324 #define GET_INSTRINFO_MC_DESC
2425 #include "SparcGenInstrInfo.inc"
2526
2627 using namespace llvm;
2728
2829 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
29 : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts),
30 SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
3131 RI(ST, *this), Subtarget(ST) {
3232 }
3333
1616 #include "llvm/Target/TargetInstrInfo.h"
1717 #include "SparcRegisterInfo.h"
1818
19 #define GET_INSTRINFO_HEADER
20 #include "SparcGenInstrInfo.inc"
21
1922 namespace llvm {
2023
2124 /// SPII - This namespace holds all of the target specific flags that
3033 };
3134 }
3235
33 class SparcInstrInfo : public TargetInstrInfoImpl {
36 class SparcInstrInfo : public SparcGenInstrInfo {
3437 const SparcRegisterInfo RI;
3538 const SparcSubtarget& Subtarget;
3639 public:
2222 #include "llvm/CodeGen/PseudoSourceValue.h"
2323 #include "llvm/Support/ErrorHandling.h"
2424
25 #define GET_INSTRINFO_CTOR
2526 #define GET_INSTRINFO_MC_DESC
2627 #include "SystemZGenInstrInfo.inc"
2728
2829 using namespace llvm;
2930
3031 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
31 : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts),
32 SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
32 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
3333 RI(tm, *this), TM(tm) {
3434 }
3535
1717 #include "SystemZRegisterInfo.h"
1818 #include "llvm/ADT/IndexedMap.h"
1919 #include "llvm/Target/TargetInstrInfo.h"
20
21 #define GET_INSTRINFO_HEADER
22 #include "SystemZGenInstrInfo.inc"
2023
2124 namespace llvm {
2225
4649 };
4750 }
4851
49 class SystemZInstrInfo : public TargetInstrInfoImpl {
52 class SystemZInstrInfo : public SystemZGenInstrInfo {
5053 const SystemZRegisterInfo RI;
5154 SystemZTargetMachine &TM;
5255 public:
2222 //===----------------------------------------------------------------------===//
2323 // TargetInstrInfo
2424 //===----------------------------------------------------------------------===//
25
26 TargetInstrInfo::TargetInstrInfo(const MCInstrDesc* Desc, unsigned numOpcodes,
27 int CFSetupOpcode, int CFDestroyOpcode)
28 : CallFrameSetupOpcode(CFSetupOpcode),
29 CallFrameDestroyOpcode(CFDestroyOpcode) {
30 InitMCInstrInfo(Desc, numOpcodes);
31 }
3225
3326 TargetInstrInfo::~TargetInstrInfo() {
3427 }
3434 #include "llvm/MC/MCAsmInfo.h"
3535 #include
3636
37 #define GET_INSTRINFO_CTOR
3738 #define GET_INSTRINFO_MC_DESC
3839 #include "X86GenInstrInfo.inc"
3940
5354 cl::init(false), cl::Hidden);
5455
5556 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
56 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts),
57 (tm.getSubtarget().is64Bit()
58 ? X86::ADJCALLSTACKDOWN64
59 : X86::ADJCALLSTACKDOWN32),
60 (tm.getSubtarget().is64Bit()
61 ? X86::ADJCALLSTACKUP64
62 : X86::ADJCALLSTACKUP32)),
57 : X86GenInstrInfo((tm.getSubtarget().is64Bit()
58 ? X86::ADJCALLSTACKDOWN64
59 : X86::ADJCALLSTACKDOWN32),
60 (tm.getSubtarget().is64Bit()
61 ? X86::ADJCALLSTACKUP64
62 : X86::ADJCALLSTACKUP32)),
6363 TM(tm), RI(tm, *this) {
6464 enum {
6565 TB_NOT_REVERSABLE = 1U << 31,
1717 #include "X86.h"
1818 #include "X86RegisterInfo.h"
1919 #include "llvm/ADT/DenseMap.h"
20
21 #define GET_INSTRINFO_HEADER
22 #include "X86GenInstrInfo.inc"
2023
2124 namespace llvm {
2225 class X86RegisterInfo;
610613 isLeaMem(MI, Op);
611614 }
612615
613 class X86InstrInfo : public TargetInstrInfoImpl {
616 class X86InstrInfo : public X86GenInstrInfo {
614617 X86TargetMachine &TM;
615618 const X86RegisterInfo RI;
616619
2121 #include "llvm/Support/Debug.h"
2222 #include "llvm/Support/ErrorHandling.h"
2323
24 #define GET_INSTRINFO_CTOR
2425 #define GET_INSTRINFO_MC_DESC
2526 #include "XCoreGenInstrInfo.inc"
2627
3940 using namespace llvm;
4041
4142 XCoreInstrInfo::XCoreInstrInfo()
42 : TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts),
43 XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
43 : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
4444 RI(*this) {
4545 }
4646
1616 #include "llvm/Target/TargetInstrInfo.h"
1717 #include "XCoreRegisterInfo.h"
1818
19 #define GET_INSTRINFO_HEADER
20 #include "XCoreGenInstrInfo.inc"
21
1922 namespace llvm {
2023
21 class XCoreInstrInfo : public TargetInstrInfoImpl {
24 class XCoreInstrInfo : public XCoreGenInstrInfo {
2225 const XCoreRegisterInfo RI;
2326 public:
2427 XCoreInstrInfo();
207207 OperandInfoIDs, OS);
208208 OS << "};\n\n";
209209
210
211210 // MCInstrInfo initialization routine.
212211 OS << "static inline void Init" << TargetName
213212 << "MCInstrInfo(MCInstrInfo *II) {\n";
217216 OS << "} // End llvm namespace \n";
218217
219218 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
219
220 // Create a TargetInstrInfo subclass to hide the MC layer initialization.
221 OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
222 OS << "#undef GET_INSTRINFO_HEADER\n";
223
224 std::string ClassName = TargetName + "GenInstrInfo";
225 OS << "namespace llvm {\n\n";
226 OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n"
227 << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
228 << "};\n";
229 OS << "} // End llvm namespace \n";
230
231 OS << "#endif // GET_INSTRINFO_HEADER\n\n";
232
233 OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
234 OS << "#undef GET_INSTRINFO_CTOR\n";
235
236 OS << "namespace llvm {\n\n";
237 OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
238 << " : TargetInstrInfoImpl(SO, DO) {\n"
239 << " InitMCInstrInfo(" << TargetName << "Insts, "
240 << NumberedInstructions.size() << ");\n}\n";
241 OS << "} // End llvm namespace \n";
242
243 OS << "#endif // GET_INSTRINFO_CTOR\n\n";
220244 }
221245
222246 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,