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[CodeGenPrep] Skip merging empty case blocks This is recommit of r287553 after fixing the invalid loop info after eliminating an empty block and unit test failures in AVR and WebAssembly : Summary: Merging an empty case block into the header block of switch could cause ISel to add COPY instructions in the header of switch, instead of the case block, if the case block is used as an incoming block of a PHI. This could potentially increase dynamic instructions, especially when the switch is in a loop. I added a test case which was reduced from the benchmark I was targetting. Reviewers: t.p.northover, mcrosier, manmanren, wmi, joerg, davidxl Subscribers: joerg, qcolombet, danielcdh, hfinkel, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D22696 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289988 91177308-0d34-0410-b5e6-96231b3b80d8 Jun Bum Lim 3 years ago
8 changed file(s) with 355 addition(s) and 48 deletion(s). Raw diff Collapse all Expand all
1616 #include "llvm/ADT/DenseMap.h"
1717 #include "llvm/ADT/SmallSet.h"
1818 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/BlockFrequencyInfo.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
1921 #include "llvm/Analysis/InstructionSimplify.h"
2022 #include "llvm/Analysis/LoopInfo.h"
2123 #include "llvm/Analysis/ProfileSummaryInfo.h"
123125 "profile-guided-section-prefix", cl::Hidden, cl::init(true),
124126 cl::desc("Use profile info to add section prefix for hot/cold functions"));
125127
128 static cl::opt FreqRatioToSkipMerge(
129 "cgp-freq-ratio-to-skip-merge", cl::Hidden, cl::init(2),
130 cl::desc("Skip merging empty blocks if (frequency of empty block) / "
131 "(frequency of destination block) is greater than this ratio"));
132
126133 namespace {
127134 typedef SmallPtrSet SetOfInstrs;
128135 typedef PointerIntPair TypeIsSExt;
135142 const TargetTransformInfo *TTI;
136143 const TargetLibraryInfo *TLInfo;
137144 const LoopInfo *LI;
145 std::unique_ptr BFI;
146 std::unique_ptr BPI;
138147
139148 /// As we scan instructions optimizing them, this is the next instruction
140149 /// to optimize. Transforms that can invalidate this should update it.
181190 private:
182191 bool eliminateFallThrough(Function &F);
183192 bool eliminateMostlyEmptyBlocks(Function &F);
193 BasicBlock *findDestBlockOfMergeableEmptyBlock(BasicBlock *BB);
184194 bool canMergeBlocks(const BasicBlock *BB, const BasicBlock *DestBB) const;
185195 void eliminateMostlyEmptyBlock(BasicBlock *BB);
196 bool isMergingEmptyBlockProfitable(BasicBlock *BB, BasicBlock *DestBB,
197 bool isPreheader);
186198 bool optimizeBlock(BasicBlock &BB, bool& ModifiedDT);
187199 bool optimizeInst(Instruction *I, bool& ModifiedDT);
188200 bool optimizeMemoryInst(Instruction *I, Value *Addr,
229241 // Clear per function information.
230242 InsertedInsts.clear();
231243 PromotedInsts.clear();
244 BFI.reset();
245 BPI.reset();
232246
233247 ModifiedDT = false;
234248 if (TM)
381395 return Changed;
382396 }
383397
398 /// Find a destination block from BB if BB is mergeable empty block.
399 BasicBlock *CodeGenPrepare::findDestBlockOfMergeableEmptyBlock(BasicBlock *BB) {
400 // If this block doesn't end with an uncond branch, ignore it.
401 BranchInst *BI = dyn_cast(BB->getTerminator());
402 if (!BI || !BI->isUnconditional())
403 return nullptr;
404
405 // If the instruction before the branch (skipping debug info) isn't a phi
406 // node, then other stuff is happening here.
407 BasicBlock::iterator BBI = BI->getIterator();
408 if (BBI != BB->begin()) {
409 --BBI;
410 while (isa(BBI)) {
411 if (BBI == BB->begin())
412 break;
413 --BBI;
414 }
415 if (!isa(BBI) && !isa(BBI))
416 return nullptr;
417 }
418
419 // Do not break infinite loops.
420 BasicBlock *DestBB = BI->getSuccessor(0);
421 if (DestBB == BB)
422 return nullptr;
423
424 if (!canMergeBlocks(BB, DestBB))
425 DestBB = nullptr;
426
427 return DestBB;
428 }
429
384430 /// Eliminate blocks that contain only PHI nodes, debug info directives, and an
385431 /// unconditional branch. Passes before isel (e.g. LSR/loopsimplify) often split
386432 /// edges in ways that are non-optimal for isel. Start by eliminating these
399445 // Note that this intentionally skips the entry block.
400446 for (Function::iterator I = std::next(F.begin()), E = F.end(); I != E;) {
401447 BasicBlock *BB = &*I++;
402
403 // If this block doesn't end with an uncond branch, ignore it.
404 BranchInst *BI = dyn_cast(BB->getTerminator());
405 if (!BI || !BI->isUnconditional())
448 BasicBlock *DestBB = findDestBlockOfMergeableEmptyBlock(BB);
449 if (!DestBB ||
450 !isMergingEmptyBlockProfitable(BB, DestBB, Preheaders.count(BB)))
406451 continue;
407
408 // If the instruction before the branch (skipping debug info) isn't a phi
409 // node, then other stuff is happening here.
410 BasicBlock::iterator BBI = BI->getIterator();
411 if (BBI != BB->begin()) {
412 --BBI;
413 while (isa(BBI)) {
414 if (BBI == BB->begin())
415 break;
416 --BBI;
417 }
418 if (!isa(BBI) && !isa(BBI))
419 continue;
420 }
421
422 // Do not break infinite loops.
423 BasicBlock *DestBB = BI->getSuccessor(0);
424 if (DestBB == BB)
425 continue;
426
427 if (!canMergeBlocks(BB, DestBB))
428 continue;
429
430 // Do not delete loop preheaders if doing so would create a critical edge.
431 // Loop preheaders can be good locations to spill registers. If the
432 // preheader is deleted and we create a critical edge, registers may be
433 // spilled in the loop body instead.
434 if (!DisablePreheaderProtect && Preheaders.count(BB) &&
435 !(BB->getSinglePredecessor() && BB->getSinglePredecessor()->getSingleSuccessor()))
436 continue;
437452
438453 eliminateMostlyEmptyBlock(BB);
439454 MadeChange = true;
440455 }
441456 return MadeChange;
457 }
458
459 bool CodeGenPrepare::isMergingEmptyBlockProfitable(BasicBlock *BB,
460 BasicBlock *DestBB,
461 bool isPreheader) {
462 // Do not delete loop preheaders if doing so would create a critical edge.
463 // Loop preheaders can be good locations to spill registers. If the
464 // preheader is deleted and we create a critical edge, registers may be
465 // spilled in the loop body instead.
466 if (!DisablePreheaderProtect && isPreheader &&
467 !(BB->getSinglePredecessor() &&
468 BB->getSinglePredecessor()->getSingleSuccessor()))
469 return false;
470
471 // Try to skip merging if the unique predecessor of BB is terminated by a
472 // switch or indirect branch instruction, and BB is used as an incoming block
473 // of PHIs in DestBB. In such case, merging BB and DestBB would cause ISel to
474 // add COPY instructions in the predecessor of BB instead of BB (if it is not
475 // merged). Note that the critical edge created by merging such blocks wont be
476 // split in MachineSink because the jump table is not analyzable. By keeping
477 // such empty block (BB), ISel will place COPY instructions in BB, not in the
478 // predecessor of BB.
479 BasicBlock *Pred = BB->getUniquePredecessor();
480 if (!Pred ||
481 !(isa(Pred->getTerminator()) ||
482 isa(Pred->getTerminator())))
483 return true;
484
485 if (BB->getTerminator() != BB->getFirstNonPHI())
486 return true;
487
488 // We use a simple cost heuristic which determine skipping merging is
489 // profitable if the cost of skipping merging is less than the cost of
490 // merging : Cost(skipping merging) < Cost(merging BB), where the
491 // Cost(skipping merging) is Freq(BB) * (Cost(Copy) + Cost(Branch)), and
492 // the Cost(merging BB) is Freq(Pred) * Cost(Copy).
493 // Assuming Cost(Copy) == Cost(Branch), we could simplify it to :
494 // Freq(Pred) / Freq(BB) > 2.
495 // Note that if there are multiple empty blocks sharing the same incoming
496 // value for the PHIs in the DestBB, we consider them together. In such
497 // case, Cost(merging BB) will be the sum of their frequencies.
498
499 if (!isa(DestBB->begin()))
500 return true;
501
502 SmallPtrSet SameIncomingValueBBs;
503
504 // Find all other incoming blocks from which incoming values of all PHIs in
505 // DestBB are the same as the ones from BB.
506 for (pred_iterator PI = pred_begin(DestBB), E = pred_end(DestBB); PI != E;
507 ++PI) {
508 BasicBlock *DestBBPred = *PI;
509 if (DestBBPred == BB)
510 continue;
511
512 bool HasAllSameValue = true;
513 BasicBlock::const_iterator DestBBI = DestBB->begin();
514 while (const PHINode *DestPN = dyn_cast(DestBBI++)) {
515 if (DestPN->getIncomingValueForBlock(BB) !=
516 DestPN->getIncomingValueForBlock(DestBBPred)) {
517 HasAllSameValue = false;
518 break;
519 }
520 }
521 if (HasAllSameValue)
522 SameIncomingValueBBs.insert(DestBBPred);
523 }
524
525 // See if all BB's incoming values are same as the value from Pred. In this
526 // case, no reason to skip merging because COPYs are expected to be place in
527 // Pred already.
528 if (SameIncomingValueBBs.count(Pred))
529 return true;
530
531 if (!BFI) {
532 Function &F = *BB->getParent();
533 LoopInfo LI{DominatorTree(F)};
534 BPI.reset(new BranchProbabilityInfo(F, LI));
535 BFI.reset(new BlockFrequencyInfo(F, *BPI, LI));
536 }
537
538 BlockFrequency PredFreq = BFI->getBlockFreq(Pred);
539 BlockFrequency BBFreq = BFI->getBlockFreq(BB);
540
541 for (auto SameValueBB : SameIncomingValueBBs)
542 if (SameValueBB->getUniquePredecessor() == Pred &&
543 DestBB == findDestBlockOfMergeableEmptyBlock(SameValueBB))
544 BBFreq += BFI->getBlockFreq(SameValueBB);
545
546 return PredFreq.getFrequency() <=
547 BBFreq.getFrequency() * FreqRatioToSkipMerge;
442548 }
443549
444550 /// Return true if we can merge BB into DestBB if there is a single
None ; RUN: llc -march=avr -print-after=expand-isel-pseudos < %s 2>&1 | FileCheck %s
0 ; RUN: llc -march=avr -print-after=expand-isel-pseudos -cgp-freq-ratio-to-skip-merge=10 < %s 2>&1 | FileCheck %s
11
22 ; Because `switch` seems to trigger Machine Basic Blocks to be ordered
33 ; in a different order than they were constructed, this exposes an
None ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-block-placement -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 | FileCheck %s
1 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -tail-dup-placement=0 -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 | FileCheck -check-prefix=OPT %s
0 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-block-placement -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 | FileCheck %s
1 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -tail-dup-placement=0 -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 | FileCheck -check-prefix=OPT %s
22
33 ; Test the CFG stackifier pass.
44
0 ; REQUIRES: asserts
1 ; RUN: llc < %s -disable-preheader-prot=true -march=x86 -stats 2>&1 | grep "Number of blocks eliminated" | grep 6
1 ; RUN: llc < %s -disable-preheader-prot=true -march=x86 -stats 2>&1 | grep "Number of blocks eliminated" | grep 3
2 ; RUN: llc < %s -disable-preheader-prot=true -march=x86 -stats -cgp-freq-ratio-to-skip-merge=10 2>&1 | grep "Number of blocks eliminated" | grep 6
23 ; RUN: llc < %s -disable-preheader-prot=false -march=x86 -stats 2>&1 | grep "Number of blocks eliminated" | grep 3
34 ; PR1296
45
176176 br label %for.cond357
177177
178178 sw.bb474:
179 ; CHECK: sw.bb474
180 ; spill is hoisted here. Although loop depth1 is even hotter than loop depth2, sw.bb474 is still cold.
181 ; CHECK: movq %r{{.*}}, {{[0-9]+}}(%rsp)
182 ; CHECK: land.rhs485
179183 %cmp476 = icmp eq i8 undef, 0
180184 br i1 %cmp476, label %if.end517, label %do.body479.preheader
181185
182186 do.body479.preheader:
183 ; CHECK: do.body479.preheader
184 ; spill is hoisted here. Although loop depth1 is even hotter than loop depth2, do.body479.preheader is cold.
185 ; CHECK: movq %r{{.*}}, {{[0-9]+}}(%rsp)
186 ; CHECK: land.rhs485
187187 %cmp4833314 = icmp eq i8 undef, 0
188188 br i1 %cmp4833314, label %if.end517, label %land.rhs485
189189
2727 ; ARM64-LABEL: @widen_switch_i16(
2828 ; ARM64: %0 = zext i16 %trunc to i32
2929 ; ARM64-NEXT: switch i32 %0, label %sw.default [
30 ; ARM64-NEXT: i32 1, label %return
30 ; ARM64-NEXT: i32 1, label %sw.bb0
3131 ; ARM64-NEXT: i32 65535, label %sw.bb1
3232 }
3333
5757 ; ARM64-LABEL: @widen_switch_i17(
5858 ; ARM64: %0 = zext i17 %trunc to i32
5959 ; ARM64-NEXT: switch i32 %0, label %sw.default [
60 ; ARM64-NEXT: i32 10, label %return
60 ; ARM64-NEXT: i32 10, label %sw.bb0
6161 ; ARM64-NEXT: i32 131071, label %sw.bb1
6262 }
6363
8888 ; ARM64-LABEL: @widen_switch_i16_sext(
8989 ; ARM64: %0 = sext i2 %a to i32
9090 ; ARM64-NEXT: switch i32 %0, label %sw.default [
91 ; ARM64-NEXT: i32 1, label %return
91 ; ARM64-NEXT: i32 1, label %sw.bb0
9292 ; ARM64-NEXT: i32 -1, label %sw.bb1
9393 }
9494
2727 ; X86-LABEL: @widen_switch_i16(
2828 ; X86: %trunc = trunc i32 %a to i16
2929 ; X86-NEXT: switch i16 %trunc, label %sw.default [
30 ; X86-NEXT: i16 1, label %return
30 ; X86-NEXT: i16 1, label %sw.bb0
3131 ; X86-NEXT: i16 -1, label %sw.bb1
3232 }
3333
5757 ; X86-LABEL: @widen_switch_i17(
5858 ; X86: %0 = zext i17 %trunc to i32
5959 ; X86-NEXT: switch i32 %0, label %sw.default [
60 ; X86-NEXT: i32 10, label %return
60 ; X86-NEXT: i32 10, label %sw.bb0
6161 ; X86-NEXT: i32 131071, label %sw.bb1
6262 }
6363
8888 ; X86-LABEL: @widen_switch_i16_sext(
8989 ; X86: %0 = sext i2 %a to i8
9090 ; X86-NEXT: switch i8 %0, label %sw.default [
91 ; X86-NEXT: i8 1, label %return
91 ; X86-NEXT: i8 1, label %sw.bb0
9292 ; X86-NEXT: i8 -1, label %sw.bb1
9393 }
9494
0 ; RUN: opt -codegenprepare < %s -mtriple=aarch64-none-linux-gnu -S | FileCheck %s
1
2 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
3 target triple = "aarch64--linux-gnu"
4
5 ; Expect to skip merging two empty blocks (sw.bb and sw.bb2) into sw.epilog
6 ; as both of them are unlikely executed.
7 define i32 @f_switch(i32 %c) {
8 ; CHECK-LABEL: @f_switch
9 ; CHECK-LABEL: entry:
10 ; CHECK: i32 10, label %sw.bb
11 ; CHECK: i32 20, label %sw.bb2
12 entry:
13 switch i32 %c, label %sw.default [
14 i32 10, label %sw.bb
15 i32 20, label %sw.bb2
16 i32 30, label %sw.bb3
17 i32 40, label %sw.bb4
18 ], !prof !0
19
20 sw.bb: ; preds = %entry
21 br label %sw.epilog
22
23 sw.bb2: ; preds = %entry
24 br label %sw.epilog
25
26 sw.bb3: ; preds = %entry
27 call void bitcast (void (...)* @callcase3 to void ()*)()
28 br label %sw.epilog
29
30 sw.bb4: ; preds = %entry
31 call void bitcast (void (...)* @callcase4 to void ()*)()
32 br label %sw.epilog
33
34 sw.default: ; preds = %entry
35 call void bitcast (void (...)* @calldefault to void ()*)()
36 br label %sw.epilog
37
38 ; CHECK-LABEL: sw.epilog:
39 ; CHECK: %fp.0 = phi void (...)* [ @FD, %sw.default ], [ @F4, %sw.bb4 ], [ @F3, %sw.bb3 ], [ @F2, %sw.bb2 ], [ @F1, %sw.bb ]
40 sw.epilog: ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb
41 %fp.0 = phi void (...)* [ @FD, %sw.default ], [ @F4, %sw.bb4 ], [ @F3, %sw.bb3 ], [ @F2, %sw.bb2 ], [ @F1, %sw.bb ]
42 %callee.knr.cast = bitcast void (...)* %fp.0 to void ()*
43 call void %callee.knr.cast()
44 ret i32 0
45 }
46
47 ; Expect not to merge sw.bb2 because of the conflict in the incoming value from
48 ; sw.bb which is already merged.
49 define i32 @f_switch2(i32 %c) {
50 ; CHECK-LABEL: @f_switch2
51 ; CHECK-LABEL: entry:
52 ; CHECK: i32 10, label %sw.epilog
53 ; CHECK: i32 20, label %sw.bb2
54 entry:
55 switch i32 %c, label %sw.default [
56 i32 10, label %sw.bb
57 i32 20, label %sw.bb2
58 i32 30, label %sw.bb3
59 i32 40, label %sw.bb4
60 ], !prof !1
61
62 sw.bb: ; preds = %entry
63 br label %sw.epilog
64
65 sw.bb2: ; preds = %entry
66 br label %sw.epilog
67
68 sw.bb3: ; preds = %entry
69 call void bitcast (void (...)* @callcase3 to void ()*)()
70 br label %sw.epilog
71
72 sw.bb4: ; preds = %entry
73 call void bitcast (void (...)* @callcase4 to void ()*)()
74 br label %sw.epilog
75
76 sw.default: ; preds = %entry
77 call void bitcast (void (...)* @calldefault to void ()*)()
78 br label %sw.epilog
79
80 ; CHECK-LABEL: sw.epilog:
81 ; CHECK: %fp.0 = phi void (...)* [ @FD, %sw.default ], [ @F4, %sw.bb4 ], [ @F3, %sw.bb3 ], [ @F2, %sw.bb2 ], [ @F1, %entry ]
82 sw.epilog: ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb
83 %fp.0 = phi void (...)* [ @FD, %sw.default ], [ @F4, %sw.bb4 ], [ @F3, %sw.bb3 ], [ @F2, %sw.bb2 ], [ @F1, %sw.bb ]
84 %callee.knr.cast = bitcast void (...)* %fp.0 to void ()*
85 call void %callee.knr.cast()
86 ret i32 0
87 }
88
89 ; Multiple empty blocks should be considered together if all incoming values
90 ; from them are same. We expect to merge both empty blocks (sw.bb and sw.bb2)
91 ; because the sum of frequencies are higer than the threshold.
92 define i32 @f_switch3(i32 %c) {
93 ; CHECK-LABEL: @f_switch3
94 ; CHECK-LABEL: entry:
95 ; CHECK: i32 10, label %sw.epilog
96 ; CHECK: i32 20, label %sw.epilog
97 entry:
98 switch i32 %c, label %sw.default [
99 i32 10, label %sw.bb
100 i32 20, label %sw.bb2
101 i32 30, label %sw.bb3
102 i32 40, label %sw.bb4
103 ], !prof !2
104
105 sw.bb: ; preds = %entry
106 br label %sw.epilog
107
108 sw.bb2: ; preds = %entry
109 br label %sw.epilog
110
111 sw.bb3: ; preds = %entry
112 call void bitcast (void (...)* @callcase3 to void ()*)()
113 br label %sw.epilog
114
115 sw.bb4: ; preds = %entry
116 call void bitcast (void (...)* @callcase4 to void ()*)()
117 br label %sw.epilog
118
119 sw.default: ; preds = %entry
120 call void bitcast (void (...)* @calldefault to void ()*)()
121 br label %sw.epilog
122
123 ; CHECK-LABEL: sw.epilog:
124 ; CHECK: %fp.0 = phi void (...)* [ @FD, %sw.default ], [ @F4, %sw.bb4 ], [ @F3, %sw.bb3 ], [ @F1, %entry ], [ @F1, %entry ]
125 sw.epilog: ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb
126 %fp.0 = phi void (...)* [ @FD, %sw.default ], [ @F4, %sw.bb4 ], [ @F3, %sw.bb3 ], [ @F1, %sw.bb2 ], [ @F1, %sw.bb ]
127 %callee.knr.cast = bitcast void (...)* %fp.0 to void ()*
128 call void %callee.knr.cast()
129 ret i32 0
130 }
131
132 declare void @F1(...) local_unnamed_addr
133 declare void @F2(...) local_unnamed_addr
134 declare void @F3(...) local_unnamed_addr
135 declare void @F4(...) local_unnamed_addr
136 declare void @FD(...) local_unnamed_addr
137 declare void @callcase3(...) local_unnamed_addr
138 declare void @callcase4(...) local_unnamed_addr
139 declare void @calldefault(...) local_unnamed_addr
140
141 !0 = !{!"branch_weights", i32 5, i32 1, i32 1,i32 5, i32 5}
142 !1 = !{!"branch_weights", i32 1 , i32 5, i32 1,i32 1, i32 1}
143 !2 = !{!"branch_weights", i32 1 , i32 4, i32 1,i32 1, i32 1}
144
145
146 ; This test that BFI/BPI is created without any assertion in isMergingEmptyBlockProfitable()
147 ; in the case where empty blocks are removed before creating BFI/BPI.
148 @b = common global i32 0, align 4
149 @a = common global i32* null, align 8
150 define i32 @should_not_assert(i32 %i) local_unnamed_addr {
151 entry:
152 %0 = load i32, i32* @b, align 4
153 %cond = icmp eq i32 %0, 6
154 br i1 %cond, label %while.cond.preheader, label %sw.epilog
155
156 while.cond.preheader: ; preds = %entry
157 %1 = load i32*, i32** @a, align 8
158 %magicptr = ptrtoint i32* %1 to i64
159 %arrayidx = getelementptr inbounds i32, i32* %1, i64 1
160 br label %while.cond
161
162 while.cond: ; preds = %while.cond.preheader, %land.rhs
163 switch i64 %magicptr, label %land.rhs [
164 i64 32, label %while.cond2.loopexit
165 i64 0, label %while.cond2.loopexit
166 ]
167
168 land.rhs: ; preds = %while.cond
169 %2 = load i32, i32* %arrayidx, align 4
170 %tobool1 = icmp eq i32 %2, 0
171 br i1 %tobool1, label %while.cond2thread-pre-split.loopexit, label %while.cond
172
173 while.cond2thread-pre-split.loopexit: ; preds = %land.rhs
174 br label %while.cond2thread-pre-split
175
176 while.cond2thread-pre-split: ; preds = %while.cond2thread-pre-split.loopexit, %while.body4
177 %.pr = phi i32* [ %.pr.pre, %while.body4 ], [ %1, %while.cond2thread-pre-split.loopexit ]
178 br label %while.cond2
179
180 while.cond2.loopexit: ; preds = %while.cond, %while.cond
181 br label %while.cond2
182
183 while.cond2: ; preds = %while.cond2.loopexit, %while.cond2thread-pre-split
184 %3 = phi i32* [ %.pr, %while.cond2thread-pre-split ], [ %1, %while.cond2.loopexit ]
185 %tobool3 = icmp eq i32* %3, null
186 br i1 %tobool3, label %sw.epilog, label %while.body4
187
188 while.body4: ; preds = %while.cond2
189 tail call void bitcast (void (...)* @fn2 to void ()*)()
190 %.pr.pre = load i32*, i32** @a, align 8
191 br label %while.cond2thread-pre-split
192
193 sw.epilog: ; preds = %while.cond2, %entry
194 ret i32 undef
195 }
196
197
198 declare void @fn2(...) local_unnamed_addr
199