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Add instruction itinerary for the PPC64 A2 core. This adds a full itinerary for IBM's PPC64 A2 embedded core. These cores form the basis for the CPUs in the new IBM BG/Q supercomputer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 8 years ago
8 changed file(s) with 615 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
3333 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
3434 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
3535 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
36 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
3637
3738 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
3839 "Enable 64-bit instructions">;
8687 [Directive970, FeatureAltivec,
8788 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
8889 Feature64Bit /*, Feature64BitRegs */]>;
90 def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
91 FeatureFSqrt, FeatureSTFIWX,
92 Feature64Bit /*, Feature64BitRegs */]>;
8993 def : Processor<"ppc", G3Itineraries, [Directive32]>;
9094 def : Processor<"ppc64", G5Itineraries,
9195 [Directive64, FeatureAltivec,
449449 "ppc7400",
450450 "ppc750",
451451 "ppc970",
452 "ppcA2",
452453 "ppc64"
453454 };
454455
2121 #include "llvm/CodeGen/MachineInstrBuilder.h"
2222 #include "llvm/CodeGen/MachineMemOperand.h"
2323 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
2425 #include "llvm/MC/MCAsmInfo.h"
2526 #include "llvm/Support/CommandLine.h"
2627 #include "llvm/Support/ErrorHandling.h"
4849 const TargetMachine *TM,
4950 const ScheduleDAG *DAG) const {
5051 unsigned Directive = TM->getSubtarget().getDarwinDirective();
51 if (Directive == PPC::DIR_440) {
52 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2) {
5253 const InstrItineraryData *II = TM->getInstrItineraryData();
5354 return new PPCScoreboardHazardRecognizer(II, DAG);
5455 }
6465 unsigned Directive = TM.getSubtarget().getDarwinDirective();
6566
6667 // Most subtargets use a PPC970 recognizer.
67 if (Directive != PPC::DIR_440) {
68 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2) {
6869 const TargetInstrInfo *TII = TM.getInstrInfo();
6970 assert(TII && "No InstrInfo?");
7071
7172 return new PPCHazardRecognizer970(*TII);
7273 }
7374
74 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
75 return new PPCScoreboardHazardRecognizer(II, DAG);
7576 }
7677 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
7778 int &FrameIndex) const {
107107 include "PPCScheduleG4.td"
108108 include "PPCScheduleG4Plus.td"
109109 include "PPCScheduleG5.td"
110 include "PPCScheduleA2.td"
110111
111112 //===----------------------------------------------------------------------===//
112113 // Instruction to itinerary class map - When add new opcodes to the supported
0 //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 // Primary reference:
10 // A2 Processor User's Manual.
11 // IBM (as updated in) 2010.
12
13 //===----------------------------------------------------------------------===//
14 // Functional units on the PowerPC A2 chip sets
15 //
16 def IU0to3_0 : FuncUnit; // Fetch unit 1 to 4 slot 1
17 def IU0to3_1 : FuncUnit; // Fetch unit 1 to 4 slot 2
18 def IU0to3_2 : FuncUnit; // Fetch unit 1 to 4 slot 3
19 def IU0to3_3 : FuncUnit; // Fetch unit 1 to 4 slot 4
20 def IU4_0 : FuncUnit; // Instruction buffer slot 1
21 def IU4_1 : FuncUnit; // Instruction buffer slot 2
22 def IU4_2 : FuncUnit; // Instruction buffer slot 3
23 def IU4_3 : FuncUnit; // Instruction buffer slot 4
24 def IU4_4 : FuncUnit; // Instruction buffer slot 5
25 def IU4_5 : FuncUnit; // Instruction buffer slot 6
26 def IU4_6 : FuncUnit; // Instruction buffer slot 7
27 def IU4_7 : FuncUnit; // Instruction buffer slot 8
28 def IU5 : FuncUnit; // Dependency resolution
29 def IU6 : FuncUnit; // Instruction issue
30 def RF0 : FuncUnit;
31 def XRF1 : FuncUnit;
32 def XEX1 : FuncUnit; // Execution stage 1 for the XU pipeline
33 def XEX2 : FuncUnit; // Execution stage 2 for the XU pipeline
34 def XEX3 : FuncUnit; // Execution stage 3 for the XU pipeline
35 def XEX4 : FuncUnit; // Execution stage 4 for the XU pipeline
36 def XEX5 : FuncUnit; // Execution stage 5 for the XU pipeline
37 def XEX6 : FuncUnit; // Execution stage 6 for the XU pipeline
38 def FRF1 : FuncUnit;
39 def FEX1 : FuncUnit; // Execution stage 1 for the FU pipeline
40 def FEX2 : FuncUnit; // Execution stage 2 for the FU pipeline
41 def FEX3 : FuncUnit; // Execution stage 3 for the FU pipeline
42 def FEX4 : FuncUnit; // Execution stage 4 for the FU pipeline
43 def FEX5 : FuncUnit; // Execution stage 5 for the FU pipeline
44 def FEX6 : FuncUnit; // Execution stage 6 for the FU pipeline
45
46 def CR_Bypass : Bypass; // The bypass for condition regs.
47 //def GPR_Bypass : Bypass; // The bypass for general-purpose regs.
48 //def FPR_Bypass : Bypass; // The bypass for floating-point regs.
49
50 //
51 // This file defines the itinerary class data for the PPC A2 processor.
52 //
53 //===----------------------------------------------------------------------===//
54
55
56 def PPCA2Itineraries : ProcessorItineraries<
57 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3,
58 IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7,
59 IU5, IU6, RF0, XRF1, XEX1, XEX2, XEX3, XEX4, XEX5, XEX6,
60 FRF1, FEX1, FEX2, FEX3, FEX4, FEX5, FEX6],
61 [CR_Bypass, GPR_Bypass, FPR_Bypass], [
62 InstrItinData,
63 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
64 IU4_4, IU4_5, IU4_6, IU4_7]>,
65 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
66 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
67 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
68 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
69 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
70 [10, 7, 7],
71 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
72 InstrItinData,
73 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
74 IU4_4, IU4_5, IU4_6, IU4_7]>,
75 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
76 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
77 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
78 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
79 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
80 [10, 7, 7],
81 [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
82 InstrItinData,
83 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
84 IU4_4, IU4_5, IU4_6, IU4_7]>,
85 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
86 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
87 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
88 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
89 InstrStage<1, [XEX5]>, InstrStage<38, [XEX6]>],
90 [53, 7, 7],
91 [NoBypass, GPR_Bypass, GPR_Bypass]>,
92 InstrItinData,
93 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
94 IU4_4, IU4_5, IU4_6, IU4_7]>,
95 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
96 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
97 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
98 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
99 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
100 [10, 7, 7],
101 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
102 InstrItinData,
103 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
104 IU4_4, IU4_5, IU4_6, IU4_7]>,
105 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
106 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
107 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
108 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
109 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
110 [10, 7, 7],
111 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
112 InstrItinData,
113 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
114 IU4_4, IU4_5, IU4_6, IU4_7]>,
115 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
116 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
117 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
118 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
119 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
120 [14, 7, 7],
121 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
122 InstrItinData,
123 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
124 IU4_4, IU4_5, IU4_6, IU4_7]>,
125 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
126 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
127 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
128 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
129 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
130 [14, 7, 7],
131 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
132 InstrItinData,
133 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
134 IU4_4, IU4_5, IU4_6, IU4_7]>,
135 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
136 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
137 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
138 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
139 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
140 [15, 7, 7],
141 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
142 InstrItinData,
143 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
144 IU4_4, IU4_5, IU4_6, IU4_7]>,
145 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
146 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
147 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
148 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
149 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
150 [10, 7, 7],
151 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
152 InstrItinData,
153 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
154 IU4_4, IU4_5, IU4_6, IU4_7]>,
155 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
156 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
157 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
158 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
159 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
160 [10, 7, 7],
161 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
162 InstrItinData,
163 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
164 IU4_4, IU4_5, IU4_6, IU4_7]>,
165 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
166 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
167 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
168 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
169 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
170 [10, 7, 7],
171 [GPR_Bypass, GPR_Bypass]>,
172 InstrItinData,
173 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
174 IU4_4, IU4_5, IU4_6, IU4_7]>,
175 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
176 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
177 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
178 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
179 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
180 [15, 7, 7],
181 [NoBypass, GPR_Bypass]>,
182 InstrItinData,
183 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
184 IU4_4, IU4_5, IU4_6, IU4_7]>,
185 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
186 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
187 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
188 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
189 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
190 [10, 7, 7],
191 [CR_Bypass, CR_Bypass, CR_Bypass]>,
192 InstrItinData,
193 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
194 IU4_4, IU4_5, IU4_6, IU4_7]>,
195 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
196 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
197 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
198 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
199 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
200 [10, 7, 7],
201 [CR_Bypass, CR_Bypass, CR_Bypass]>,
202 InstrItinData,
203 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
204 IU4_4, IU4_5, IU4_6, IU4_7]>,
205 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
206 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
207 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
208 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
209 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
210 [10, 7, 7],
211 [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
212 InstrItinData,
213 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
214 IU4_4, IU4_5, IU4_6, IU4_7]>,
215 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
216 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
217 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
218 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
219 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
220 [13, 11],
221 [NoBypass, GPR_Bypass]>,
222 InstrItinData,
223 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
224 IU4_4, IU4_5, IU4_6, IU4_7]>,
225 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
226 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
227 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
228 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
229 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
230 [13, 11],
231 [NoBypass, GPR_Bypass]>,
232 InstrItinData,
233 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
234 IU4_4, IU4_5, IU4_6, IU4_7]>,
235 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
236 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
237 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
238 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
239 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
240 [13, 11],
241 [NoBypass, GPR_Bypass]>,
242 InstrItinData,
243 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
244 IU4_4, IU4_5, IU4_6, IU4_7]>,
245 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
246 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
247 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
248 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
249 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
250 [14, 7],
251 [GPR_Bypass, GPR_Bypass]>,
252 InstrItinData,
253 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
254 IU4_4, IU4_5, IU4_6, IU4_7]>,
255 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
256 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
257 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
258 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
259 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
260 [13, 7],
261 [GPR_Bypass, GPR_Bypass]>,
262 InstrItinData,
263 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
264 IU4_4, IU4_5, IU4_6, IU4_7]>,
265 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
266 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
267 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
268 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
269 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
270 [14, 7],
271 [NoBypass, GPR_Bypass]>,
272 InstrItinData,
273 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
274 IU4_4, IU4_5, IU4_6, IU4_7]>,
275 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
276 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
277 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
278 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
279 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
280 [14, 7, 7],
281 [NoBypass, FPR_Bypass, FPR_Bypass]>,
282 InstrItinData,
283 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
284 IU4_4, IU4_5, IU4_6, IU4_7]>,
285 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
286 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
287 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
288 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
289 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
290 [14, 7, 7],
291 [FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
292 InstrItinData,
293 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
294 IU4_4, IU4_5, IU4_6, IU4_7]>,
295 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
296 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
297 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
298 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
299 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
300 [14, 7, 7],
301 [FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
302 InstrItinData,
303 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
304 IU4_4, IU4_5, IU4_6, IU4_7]>,
305 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
306 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
307 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
308 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
309 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
310 [14, 7],
311 [NoBypass, GPR_Bypass]>,
312 InstrItinData,
313 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
314 IU4_4, IU4_5, IU4_6, IU4_7]>,
315 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
316 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
317 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
318 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
319 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
320 [14, 7],
321 [NoBypass, GPR_Bypass]>,
322 InstrItinData,
323 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
324 IU4_4, IU4_5, IU4_6, IU4_7]>,
325 InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
326 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
327 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
328 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
329 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
330 [26, 7],
331 [NoBypass, GPR_Bypass]>,
332 InstrItinData,
333 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
334 IU4_4, IU4_5, IU4_6, IU4_7]>,
335 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
336 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
337 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
338 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
339 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
340 [13, 7],
341 [GPR_Bypass, GPR_Bypass]>,
342 InstrItinData,
343 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
344 IU4_4, IU4_5, IU4_6, IU4_7]>,
345 InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
346 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
347 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
348 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
349 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
350 [26, 7],
351 [NoBypass, GPR_Bypass]>,
352 InstrItinData,
353 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
354 IU4_4, IU4_5, IU4_6, IU4_7]>,
355 InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
356 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
357 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
358 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
359 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
360 [26, 7],
361 [NoBypass, GPR_Bypass]>,
362 InstrItinData,
363 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
364 IU4_4, IU4_5, IU4_6, IU4_7]>,
365 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
366 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
367 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
368 InstrStage<1, [XEX3]>, InstrStage<12, [XEX4]>,
369 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>]>,
370 InstrItinData,
371 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
372 IU4_4, IU4_5, IU4_6, IU4_7]>,
373 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
374 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
375 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
376 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
377 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>,
378 InstrItinData,
379 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
380 IU4_4, IU4_5, IU4_6, IU4_7]>,
381 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
382 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
383 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
384 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
385 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
386 [15, 7],
387 [GPR_Bypass, NoBypass]>,
388 InstrItinData,
389 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
390 IU4_4, IU4_5, IU4_6, IU4_7]>,
391 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
392 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
393 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
394 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
395 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
396 [15, 7],
397 [NoBypass, GPR_Bypass]>,
398 InstrItinData,
399 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
400 IU4_4, IU4_5, IU4_6, IU4_7]>,
401 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
402 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
403 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
404 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
405 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
406 [15, 7],
407 [NoBypass, GPR_Bypass]>,
408 InstrItinData,
409 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
410 IU4_4, IU4_5, IU4_6, IU4_7]>,
411 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
412 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
413 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
414 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
415 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>,
416 InstrItinData,
417 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
418 IU4_4, IU4_5, IU4_6, IU4_7]>,
419 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
420 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
421 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
422 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
423 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
424 [10, 7],
425 [GPR_Bypass, CR_Bypass]>,
426 InstrItinData,
427 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
428 IU4_4, IU4_5, IU4_6, IU4_7]>,
429 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
430 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
431 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
432 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
433 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
434 [15, 7],
435 [GPR_Bypass, NoBypass]>,
436 InstrItinData,
437 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
438 IU4_4, IU4_5, IU4_6, IU4_7]>,
439 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
440 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
441 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
442 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
443 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
444 [15, 7],
445 [NoBypass, GPR_Bypass]>,
446 InstrItinData,
447 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
448 IU4_4, IU4_5, IU4_6, IU4_7]>,
449 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
450 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
451 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
452 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
453 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
454 [29, 7],
455 [NoBypass, GPR_Bypass]>,
456 InstrItinData,
457 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
458 IU4_4, IU4_5, IU4_6, IU4_7]>,
459 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
460 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
461 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
462 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
463 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
464 [15, 7],
465 [NoBypass, GPR_Bypass]>,
466 InstrItinData,
467 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
468 IU4_4, IU4_5, IU4_6, IU4_7]>,
469 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
470 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
471 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
472 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
473 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
474 [29, 7],
475 [NoBypass, GPR_Bypass]>,
476 InstrItinData,
477 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
478 IU4_4, IU4_5, IU4_6, IU4_7]>,
479 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
480 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
481 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
482 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
483 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
484 [29, 7],
485 [NoBypass, GPR_Bypass]>,
486 InstrItinData,
487 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
488 IU4_4, IU4_5, IU4_6, IU4_7]>,
489 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
490 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
491 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
492 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
493 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
494 [29, 7],
495 [NoBypass, GPR_Bypass]>,
496 InstrItinData,
497 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
498 IU4_4, IU4_5, IU4_6, IU4_7]>,
499 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
500 InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
501 InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
502 InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
503 InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
504 [15, 7, 7],
505 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
506 InstrItinData,
507 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
508 IU4_4, IU4_5, IU4_6, IU4_7]>,
509 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
510 InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
511 InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
512 InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
513 InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
514 [13, 7, 7],
515 [CR_Bypass, FPR_Bypass, FPR_Bypass]>,
516 InstrItinData,
517 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
518 IU4_4, IU4_5, IU4_6, IU4_7]>,
519 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
520 InstrStage<1, [RF0]>, InstrStage<71, [FRF1], 0>,
521 InstrStage<71, [FEX1], 0>, InstrStage<71, [FEX2], 0>,
522 InstrStage<71, [FEX3], 0>, InstrStage<71, [FEX4], 0>,
523 InstrStage<71, [FEX5], 0>, InstrStage<71, [FEX6]>],
524 [86, 7, 7],
525 [NoBypass, FPR_Bypass, FPR_Bypass]>,
526 InstrItinData,
527 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
528 IU4_4, IU4_5, IU4_6, IU4_7]>,
529 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
530 InstrStage<1, [RF0]>, InstrStage<58, [FRF1], 0>,
531 InstrStage<58, [FEX1], 0>, InstrStage<58, [FEX2], 0>,
532 InstrStage<58, [FEX3], 0>, InstrStage<58, [FEX4], 0>,
533 InstrStage<58, [FEX5], 0>, InstrStage<58, [FEX6]>],
534 [73, 7, 7],
535 [NoBypass, FPR_Bypass, FPR_Bypass]>,
536 InstrItinData,
537 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
538 IU4_4, IU4_5, IU4_6, IU4_7]>,
539 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
540 InstrStage<1, [RF0]>, InstrStage<68, [FRF1], 0>,
541 InstrStage<68, [FEX1], 0>, InstrStage<68, [FEX2], 0>,
542 InstrStage<68, [FEX3], 0>, InstrStage<68, [FEX4], 0>,
543 InstrStage<68, [FEX5], 0>, InstrStage<68, [FEX6]>],
544 [86, 7], // FIXME: should be [86, 7] for double
545 // and [82, 7] for single. Likewise,
546 // the FEX? cycle count should be 68
547 // for double and 64 for single.
548 [NoBypass, FPR_Bypass]>,
549 InstrItinData,
550 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
551 IU4_4, IU4_5, IU4_6, IU4_7]>,
552 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
553 InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
554 InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
555 InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
556 InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
557 [15, 7, 7, 7],
558 [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
559 InstrItinData,
560 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
561 IU4_4, IU4_5, IU4_6, IU4_7]>,
562 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
563 InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
564 InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
565 InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
566 InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
567 [15, 7],
568 [FPR_Bypass, FPR_Bypass]>
569 ]>;
145145 CodeGenOpt::Level OptLevel,
146146 TargetSubtargetInfo::AntiDepBreakMode& Mode,
147147 RegClassVector& CriticalPathRCs) const {
148 if (DarwinDirective == PPC::DIR_440)
148 if (DarwinDirective == PPC::DIR_440 || DarwinDirective == PPC::DIR_A2)
149149 return false;
150150
151151 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
3939 DIR_7400,
4040 DIR_750,
4141 DIR_970,
42 DIR_A2,
4243 DIR_64
4344 };
4445 }
0 ; RUN: llc < %s -march=ppc64 -mcpu=a2 | FileCheck %s
1
2 %0 = type { double, double }
3
4 define void @maybe_an_fma(%0* sret %agg.result, %0* byval %a, %0* byval %b, %0* byval %c) nounwind {
5 entry:
6 %a.realp = getelementptr inbounds %0* %a, i32 0, i32 0
7 %a.real = load double* %a.realp
8 %a.imagp = getelementptr inbounds %0* %a, i32 0, i32 1
9 %a.imag = load double* %a.imagp
10 %b.realp = getelementptr inbounds %0* %b, i32 0, i32 0
11 %b.real = load double* %b.realp
12 %b.imagp = getelementptr inbounds %0* %b, i32 0, i32 1
13 %b.imag = load double* %b.imagp
14 %mul.rl = fmul double %a.real, %b.real
15 %mul.rr = fmul double %a.imag, %b.imag
16 %mul.r = fsub double %mul.rl, %mul.rr
17 %mul.il = fmul double %a.imag, %b.real
18 %mul.ir = fmul double %a.real, %b.imag
19 %mul.i = fadd double %mul.il, %mul.ir
20 %c.realp = getelementptr inbounds %0* %c, i32 0, i32 0
21 %c.real = load double* %c.realp
22 %c.imagp = getelementptr inbounds %0* %c, i32 0, i32 1
23 %c.imag = load double* %c.imagp
24 %add.r = fadd double %mul.r, %c.real
25 %add.i = fadd double %mul.i, %c.imag
26 %real = getelementptr inbounds %0* %agg.result, i32 0, i32 0
27 %imag = getelementptr inbounds %0* %agg.result, i32 0, i32 1
28 store double %add.r, double* %real
29 store double %add.i, double* %imag
30 ret void
31 ; CHECK: fmadd
32 }