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[X86][MIPS][ARM] New machine instruction property 'isMoveReg' This property is needed in order to follow values movement between registers. This property is used in TII to implement method that returns true if simple copy like instruction is recognized, along with source and destination machine operands. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D45204 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333093 91177308-0d34-0410-b5e6-96231b3b80d8 Petar Jovanovic 2 years ago
31 changed file(s) with 188 addition(s) and 27 deletion(s). Raw diff Collapse all Expand all
546546 return hasProperty(MCID::MoveImm, Type);
547547 }
548548
549 /// Return true if this instruction is a register move.
550 /// (including moving values from subreg to reg)
551 bool isMoveReg(QueryType Type = IgnoreBundle) const {
552 return hasProperty(MCID::MoveReg, Type);
553 }
554
549555 /// Return true if this instruction is a bitcast instruction.
550556 bool isBitcast(QueryType Type = IgnoreBundle) const {
551557 return hasProperty(MCID::Bitcast, Type);
844844 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
845845 }
846846
847 /// If the specific machine instruction is a instruction that moves/copies
848 /// value from one register to another register return true along with
849 /// @Source machine operand and @Destination machine operand.
850 virtual bool isCopyInstr(const MachineInstr &MI, MachineOperand &Source,
851 MachineOperand &Destination) const {
852 return false;
853 }
854
847855 /// Store the specified register of the given register class to the specified
848856 /// stack frame index. The store instruction is to be added to the given
849857 /// machine basic block before the specified machine instruction. If isKill
126126 IndirectBranch,
127127 Compare,
128128 MoveImm,
129 MoveReg,
129130 Bitcast,
130131 Select,
131132 DelaySlot,
243244 /// Return true if the instruction is an add instruction.
244245 bool isAdd() const { return Flags & (1ULL << MCID::Add); }
245246
247 /// Return true if the instruction is a register to register move.
248 bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
249
246250 /// Return true if the instruction is a call.
247251 bool isCall() const { return Flags & (1ULL << MCID::Call); }
248252
436436 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
437437 bit isCompare = 0; // Is this instruction a comparison instruction?
438438 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
439 bit isMoveReg = 0; // Is this instruction a move register instruction?
439440 bit isBitcast = 0; // Is this instruction a bitcast instruction?
440441 bit isSelect = 0; // Is this instruction a select instruction?
441442 bit isBarrier = 0; // Can control flow fall through this instruction?
932932 Mov->addRegisterDefined(DestReg, TRI);
933933 if (KillSrc)
934934 Mov->addRegisterKilled(SrcReg, TRI);
935 }
936
937 bool ARMBaseInstrInfo::isCopyInstr(const MachineInstr &MI, MachineOperand &Src,
938 MachineOperand &Dest) const {
939 // VMOVRRD is also a copy instruction but it requires
940 // special way of handling. It is more complex copy version
941 // and since that we are not considering it. For recognition
942 // of such instruction isExtractSubregLike MI interface fuction
943 // could be used.
944 // VORRq is considered as a move only if two inputs are
945 // the same register.
946 if (!MI.isMoveReg() ||
947 (MI.getOpcode() == ARM::VORRq &&
948 MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
949 return false;
950 Dest = MI.getOperand(0);
951 Src = MI.getOperand(1);
952 return true;
935953 }
936954
937955 const MachineInstrBuilder &
199199 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
200200 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
201201 bool KillSrc) const override;
202
203 bool isCopyInstr(const MachineInstr &MI, MachineOperand &Src,
204 MachineOperand &Dest) const override;
202205
203206 void storeRegToStackSlot(MachineBasicBlock &MBB,
204207 MachineBasicBlock::iterator MBBI,
33393339 // Move Instructions.
33403340 //
33413341
3342 let hasSideEffects = 0 in
3342 let hasSideEffects = 0, isMoveReg = 1 in
33433343 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
33443344 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
33453345 bits<4> Rd;
11531153
11541154 // A7-73: MOV(2) - mov setting flag.
11551155
1156 let hasSideEffects = 0 in {
1156 let hasSideEffects = 0, isMoveReg = 1 in {
11571157 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
11581158 2, IIC_iMOVr,
11591159 "mov", "\t$Rd, $Rm", "", []>,
998998 []>;
999999
10001000 let hasSideEffects = 0 in {
1001 let isMoveReg = 1 in {
10011002 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
10021003 (outs DPR:$Dd), (ins DPR:$Dm),
10031004 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
10051006 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
10061007 (outs SPR:$Sd), (ins SPR:$Sm),
10071008 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
1009 } // isMoveReg
10081010
10091011 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
10101012 def VMOVH : ASuInp<0b11101, 0b11, 0b0000, 0b01, 0,
10231025 // FP <-> GPR Copies. Int <-> FP Conversions.
10241026 //
10251027
1028 let isMoveReg = 1 in {
10261029 def VMOVRS : AVConv2I<0b11100001, 0b1010,
10271030 (outs GPR:$Rt), (ins SPR:$Sn),
10281031 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
10681071 // pipelines.
10691072 let D = VFPNeonDomain;
10701073 }
1074 } // isMoveReg
10711075 def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>, Requires<[HasVFP2, UseVMOVSR]>;
10721076
10731077 let hasSideEffects = 0 in {
385385 string AsmString = !strconcat("wrdsp", "\t$rt, $mask");
386386 list Pattern = [(int_mips_wrdsp GPR32Opnd:$rt, immZExt7:$mask)];
387387 InstrItinClass Itinerary = NoItinerary;
388 bit isMoveReg = 1;
388389 }
389390
390391 class BPOSGE32C_MMR3_DESC {
129129 }
130130
131131 def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
132 ABS_FM_MM<0, 0x1>, ISA_MICROMIPS;
132 ABS_FM_MM<0, 0x1>, ISA_MICROMIPS {
133 let isMoveReg = 1;
134 }
133135 def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
134136 ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS;
135137
237237 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
238238 NoItinerary, FrmR> {
239239 let isReMaterializable = 1;
240 let isMoveReg = 1;
240241 }
241242
242243 /// A register pair used by load/store pair instructions.
414415 [], II_MFHI_MFLO, FrmR> {
415416 let Uses = [UseReg];
416417 let hasSideEffects = 0;
418 let isMoveReg = 1;
417419 }
418420
419421 class MoveMM16
420422 : MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
421423 !strconcat(opstr, "\t$rd, $rs"), [], II_MOVE, FrmR> {
422424 let isReMaterializable = 1;
425 let isMoveReg = 1;
423426 }
424427
425428 class LoadImmMM16 :
9494
9595 if (SrcReg)
9696 MIB.addReg(SrcReg, getKillRegState(KillSrc));
97 }
98
99 bool Mips16InstrInfo::isCopyInstr(const MachineInstr &MI, MachineOperand &Src,
100 MachineOperand &Dest) const {
101 if (MI.isMoveReg()) {
102 Dest = MI.getOperand(0);
103 Src = MI.getOperand(1);
104 return true;
105 }
106 return false;
97107 }
98108
99109 void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
5151 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
5252 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
5353 bool KillSrc) const override;
54
55 bool isCopyInstr(const MachineInstr &MI, MachineOperand &Src,
56 MachineOperand &Dest) const override;
5457
5558 void storeRegToStack(MachineBasicBlock &MBB,
5659 MachineBasicBlock::iterator MBBI,
868868 //Purpose: Move
869869 // To move the contents of a GPR to a GPR.
870870 //
871 def MoveR3216: FI8_MOVR3216_ins<"move", IIM16Alu>;
871 def MoveR3216: FI8_MOVR3216_ins<"move", IIM16Alu> {
872 let isMoveReg = 1;
873 }
872874
873875 //
874876 // Format: MFHI rx MIPS16e
878880 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIM16Alu> {
879881 let Uses = [HI0];
880882 let hasSideEffects = 0;
883 let isMoveReg = 1;
881884 }
882885
883886 //
888891 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIM16Alu> {
889892 let Uses = [LO0];
890893 let hasSideEffects = 0;
894 let isMoveReg = 0;
891895 }
892896
893897 //
376376 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
377377 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
378378 "dsll\t$rd, $rt, 32", [], II_DSLL>;
379 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
380 "sll\t$rd, $rt, 0", [], II_SLL>;
381 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
382 "sll\t$rd, $rt, 0", [], II_SLL>;
379 let isMoveReg = 1 in {
380 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
381 "sll\t$rd, $rt, 0", [], II_SLL>;
382 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
383 "sll\t$rd, $rt, 0", [], II_SLL>;
384 }
383385 }
384386
385387 // We need the following pseudo instruction to avoid offset calculation for
446446 list Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
447447 InstrItinClass Itinerary = itin;
448448 string BaseOpcode = instr_asm;
449 bit isMoveReg = 1;
449450 }
450451
451452 class WRDSP_DESC_BASE
456457 list Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
457458 InstrItinClass Itinerary = itin;
458459 string BaseOpcode = instr_asm;
460 bit isMoveReg = 1;
459461 }
460462
461463 class DPA_W_PH_DESC_BASE {
499501 list Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
500502 InstrItinClass Itinerary = itin;
501503 string BaseOpcode = instr_asm;
504 bit isMoveReg = 1;
502505 }
503506
504507 class MTHI_DESC_BASE {
507510 string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
508511 InstrItinClass Itinerary = itin;
509512 string BaseOpcode = instr_asm;
513 bit isMoveReg = 1;
510514 }
511515
512516 class BPOSGE32_PSEUDO_DESC_BASE :
148148 class MFC1_FT
149149 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
150150 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
151 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT;
151 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
152 let isMoveReg = 1;
153 }
152154
153155 class MTC1_FT
154156 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
155157 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
156 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT;
158 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT {
159 let isMoveReg = 1;
160 }
157161
158162 class MTC1_64_FT
159163 InstrItinClass Itin> :
509513 bitconvert>, MFC1_FM<5>, ISA_MIPS3;
510514 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
511515 bitconvert>, MFC1_FM<1>, ISA_MIPS3;
512 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
513 ABSS_FM<0x6, 16>;
514 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
515 ABSS_FM<0x6, 17>, FGR_32;
516 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
517 ABSS_FM<0x6, 17>, FGR_64 {
518 let DecoderNamespace = "MipsFP64";
519 }
516 let isMoveReg = 1 in {
517 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
518 ABSS_FM<0x6, 16>;
519 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
520 ABSS_FM<0x6, 17>, FGR_32;
521 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
522 ABSS_FM<0x6, 17>, FGR_64 {
523 let DecoderNamespace = "MipsFP64";
524 }
525 } // isMoveReg
520526 }
521527
522528 /// Floating Point Memory Instructions
17711771 FrmR, opstr> {
17721772 let Uses = [UseReg];
17731773 let hasSideEffects = 0;
1774 let isMoveReg = 1;
17741775 }
17751776
17761777 class PseudoMTLOHI
17831784 FrmR, opstr> {
17841785 let Defs = DefRegs;
17851786 let hasSideEffects = 0;
1787 let isMoveReg = 1;
17861788 }
17871789
17881790 class EffectiveAddress :
17891789 string AsmString = "cfcmsa\t$rd, $cs";
17901790 InstrItinClass Itinerary = NoItinerary;
17911791 bit hasSideEffects = 1;
1792 bit isMoveReg = 1;
17921793 }
17931794
17941795 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
18831884 string AsmString = "ctcmsa\t$cd, $rs";
18841885 InstrItinClass Itinerary = NoItinerary;
18851886 bit hasSideEffects = 1;
1887 bit isMoveReg = 1;
18861888 }
18871889
18881890 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
24282430 string AsmString = "move.v\t$wd, $ws";
24292431 list Pattern = [];
24302432 InstrItinClass Itinerary = NoItinerary;
2433 bit isMoveReg = 1;
24312434 }
24322435
24332436 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
176176
177177 if (ZeroReg)
178178 MIB.addReg(ZeroReg);
179 }
180
181 static bool isORCopyInst(const MachineInstr &MI) {
182 switch (MI.getOpcode()) {
183 case Mips::OR_MM:
184 case Mips::OR:
185 if (MI.getOperand(2).getReg() == Mips::ZERO)
186 return true;
187 case Mips::OR64:
188 if (MI.getOperand(2).getReg() == Mips::ZERO_64)
189 return true;
190 default:
191 return false;
192 }
193 }
194
195 /// If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true
196 /// if it is WRDSP instruction.
197 static bool isReadOrWritToDSPReg(const MachineInstr &MI, bool &isWrite) {
198 switch (MI.getOpcode()) {
199 case Mips::WRDSP:
200 case Mips::WRDSP_MM:
201 isWrite = true;
202 case Mips::RDDSP:
203 case Mips::RDDSP_MM:
204 return true;
205 default:
206 return false;
207 }
208 }
209
210 /// We check for the common case of 'or', as it's MIPS' preferred instruction
211 /// for GPRs but we have to check the operands to ensure that is the case.
212 /// Other move instructions for MIPS are directly identifiable.
213 bool MipsSEInstrInfo::isCopyInstr(const MachineInstr &MI, MachineOperand &Src,
214 MachineOperand &Dest) const {
215 bool isDSPControlWrite = false;
216 // Condition is made to match the creation of WRDSP/RDDSP copy instruction
217 // from copyPhysReg function.
218 if (isReadOrWritToDSPReg(MI, isDSPControlWrite)) {
219 if (!MI.getOperand(1).isImm() || !MI.getOperand(1).getImm() == (1<<4))
220 return false;
221 else if (isDSPControlWrite) {
222 Src = MI.getOperand(0);
223 Dest = MI.getOperand(2);
224 } else {
225 Dest = MI.getOperand(0);
226 Src = MI.getOperand(2);
227 }
228 return true;
229 } else if (MI.isMoveReg() || isORCopyInst(MI)) {
230 Dest = MI.getOperand(0);
231 Src = MI.getOperand(1);
232 return true;
233 }
234 return false;
179235 }
180236
181237 void MipsSEInstrInfo::
4545 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
4646 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
4747 bool KillSrc) const override;
48
49 bool isCopyInstr(const MachineInstr &MI, MachineOperand &Src,
50 MachineOperand &Dest) const override;
4851
4952 void storeRegToStack(MachineBasicBlock &MBB,
5053 MachineBasicBlock::iterator MI,
26822682 multiclass avx512_mask_mov opc_kk, bits<8> opc_km, bits<8> opc_mk,
26832683 string OpcodeStr, RegisterClass KRC,
26842684 ValueType vvt, X86MemOperand x86memop> {
2685 let hasSideEffects = 0, SchedRW = [WriteMove] in
2685 let isMoveReg = 1, hasSideEffects = 0, SchedRW = [WriteMove] in
26862686 def kk : I
26872687 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
26882688 Sched<[WriteMove]>;
31673167 X86SchedWriteMoveLS Sched, bit NoRMPattern = 0,
31683168 SDPatternOperator SelectOprr = vselect> {
31693169 let hasSideEffects = 0 in {
3170 let isMoveReg = 1 in
31703171 def rr : AVX512PI
31713172 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
31723173 _.ExeDomain>, EVEX, Sched<[Sched.RR]>;
32693270 string Name, X86SchedWriteMoveLS Sched,
32703271 bit NoMRPattern = 0> {
32713272 let hasSideEffects = 0 in {
3273 let isMoveReg = 1 in
32723274 def rr_REV : AVX512PI
32733275 OpcodeStr # ".s\t{$src, $dst|$dst, $src}",
32743276 [], _.ExeDomain>, EVEX, FoldGenData,
68516851 llvm_unreachable("Cannot emit physreg copy instruction");
68526852 }
68536853
6854 bool X86InstrInfo::isCopyInstr(const MachineInstr &MI, MachineOperand &Src,
6855 MachineOperand &Dest) const {
6856 if (MI.isMoveReg()) {
6857 Dest = MI.getOperand(0);
6858 Src = MI.getOperand(1);
6859 return true;
6860 }
6861 return false;
6862 }
6863
68546864 static unsigned getLoadStoreRegOpcode(unsigned Reg,
68556865 const TargetRegisterClass *RC,
68566866 bool isStackAligned,
393393 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
394394 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
395395 bool KillSrc) const override;
396 bool isCopyInstr(const MachineInstr &MI, MachineOperand &Src,
397 MachineOperand &Dest) const override;
396398 void storeRegToStackSlot(MachineBasicBlock &MBB,
397399 MachineBasicBlock::iterator MI, unsigned SrcReg,
398400 bool isKill, int FrameIndex,
14541454 // Move Instructions.
14551455 //
14561456 let SchedRW = [WriteMove] in {
1457 let hasSideEffects = 0 in {
1457 let hasSideEffects = 0, isMoveReg = 1 in {
14581458 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
14591459 "mov{b}\t{$src, $dst|$dst, $src}", []>;
14601460 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
16231623 } // hasSideEffects = 0
16241624
16251625 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1626 SchedRW = [WriteMove] in {
1626 SchedRW = [WriteMove], isMoveReg = 1 in {
16271627 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
16281628 "mov{b}\t{$src, $dst|$dst, $src}", []>,
16291629 FoldGenData<"MOV8rr">;
16721672 // that they can be used for copying and storing h registers, which can't be
16731673 // encoded when a REX prefix is present.
16741674 let isCodeGenOnly = 1 in {
1675 let hasSideEffects = 0 in
1675 let hasSideEffects = 0, isMoveReg = 1 in
16761676 def MOV8rr_NOREX : I<0x88, MRMDestReg,
16771677 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
16781678 "mov{b}\t{$src, $dst|$dst, $src}", []>,
214214 "movq\t{$src, $dst|$dst, $src}",
215215 [(set GR64:$dst, (bitconvert VR64:$src))]>,
216216 Sched<[WriteVecMoveToGpr]>;
217 let SchedRW = [WriteVecMove], hasSideEffects = 0 in {
217 let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in {
218218 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
219219 "movq\t{$src, $dst|$dst, $src}", []>;
220220 let isCodeGenOnly = 1, ForceDisassemble = 1 in
221221 def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
222222 "movq\t{$src, $dst|$dst, $src}", []>,
223223 FoldGenData<"MMX_MOVQ64rr">;
224 } // SchedRW, hasSideEffects
224 } // SchedRW, hasSideEffects, isMoveReg
225225 } // isBitcast
226226
227227 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
407407 X86MemOperand x86memop, PatFrag ld_frag,
408408 string asm, Domain d,
409409 X86SchedWriteMoveLS sched> {
410 let hasSideEffects = 0 in
410 let hasSideEffects = 0, isMoveReg = 1 in
411411 def rr : PI
412412 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
413413 Sched<[sched.RR]>;
504504 } // Predicate
505505
506506 // For disassembler
507 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
507 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
508 isMoveReg = 1 in {
508509 let SchedRW = [SchedWriteFMoveLS.XMM.RR] in {
509510 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
510511 (ins VR128:$src),
580581
581582 // For disassembler
582583 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
583 SchedRW = [SchedWriteFMoveLS.XMM.RR] in {
584 isMoveReg = 1, SchedRW = [SchedWriteFMoveLS.XMM.RR] in {
584585 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
585586 "movaps\t{$src, $dst|$dst, $src}", []>,
586587 FoldGenData<"MOVAPSrr">;
305305 isIndirectBranch = R->getValueAsBit("isIndirectBranch");
306306 isCompare = R->getValueAsBit("isCompare");
307307 isMoveImm = R->getValueAsBit("isMoveImm");
308 isMoveReg = R->getValueAsBit("isMoveReg");
308309 isBitcast = R->getValueAsBit("isBitcast");
309310 isSelect = R->getValueAsBit("isSelect");
310311 isBarrier = R->getValueAsBit("isBarrier");
225225 bool isIndirectBranch : 1;
226226 bool isCompare : 1;
227227 bool isMoveImm : 1;
228 bool isMoveReg : 1;
228229 bool isBitcast : 1;
229230 bool isSelect : 1;
230231 bool isBarrier : 1;
488488 if (Inst.isIndirectBranch) OS << "|(1ULL<
489489 if (Inst.isCompare) OS << "|(1ULL<
490490 if (Inst.isMoveImm) OS << "|(1ULL<
491 if (Inst.isMoveReg) OS << "|(1ULL<
491492 if (Inst.isBitcast) OS << "|(1ULL<
492493 if (Inst.isAdd) OS << "|(1ULL<
493494 if (Inst.isSelect) OS << "|(1ULL<