llvm.org GIT mirror llvm / 4d6ccb5
More dead code removal (using -Wunreachable-code) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8 David Blaikie 7 years ago
110 changed file(s) with 207 addition(s) and 470 deletion(s). Raw diff Collapse all Expand all
445445 case 8: return MVT::v8i8;
446446 case 16: return MVT::v16i8;
447447 }
448 return MVT::INVALID_SIMPLE_VALUE_TYPE;
449448 }
450449
451450 /// changeVectorElementTypeToInteger - Return a vector with the same number
5757 /// Returns the maximum size and alignment for a call stub on this target.
5858 virtual StubLayout getStubLayout() {
5959 llvm_unreachable("This target doesn't implement getStubLayout!");
60 StubLayout Result = {0, 0};
61 return Result;
6260 }
6361
6462 /// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
296296 return VT;
297297 }
298298 }
299 return VT;
300299 }
301300
302301 /// getVectorTypeBreakdown - Vector types are broken down into some number of
11241124 if (Ty->isDoubleTy())
11251125 return ConstantFP::get(Ty->getContext(), APFloat(V));
11261126 llvm_unreachable("Can only constant fold float/double");
1127 return 0; // dummy return to suppress warning
11281127 }
11291128
11301129 static Constant *ConstantFoldBinaryFP(double (*NativeFP)(double, double),
11411140 if (Ty->isDoubleTy())
11421141 return ConstantFP::get(Ty->getContext(), APFloat(V));
11431142 llvm_unreachable("Can only constant fold float/double");
1144 return 0; // dummy return to suppress warning
11451143 }
11461144
11471145 /// ConstantFoldConvertToInt - Attempt to an SSE floating point to integer
9090 if (StoreInst *i = dyn_cast(I))
9191 return i->getPointerOperand();
9292 llvm_unreachable("Value is no load or store instruction!");
93 // Never reached.
94 return 0;
9593 }
9694
9795 static AliasAnalysis::AliasResult UnderlyingObjectsAlias(AliasAnalysis *AA,
328328
329329 NewLoadByteSize <<= 1;
330330 }
331
332 return 0;
333331 }
334332
335333 namespace {
7373 errs() << *I << '\n';
7474 llvm_unreachable("Either something is missing from InstInputs or "
7575 "CanPHITrans is wrong.");
76 return false;
7776 }
7877
7978 // Validate the operands of the instruction.
10099 for (unsigned i = 0, e = InstInputs.size(); i != e; ++i)
101100 errs() << " InstInput #" << i << " is " << *InstInputs[i] << "\n";
102101 llvm_unreachable("This is unexpected.");
103 return false;
104102 }
105103
106104 // a-ok.
258258 return cast(this)->getType();
259259 case scCouldNotCompute:
260260 llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
261 return 0;
262 default: break;
263 }
264 llvm_unreachable("Unknown SCEV kind!");
265 return 0;
261 default:
262 llvm_unreachable("Unknown SCEV kind!");
263 }
266264 }
267265
268266 bool SCEV::isZero() const {
610608 }
611609
612610 default:
613 break;
611 llvm_unreachable("Unknown SCEV kind!");
614612 }
615
616 llvm_unreachable("Unknown SCEV kind!");
617 return 0;
618613 }
619614 };
620615 }
53185313 }
53195314
53205315 llvm_unreachable("Unknown SCEV type!");
5321 return 0;
53225316 }
53235317
53245318 /// getSCEVAtScope - This is a convenience function which does
59495943 switch (Pred) {
59505944 default:
59515945 llvm_unreachable("Unexpected ICmpInst::Predicate value!");
5952 break;
59535946 case ICmpInst::ICMP_SGT:
59545947 Pred = ICmpInst::ICMP_SLT;
59555948 std::swap(LHS, RHS);
68006793 return LoopInvariant;
68016794 case scCouldNotCompute:
68026795 llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
6803 return LoopVariant;
6804 default: break;
6805 }
6806 llvm_unreachable("Unknown SCEV kind!");
6807 return LoopVariant;
6796 default: llvm_unreachable("Unknown SCEV kind!");
6797 }
68086798 }
68096799
68106800 bool ScalarEvolution::isLoopInvariant(const SCEV *S, const Loop *L) {
68866876 return ProperlyDominatesBlock;
68876877 case scCouldNotCompute:
68886878 llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
6889 return DoesNotDominateBlock;
6890 default: break;
6891 }
6892 llvm_unreachable("Unknown SCEV kind!");
6893 return DoesNotDominateBlock;
6879 default:
6880 llvm_unreachable("Unknown SCEV kind!");
6881 }
68946882 }
68956883
68966884 bool ScalarEvolution::dominates(const SCEV *S, const BasicBlock *BB) {
69366924 return false;
69376925 case scCouldNotCompute:
69386926 llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
6939 return false;
6940 default: break;
6941 }
6942 llvm_unreachable("Unknown SCEV kind!");
6943 return false;
6927 default:
6928 llvm_unreachable("Unknown SCEV kind!");
6929 }
69446930 }
69456931
69466932 void ScalarEvolution::forgetMemoizedResults(const SCEV *S) {
649649 return RelevantLoops[D] = Result;
650650 }
651651 llvm_unreachable("Unexpected SCEV type!");
652 return 0;
653652 }
654653
655654 namespace {
189189 }
190190
191191 llvm_unreachable("Unexpected SCEV kind!");
192 return 0;
193192 }
194193
195194 /// Manage recursive transformation across an expression DAG. Revisiting
10421042 case lltok::kw_cc: {
10431043 unsigned ArbitraryCC;
10441044 Lex.Lex();
1045 if (ParseUInt32(ArbitraryCC)) {
1045 if (ParseUInt32(ArbitraryCC))
10461046 return true;
1047 } else
1048 CC = static_cast(ArbitraryCC);
1049 return false;
1050 }
1051 break;
1047 CC = static_cast(ArbitraryCC);
1048 return false;
1049 }
10521050 }
10531051
10541052 Lex.Lex();
166166 case FCmpInst::FCMP_ULE: return ISD::SETULE;
167167 case FCmpInst::FCMP_UNE: return ISD::SETUNE;
168168 case FCmpInst::FCMP_TRUE: return ISD::SETTRUE;
169 default: break;
170 }
171 llvm_unreachable("Invalid FCmp predicate opcode!");
172 return ISD::SETFALSE;
169 default: llvm_unreachable("Invalid FCmp predicate opcode!");
170 }
173171 }
174172
175173 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) {
180178 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE;
181179 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT;
182180 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE;
183 default: break;
184 }
185 return CC;
181 default: return CC;
182 }
186183 }
187184
188185 /// getICmpCondCode - Return the ISD condition code corresponding to
202199 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
203200 default:
204201 llvm_unreachable("Invalid ICmp predicate opcode!");
205 return ISD::SETNE;
206202 }
207203 }
208204
11351135 const MCExpr *Value = 0;
11361136 switch (MJTI->getEntryKind()) {
11371137 case MachineJumpTableInfo::EK_Inline:
1138 llvm_unreachable("Cannot emit EK_Inline jump table entry"); break;
1138 llvm_unreachable("Cannot emit EK_Inline jump table entry");
11391139 case MachineJumpTableInfo::EK_Custom32:
11401140 Value = TM.getTargetLowering()->LowerCustomJumpTableEntry(MJTI, MBB, UID,
11411141 OutContext);
14381438 const ConstantExpr *CE = dyn_cast(CV);
14391439 if (CE == 0) {
14401440 llvm_unreachable("Unknown constant value to lower!");
1441 return MCConstantExpr::Create(0, Ctx);
14421441 }
14431442
14441443 switch (CE->getOpcode()) {
14601459 !AP.MF ? 0 : AP.MF->getFunction()->getParent());
14611460 report_fatal_error(OS.str());
14621461 }
1463 return MCConstantExpr::Create(0, Ctx);
14641462 case Instruction::GetElementPtr: {
14651463 const TargetData &TD = *AP.TM.getTargetData();
14661464 // Generate a symbolic expression for the byte address
21392137 }
21402138
21412139 report_fatal_error("no GCMetadataPrinter registered for GC: " + Twine(Name));
2142 return 0;
2143 }
2140 }
223223 case dwarf::DW_FORM_udata: return MCAsmInfo::getULEB128Size(Integer);
224224 case dwarf::DW_FORM_sdata: return MCAsmInfo::getSLEB128Size(Integer);
225225 case dwarf::DW_FORM_addr: return AP->getTargetData().getPointerSize();
226 default: llvm_unreachable("DIE Value form not supported yet"); break;
227 }
228 return 0;
226 default: llvm_unreachable("DIE Value form not supported yet");
227 }
229228 }
230229
231230 #ifndef NDEBUG
339338 case dwarf::DW_FORM_block2: return Size + sizeof(int16_t);
340339 case dwarf::DW_FORM_block4: return Size + sizeof(int32_t);
341340 case dwarf::DW_FORM_block: return Size + MCAsmInfo::getULEB128Size(Size);
342 default: llvm_unreachable("Improper form for block"); break;
343 }
344 return 0;
341 default: llvm_unreachable("Improper form for block");
342 }
345343 }
346344
347345 #ifndef NDEBUG
482482 // an object with itself.
483483 #ifndef _GLIBCXX_DEBUG
484484 llvm_unreachable("Predecessor appears twice");
485 #else
486 return false;
485487 #endif
486 return false;
487488 }
488489 }
489490
113113 bool GCStrategy::performCustomLowering(Function &F) {
114114 dbgs() << "gc " << getName() << " must override performCustomLowering.\n";
115115 llvm_unreachable(0);
116 return 0;
117116 }
118117
119118
120119 bool GCStrategy::findCustomSafePoints(GCFunctionInfo& FI, MachineFunction &F) {
121120 dbgs() << "gc " << getName() << " must override findCustomSafePoints.\n";
122121 llvm_unreachable(0);
123 return 0;
124122 }
125123
126124
213213 }
214214
215215 llvm_unreachable("MachineOperand::getParent() failure?");
216 return 0;
217216 }
218217
219218 /// RewriteUse - Rewrite a use of the symbolic value. This handles PHI nodes,
8686 this == getJumpTable())
8787 return true;
8888 llvm_unreachable("Unknown PseudoSourceValue!");
89 return false;
9089 }
9190
9291 bool PseudoSourceValue::isAliased(const MachineFrameInfo *MFI) const {
9695 this == getJumpTable())
9796 return false;
9897 llvm_unreachable("Unknown PseudoSourceValue!");
99 return true;
10098 }
10199
102100 bool PseudoSourceValue::mayAlias(const MachineFrameInfo *MFI) const {
800800 Node->dump();
801801 #endif
802802 llvm_unreachable("This target-independent node should have been selected!");
803 break;
804803 case ISD::EntryToken:
805804 llvm_unreachable("EntryToken should have been excluded from the schedule!");
806 break;
807805 case ISD::MERGE_VALUES:
808806 case ISD::TokenFactor: // fall thru
809807 break;
24372437 switch (Opc) {
24382438 default:
24392439 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2440 break;
24412440 case ISD::ATOMIC_SWAP:
24422441 switch (VT.SimpleTy) {
24432442 default: llvm_unreachable("Unexpected value type for atomic!");
11781178 switch (Opc) {
11791179 default:
11801180 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1181 break;
11821181 case ISD::ATOMIC_SWAP:
11831182 switch (VT.SimpleTy) {
11841183 default: llvm_unreachable("Unexpected value type for atomic!");
15001499 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
15011500 return true;
15021501 }
1503
1504 return false;
15051502 }
15061503
15071504 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
22442244
22452245 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
22462246 if (Tmp2 == 1) return 1;
2247 return std::min(Tmp, Tmp2)-1;
2248 break;
2247 return std::min(Tmp, Tmp2)-1;
22492248
22502249 case ISD::SUB:
22512250 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
22742273 // is, at worst, one more bit than the inputs.
22752274 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
22762275 if (Tmp == 1) return 1; // Early out.
2277 return std::min(Tmp, Tmp2)-1;
2278 break;
2276 return std::min(Tmp, Tmp2)-1;
22792277 case ISD::TRUNCATE:
22802278 // FIXME: it's tricky to do anything useful for this, but it is an important
22812279 // case for targets like X86.
31593157 case ISD::SELECT:
31603158 if (N1C) {
31613159 if (N1C->getZExtValue())
3162 return N2; // select true, X, Y -> X
3163 else
3164 return N3; // select false, X, Y -> Y
3160 return N2; // select true, X, Y -> X
3161 return N3; // select false, X, Y -> Y
31653162 }
31663163
31673164 if (N2 == N3) return N2; // select C, X, X -> X
31683165 break;
31693166 case ISD::VECTOR_SHUFFLE:
31703167 llvm_unreachable("should use getVectorShuffle constructor!");
3171 break;
31723168 case ISD::INSERT_SUBVECTOR: {
31733169 SDValue Index = N3;
31743170 if (VT.isSimple() && N1.getValueType().isSimple()
205205 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
206206
207207 llvm_unreachable("Unknown mismatch!");
208 return SDValue();
209208 }
210209
211210 /// getCopyFromParts - Create a value that contains the specified legal parts
11271126 }
11281127
11291128 llvm_unreachable("Can't get register for value!");
1130 return SDValue();
11311129 }
11321130
11331131 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
33783376 DebugLoc dl = getCurDebugLoc();
33793377 ISD::NodeType NT;
33803378 switch (I.getOperation()) {
3381 default: llvm_unreachable("Unknown atomicrmw operation"); return;
3379 default: llvm_unreachable("Unknown atomicrmw operation");
33823380 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
33833381 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
33843382 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
50635061 case Intrinsic::gcread:
50645062 case Intrinsic::gcwrite:
50655063 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5066 return 0;
50675064 case Intrinsic::flt_rounds:
50685065 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
50695066 return 0;
66046601
66056602 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
66066603 llvm_unreachable("LowerOperation not implemented for this target!");
6607 return SDValue();
66086604 }
66096605
66106606 void
248248 "TargetLowering::EmitInstrWithCustomInserter!";
249249 #endif
250250 llvm_unreachable(0);
251 return 0;
252251 }
253252
254253 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
980979 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
981980 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
982981 }
983 return;
984982 }
985983 #endif
986984
10711071 break;
10721072 case SM_Speed:
10731073 llvm_unreachable("Spill mode 'speed' not implemented yet");
1074 break;
10751074 }
10761075
10771076 // Transfer the simply mapped values, check if any are skipped.
5252 report_fatal_error("We do not support this DWARF encoding yet!");
5353 case dwarf::DW_EH_PE_absptr:
5454 return Mang->getSymbol(GV);
55 break;
5655 case dwarf::DW_EH_PE_pcrel: {
5756 return getContext().GetOrCreateSymbol(StringRef("DW.ref.") +
5857 Mang->getSymbol(GV)->getName());
59 break;
6058 }
6159 }
6260 }
360358 report_fatal_error("Global variable '" + GV->getName() +
361359 "' has an invalid section specifier '" +
362360 GV->getSection() + "': " + ErrorCode + ".");
363 // Fall back to dropping it into the data section.
364 return DataSection;
365361 }
366362
367363 // Get the section.
202202 AbbrevDecl = NULL;
203203 return true; // NULL debug tag entry
204204 }
205
206 return false;
207205 }
208206
209207 bool
7575 return unwrap(GenVal)->DoubleVal;
7676 default:
7777 llvm_unreachable("LLVMGenericValueToFloat supports only float and double.");
78 break;
79 }
80 return 0; // Not reached
78 }
8179 }
8280
8381 void LLVMDisposeGenericValue(LLVMGenericValueRef GenVal) {
12531253 default:
12541254 dbgs() << "Unhandled ConstantExpr: " << *CE << "\n";
12551255 llvm_unreachable(0);
1256 return GenericValue();
12571256 }
12581257 return Dest;
12591258 }
408408 break;
409409 }
410410 }
411 return GV;
412411 }
413412
414413 // int printf(const char *, ...) - a very rough implementation to make output
474474 case Type::FP128TyID:
475475 case Type::PPC_FP128TyID:
476476 llvm_unreachable("long double not supported yet");
477 return rv;
478477 case Type::PointerTyID:
479478 return PTOGV(((void*(*)())(intptr_t)FPtr)());
480479 }
8989
9090 void *MCJIT::getPointerToBasicBlock(BasicBlock *BB) {
9191 report_fatal_error("not yet implemented");
92 return 0;
9392 }
9493
9594 void *MCJIT::getPointerToFunction(Function *F) {
208207 case Type::FP128TyID:
209208 case Type::PPC_FP128TyID:
210209 llvm_unreachable("long double not supported yet");
211 return rv;
212210 case Type::PointerTyID:
213211 return PTOGV(((void*(*)())(intptr_t)FPtr)());
214212 }
7171 case macho::RIT_X86_64_TLV:
7272 return Error("Relocation type not implemented yet!");
7373 }
74 return false;
7574 }
7675
7776 bool RuntimeDyldMachO::
1717 #include "llvm/MC/MCRegisterInfo.h"
1818 #include "llvm/Support/MemoryObject.h"
1919 #include "llvm/Support/TargetRegistry.h"
20 #include "llvm/Support/ErrorHandling.h"
2021
2122 namespace llvm {
2223 class Target;
162163 return Size;
163164 }
164165 }
165 return 0;
166 llvm_unreachable("Invalid DecodeStatus!");
166167 }
199199 return 0;
200200 }
201201 } // switch (operandType)
202 break;
203202 case Triple::arm:
204203 case Triple::thumb:
205204 switch (operandType) {
235234 return 0;
236235 }
237236 }
238 break;
239237 }
240
241 return -1;
242238 }
243239
244240 int EDOperand::isRegister() {
826826 if (!ModifiedRes) {
827827 return TokError("invalid modifier '" + getTok().getIdentifier() +
828828 "' (no symbols present)");
829 return true;
830829 }
831830
832831 Res = ModifiedRes;
9595 virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Directory,
9696 StringRef Filename) {
9797 report_fatal_error("unsupported directive in pure streamer");
98 return false;
9998 }
10099
101100 /// @}
252252
253253 default:
254254 llvm_unreachable("unsupported attribute");
255 break;
256255 }
257256 }
258257
99 #include "llvm/ADT/Triple.h"
1010 #include "llvm/ADT/SmallString.h"
1111 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/Support/ErrorHandling.h"
1213 #include
1314 using namespace llvm;
1415
4142 case amdil: return "amdil";
4243 }
4344
44 return "";
45 llvm_unreachable("Invalid ArchType!");
4546 }
4647
4748 const char *Triple::getArchTypePrefix(ArchType Kind) {
8586 case SCEI: return "scei";
8687 }
8788
88 return "";
89 llvm_unreachable("Invalid VendorType!");
8990 }
9091
9192 const char *Triple::getOSTypeName(OSType Kind) {
114115 case NativeClient: return "nacl";
115116 }
116117
117 return "";
118 llvm_unreachable("Invalid OSType");
118119 }
119120
120121 const char *Triple::getEnvironmentTypeName(EnvironmentType Kind) {
128129 case ANDROIDEABI: return "androideabi";
129130 }
130131
131 return "";
132 llvm_unreachable("Invalid EnvironmentType!");
132133 }
133134
134135 Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
317317 // Some of these can also begin values but we disallow those cases
318318 // because they are unlikely to be useful.
319319 return StringInit::get(GetNewAnonymousName());
320 break;
321320 default:
322321 break;
323322 }
721720 default:
722721 TokError("unknown operation");
723722 return 0;
724 break;
725723 case tgtok::XHead:
726724 case tgtok::XTail:
727725 case tgtok::XEmpty:
10251023 CurMultiClass);
10261024 }
10271025 }
1028 TokError("could not parse operation");
1029 return 0;
10301026 }
10311027
10321028 /// ParseOperatorType - Parse a type for an operator. This returns
10871083 // still exists in some .td files. Ignore it.
10881084 Lex.Lex(); // Skip '#'.
10891085 return ParseSimpleValue(CurRec, ItemType, Mode);
1090 break;
10911086 case tgtok::IntVal: R = IntInit::get(Lex.getCurIntVal()); Lex.Lex(); break;
10921087 case tgtok::StrVal: {
10931088 std::string Val = Lex.getCurStrVal();
823823 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
824824 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
825825 }
826 return MCSymbolRefExpr::VK_None;
826 llvm_unreachable("Invalid ARMCPModifier!");
827827 }
828828
829829 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
557557 if (MCID.getSize())
558558 return MCID.getSize();
559559
560 // If this machine instr is an inline asm, measure it.
561 if (MI->getOpcode() == ARM::INLINEASM)
562 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
563 if (MI->isLabel())
564 return 0;
565 unsigned Opc = MI->getOpcode();
566 switch (Opc) {
567 case TargetOpcode::IMPLICIT_DEF:
568 case TargetOpcode::KILL:
569 case TargetOpcode::PROLOG_LABEL:
570 case TargetOpcode::EH_LABEL:
571 case TargetOpcode::DBG_VALUE:
572 return 0;
573 case TargetOpcode::BUNDLE:
574 return getInstBundleLength(MI);
575 case ARM::MOVi16_ga_pcrel:
576 case ARM::MOVTi16_ga_pcrel:
577 case ARM::t2MOVi16_ga_pcrel:
578 case ARM::t2MOVTi16_ga_pcrel:
579 return 4;
580 case ARM::MOVi32imm:
581 case ARM::t2MOVi32imm:
582 return 8;
583 case ARM::CONSTPOOL_ENTRY:
584 // If this machine instr is a constant pool entry, its size is recorded as
585 // operand #2.
586 return MI->getOperand(2).getImm();
587 case ARM::Int_eh_sjlj_longjmp:
588 return 16;
589 case ARM::tInt_eh_sjlj_longjmp:
590 return 10;
591 case ARM::Int_eh_sjlj_setjmp:
592 case ARM::Int_eh_sjlj_setjmp_nofp:
593 return 20;
594 case ARM::tInt_eh_sjlj_setjmp:
595 case ARM::t2Int_eh_sjlj_setjmp:
596 case ARM::t2Int_eh_sjlj_setjmp_nofp:
597 return 12;
598 case ARM::BR_JTr:
599 case ARM::BR_JTm:
600 case ARM::BR_JTadd:
601 case ARM::tBR_JTr:
602 case ARM::t2BR_JT:
603 case ARM::t2TBB_JT:
604 case ARM::t2TBH_JT: {
605 // These are jumptable branches, i.e. a branch followed by an inlined
606 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
607 // entry is one byte; TBH two byte each.
608 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
609 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
610 unsigned NumOps = MCID.getNumOperands();
611 MachineOperand JTOP =
612 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
613 unsigned JTI = JTOP.getIndex();
614 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
615 assert(MJTI != 0);
616 const std::vector &JT = MJTI->getJumpTables();
617 assert(JTI < JT.size());
618 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
619 // 4 aligned. The assembler / linker may add 2 byte padding just before
620 // the JT entries. The size does not include this padding; the
621 // constant islands pass does separate bookkeeping for it.
622 // FIXME: If we know the size of the function is less than (1 << 16) *2
623 // bytes, we can use 16-bit entries instead. Then there won't be an
624 // alignment issue.
625 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
626 unsigned NumEntries = getNumJTEntries(JT, JTI);
627 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
628 // Make sure the instruction that follows TBB is 2-byte aligned.
629 // FIXME: Constant island pass should insert an "ALIGN" instruction
630 // instead.
631 ++NumEntries;
632 return NumEntries * EntrySize + InstSize;
633 }
634 default:
635 // Otherwise, pseudo-instruction sizes are zero.
636 return 0;
637 }
638 return 0; // Not reached
560 // If this machine instr is an inline asm, measure it.
561 if (MI->getOpcode() == ARM::INLINEASM)
562 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
563 if (MI->isLabel())
564 return 0;
565 unsigned Opc = MI->getOpcode();
566 switch (Opc) {
567 case TargetOpcode::IMPLICIT_DEF:
568 case TargetOpcode::KILL:
569 case TargetOpcode::PROLOG_LABEL:
570 case TargetOpcode::EH_LABEL:
571 case TargetOpcode::DBG_VALUE:
572 return 0;
573 case TargetOpcode::BUNDLE:
574 return getInstBundleLength(MI);
575 case ARM::MOVi16_ga_pcrel:
576 case ARM::MOVTi16_ga_pcrel:
577 case ARM::t2MOVi16_ga_pcrel:
578 case ARM::t2MOVTi16_ga_pcrel:
579 return 4;
580 case ARM::MOVi32imm:
581 case ARM::t2MOVi32imm:
582 return 8;
583 case ARM::CONSTPOOL_ENTRY:
584 // If this machine instr is a constant pool entry, its size is recorded as
585 // operand #2.
586 return MI->getOperand(2).getImm();
587 case ARM::Int_eh_sjlj_longjmp:
588 return 16;
589 case ARM::tInt_eh_sjlj_longjmp:
590 return 10;
591 case ARM::Int_eh_sjlj_setjmp:
592 case ARM::Int_eh_sjlj_setjmp_nofp:
593 return 20;
594 case ARM::tInt_eh_sjlj_setjmp:
595 case ARM::t2Int_eh_sjlj_setjmp:
596 case ARM::t2Int_eh_sjlj_setjmp_nofp:
597 return 12;
598 case ARM::BR_JTr:
599 case ARM::BR_JTm:
600 case ARM::BR_JTadd:
601 case ARM::tBR_JTr:
602 case ARM::t2BR_JT:
603 case ARM::t2TBB_JT:
604 case ARM::t2TBH_JT: {
605 // These are jumptable branches, i.e. a branch followed by an inlined
606 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
607 // entry is one byte; TBH two byte each.
608 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
609 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
610 unsigned NumOps = MCID.getNumOperands();
611 MachineOperand JTOP =
612 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
613 unsigned JTI = JTOP.getIndex();
614 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
615 assert(MJTI != 0);
616 const std::vector &JT = MJTI->getJumpTables();
617 assert(JTI < JT.size());
618 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
619 // 4 aligned. The assembler / linker may add 2 byte padding just before
620 // the JT entries. The size does not include this padding; the
621 // constant islands pass does separate bookkeeping for it.
622 // FIXME: If we know the size of the function is less than (1 << 16) *2
623 // bytes, we can use 16-bit entries instead. Then there won't be an
624 // alignment issue.
625 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
626 unsigned NumEntries = getNumJTEntries(JT, JTI);
627 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
628 // Make sure the instruction that follows TBB is 2-byte aligned.
629 // FIXME: Constant island pass should insert an "ALIGN" instruction
630 // instead.
631 ++NumEntries;
632 return NumEntries * EntrySize + InstSize;
633 }
634 default:
635 // Otherwise, pseudo-instruction sizes are zero.
636 return 0;
637 }
639638 }
640639
641640 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
14711470 int llvm::getMatchingCondBranchOpcode(int Opc) {
14721471 if (Opc == ARM::B)
14731472 return ARM::Bcc;
1474 else if (Opc == ARM::tB)
1473 if (Opc == ARM::tB)
14751474 return ARM::tBcc;
1476 else if (Opc == ARM::t2B)
1477 return ARM::t2Bcc;
1475 if (Opc == ARM::t2B)
1476 return ARM::t2Bcc;
14781477
14791478 llvm_unreachable("Unknown unconditional branch opcode!");
1480 return 0;
14811479 }
14821480
14831481
16501648 }
16511649 default:
16521650 llvm_unreachable("Unsupported addressing mode!");
1653 break;
16541651 }
16551652
16561653 Offset += InstrOffs * Scale;
20122009 switch (Opc) {
20132010 default:
20142011 llvm_unreachable("Unexpected multi-uops instruction!");
2015 break;
20162012 case ARM::VLDMQIA:
20172013 case ARM::VSTMQIA:
20182014 return 2;
568568
569569 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
570570 llvm_unreachable("What is the exception register");
571 return 0;
572571 }
573572
574573 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
575574 llvm_unreachable("What is the exception handler register");
576 return 0;
577575 }
578576
579577 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
822820 }
823821 default:
824822 llvm_unreachable("Unsupported addressing mode!");
825 break;
826823 }
827824
828825 return InstrOffs * Scale;
10181015 break;
10191016 default:
10201017 llvm_unreachable("Unsupported addressing mode!");
1021 break;
10221018 }
10231019
10241020 Offset += getFrameIndexInstrOffset(MI, i);
405405 case ARM_AM::ror:
406406 case ARM_AM::rrx: return 3;
407407 }
408 return 0;
409408 }
410409
411410 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
531530 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
532531 default: {
533532 llvm_unreachable("Unhandled instruction encoding format!");
534 break;
535533 }
536534 case ARMII::MiscFrm:
537535 if (MI.getOpcode() == ARM::LEApcrelJT) {
540538 break;
541539 }
542540 llvm_unreachable("Unhandled instruction encoding!");
543 break;
544541 case ARMII::Pseudo:
545542 emitPseudoInstruction(MI);
546543 break;
729729 switch (Opc) {
730730 default:
731731 llvm_unreachable("Unknown addressing mode for CP reference!");
732 break;
733732
734733 // Taking the address of a CP entry.
735734 case ARM::LEApcrel:
4040 case ARM::reloc_arm_machine_cp_entry:
4141 case ARM::reloc_arm_jt_base:
4242 case ARM::reloc_arm_pic_jt:
43 assert(0 && "unsupported ARM relocation type"); break;
43 assert(0 && "unsupported ARM relocation type"); return 0;
4444
45 case ARM::reloc_arm_branch: return ELF::R_ARM_CALL; break;
46 case ARM::reloc_arm_movt: return ELF::R_ARM_MOVT_ABS; break;
47 case ARM::reloc_arm_movw: return ELF::R_ARM_MOVW_ABS_NC; break;
45 case ARM::reloc_arm_branch: return ELF::R_ARM_CALL;
46 case ARM::reloc_arm_movt: return ELF::R_ARM_MOVT_ABS;
47 case ARM::reloc_arm_movw: return ELF::R_ARM_MOVW_ABS_NC;
4848 default:
49 llvm_unreachable("unknown ARM relocation type"); break;
49 llvm_unreachable("unknown ARM relocation type");
5050 }
51 return 0;
5251 }
5352
5453 long int ARMELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
13391339 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
13401340 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
13411341 }
1342
1343 return false;
13441342 }
13451343
13461344 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
23392339 return SelectCall(&I, "memset");
23402340 }
23412341 }
2342 return false;
23432342 }
23442343
23452344 bool ARMFastISel::SelectTrunc(const Instruction *I) {
21912191 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
21922192 default:
21932193 llvm_unreachable("Unknown so_reg opcode!");
2194 break;
21952194 }
21962195 SDValue SOShImm =
21972196 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
34933493
34943494 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
34953495 switch (SetCCOpcode) {
3496 default: llvm_unreachable("Illegal FP comparison"); break;
3496 default: llvm_unreachable("Illegal FP comparison");
34973497 case ISD::SETUNE:
34983498 case ISD::SETNE: Invert = true; // Fallthrough
34993499 case ISD::SETOEQ:
35323532 } else {
35333533 // Integer comparisons.
35343534 switch (SetCCOpcode) {
3535 default: llvm_unreachable("Illegal integer comparison"); break;
3535 default: llvm_unreachable("Illegal integer comparison");
35363536 case ISD::SETNE: Invert = true;
35373537 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
35383538 case ISD::SETLT: Swap = true;
37393739
37403740 default:
37413741 llvm_unreachable("unexpected size for isNEONModifiedImm");
3742 return SDValue();
37433742 }
37443743
37453744 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
50625061 case ISD::ATOMIC_LOAD:
50635062 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
50645063 }
5065 return SDValue();
50665064 }
50675065
50685066 /// ReplaceNodeResults - Replace the results of node with an illegal result
50745072 switch (N->getOpcode()) {
50755073 default:
50765074 llvm_unreachable("Don't know how to custom expand this!");
5077 break;
50785075 case ISD::BITCAST:
50795076 Res = ExpandBITCAST(N, DAG);
50805077 break;
83738370 if (Scale & 1) return false;
83748371 return isPowerOf2_32(Scale);
83758372 }
8376 break;
83778373 }
83788374 return true;
83798375 }
143143 case ARM_AM::db: return ARM::LDMDB;
144144 case ARM_AM::ib: return ARM::LDMIB;
145145 }
146 break;
147146 case ARM::STRi12:
148147 ++NumSTMGened;
149148 switch (Mode) {
153152 case ARM_AM::db: return ARM::STMDB;
154153 case ARM_AM::ib: return ARM::STMIB;
155154 }
156 break;
157155 case ARM::t2LDRi8:
158156 case ARM::t2LDRi12:
159157 ++NumLDMGened;
162160 case ARM_AM::ia: return ARM::t2LDMIA;
163161 case ARM_AM::db: return ARM::t2LDMDB;
164162 }
165 break;
166163 case ARM::t2STRi8:
167164 case ARM::t2STRi12:
168165 ++NumSTMGened;
171168 case ARM_AM::ia: return ARM::t2STMIA;
172169 case ARM_AM::db: return ARM::t2STMDB;
173170 }
174 break;
175171 case ARM::VLDRS:
176172 ++NumVLDMGened;
177173 switch (Mode) {
179175 case ARM_AM::ia: return ARM::VLDMSIA;
180176 case ARM_AM::db: return 0; // Only VLDMSDB_UPD exists.
181177 }
182 break;
183178 case ARM::VSTRS:
184179 ++NumVSTMGened;
185180 switch (Mode) {
187182 case ARM_AM::ia: return ARM::VSTMSIA;
188183 case ARM_AM::db: return 0; // Only VSTMSDB_UPD exists.
189184 }
190 break;
191185 case ARM::VLDRD:
192186 ++NumVLDMGened;
193187 switch (Mode) {
195189 case ARM_AM::ia: return ARM::VLDMDIA;
196190 case ARM_AM::db: return 0; // Only VLDMDDB_UPD exists.
197191 }
198 break;
199192 case ARM::VSTRD:
200193 ++NumVSTMGened;
201194 switch (Mode) {
203196 case ARM_AM::ia: return ARM::VSTMDIA;
204197 case ARM_AM::db: return 0; // Only VSTMDDB_UPD exists.
205198 }
206 break;
207 }
208
209 return 0;
199 }
210200 }
211201
212202 namespace llvm {
261251 case ARM::STMIB_UPD:
262252 return ARM_AM::ib;
263253 }
264
265 return ARM_AM::bad_am_submode;
266254 }
267255
268256 } // end namespace ARM_AM
605593 case ARM_AM::da: return ARM::LDMDA_UPD;
606594 case ARM_AM::db: return ARM::LDMDB_UPD;
607595 }
608 break;
609596 case ARM::STMIA:
610597 case ARM::STMDA:
611598 case ARM::STMDB:
617604 case ARM_AM::da: return ARM::STMDA_UPD;
618605 case ARM_AM::db: return ARM::STMDB_UPD;
619606 }
620 break;
621607 case ARM::t2LDMIA:
622608 case ARM::t2LDMDB:
623609 switch (Mode) {
625611 case ARM_AM::ia: return ARM::t2LDMIA_UPD;
626612 case ARM_AM::db: return ARM::t2LDMDB_UPD;
627613 }
628 break;
629614 case ARM::t2STMIA:
630615 case ARM::t2STMDB:
631616 switch (Mode) {
633618 case ARM_AM::ia: return ARM::t2STMIA_UPD;
634619 case ARM_AM::db: return ARM::t2STMDB_UPD;
635620 }
636 break;
637621 case ARM::VLDMSIA:
638622 switch (Mode) {
639623 default: llvm_unreachable("Unhandled submode!");
640624 case ARM_AM::ia: return ARM::VLDMSIA_UPD;
641625 case ARM_AM::db: return ARM::VLDMSDB_UPD;
642626 }
643 break;
644627 case ARM::VLDMDIA:
645628 switch (Mode) {
646629 default: llvm_unreachable("Unhandled submode!");
647630 case ARM_AM::ia: return ARM::VLDMDIA_UPD;
648631 case ARM_AM::db: return ARM::VLDMDDB_UPD;
649632 }
650 break;
651633 case ARM::VSTMSIA:
652634 switch (Mode) {
653635 default: llvm_unreachable("Unhandled submode!");
654636 case ARM_AM::ia: return ARM::VSTMSIA_UPD;
655637 case ARM_AM::db: return ARM::VSTMSDB_UPD;
656638 }
657 break;
658639 case ARM::VSTMDIA:
659640 switch (Mode) {
660641 default: llvm_unreachable("Unhandled submode!");
661642 case ARM_AM::ia: return ARM::VSTMDIA_UPD;
662643 case ARM_AM::db: return ARM::VSTMDDB_UPD;
663644 }
664 break;
665 }
666
667 return 0;
645 }
668646 }
669647
670648 /// MergeBaseUpdateLSMultiple - Fold proceeding/trailing inc/dec of base
785763 return ARM::t2STR_PRE;
786764 default: llvm_unreachable("Unhandled opcode!");
787765 }
788 return 0;
789766 }
790767
791768 static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc,
811788 return ARM::t2STR_POST;
812789 default: llvm_unreachable("Unhandled opcode!");
813790 }
814 return 0;
815791 }
816792
817793 /// MergeBaseUpdateLoadStore - Fold proceeding/trailing inc/dec of base
24992499 // Use the same layout as the tablegen'erated register name matcher. Ugly,
25002500 // but efficient.
25012501 switch (Name.size()) {
2502 default: break;
2502 default: return -1;
25032503 case 2:
25042504 if (Name[0] != CoprocOp)
25052505 return -1;
25162516 case '8': return 8;
25172517 case '9': return 9;
25182518 }
2519 break;
25202519 case 3:
25212520 if (Name[0] != CoprocOp || Name[1] != '1')
25222521 return -1;
25292528 case '4': return 14;
25302529 case '5': return 15;
25312530 }
2532 break;
2533 }
2534
2535 return -1;
2531 }
25362532 }
25372533
25382534 /// parseITCondCode - Try to parse a condition code for an IT instruction.
63836379 }
63846380
63856381 llvm_unreachable("Implement any new match types added!");
6386 return true;
63876382 }
63886383
63896384 /// parseDirective parses the arm specific directives
9696 Out = In;
9797 return false;
9898 }
99 return false;
99 llvm_unreachable("Invalid DecodeStatus!");
100100 }
101101
102102
216216 default: llvm_unreachable("invalid fixup kind!");
217217 case FK_Data_4:
218218 switch (Modifier) {
219 default: llvm_unreachable("Unsupported Modifier"); break;
219 default: llvm_unreachable("Unsupported Modifier");
220220 case MCSymbolRefExpr::VK_ARM_GOT:
221221 Type = ELF::R_ARM_GOT_BREL;
222222 break;
183183 case ARM_AM::ror:
184184 case ARM_AM::rrx: return 3;
185185 }
186 return 0;
186 llvm_unreachable("Invalid ShiftOpc!");
187187 }
188188
189189 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
421421 }
422422
423423 llvm_unreachable("Unable to encode MCOperand!");
424 return 0;
425424 }
426425
427426 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
883882 };
884883
885884 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
886 return 0;
887885 }
888886
889887 uint32_t ARMMCCodeEmitter::
295295 unsigned RelocType = macho::RIT_Vanilla;
296296 if (!getARMFixupKindMachOInfo(Fixup.getKind(), RelocType, Log2Size)) {
297297 report_fatal_error("unknown ARM fixup kind!");
298 return;
299298 }
300299
301300 // If this is a difference or a defined symbol plus an offset, then we need a
552552 default:
553553 llvm_unreachable("Unhandled case in getTypeProps!");
554554 }
555
556 return Out;
557555 }
558556
559557 void CWriter::printConstantArray(ConstantArray *CPA, bool Static) {
742740 break; // These don't need a source cast.
743741 default:
744742 llvm_unreachable("Invalid cast opcode");
745 break;
746743 }
747744 }
748745
247247 switch (MO.getType()) {
248248 case MachineOperand::MO_Immediate:
249249 report_fatal_error("printOp() does not handle immediate values");
250 return;
251250
252251 case MachineOperand::MO_MachineBasicBlock:
253252 O << *MO.getMBB()->getSymbol();
8989 short s_val = (short) i_val;
9090 return i_val == s_val;
9191 }
92
93 return false;
9492 }
9593
9694 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
285283 llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
286284 #else
287285 SelectAddrIdxOnly(Op, Op, Op0, Op1);
286 break;
288287 #endif
289 break;
290288 }
291289
292290 OutOps.push_back(Op0);
325323 val = dyn_cast(N.getNode())->getSExtValue();
326324 Base = CurDAG->getTargetConstant( val , MVT::i32);
327325 Index = Zero;
328 return true; break;
326 return true;
329327 case ISD::ConstantPool:
330328 case ISD::GlobalAddress:
331329 report_fatal_error("SPU SelectAFormAddr: Pool/Global not lowered.");
577575 switch( VT.SimpleTy ) {
578576 case MVT::i8:
579577 return CurDAG->getTargetConstant(SPU::R8CRegClass.getID(), MVT::i32);
580 break;
581578 case MVT::i16:
582579 return CurDAG->getTargetConstant(SPU::R16CRegClass.getID(), MVT::i32);
583 break;
584580 case MVT::i32:
585581 return CurDAG->getTargetConstant(SPU::R32CRegClass.getID(), MVT::i32);
586 break;
587582 case MVT::f32:
588583 return CurDAG->getTargetConstant(SPU::R32FPRegClass.getID(), MVT::i32);
589 break;
590584 case MVT::i64:
591585 return CurDAG->getTargetConstant(SPU::R64CRegClass.getID(), MVT::i32);
592 break;
593586 case MVT::i128:
594587 return CurDAG->getTargetConstant(SPU::GPRCRegClass.getID(), MVT::i32);
595 break;
596588 case MVT::v16i8:
597589 case MVT::v8i16:
598590 case MVT::v4i32:
600592 case MVT::v2i64:
601593 case MVT::v2f64:
602594 return CurDAG->getTargetConstant(SPU::VECREGRegClass.getID(), MVT::i32);
603 break;
604595 default:
605596 assert( false && "add a new case here" );
606 }
607 return SDValue();
597 return SDValue();
598 }
608599 }
609600
610601 //! Convert the operand from a target-independent to a target-specific node
10371037
10381038 llvm_unreachable("LowerConstantPool: Relocation model other than static"
10391039 " not supported.");
1040 return SDValue();
10411040 }
10421041
10431042 //! Alternate entry point for generating the address of a constant pool entry
10681067
10691068 llvm_unreachable("LowerJumpTable: Relocation model other than static"
10701069 " not supported.");
1071 return SDValue();
10721070 }
10731071
10741072 static SDValue
10961094 "not supported.");
10971095 /*NOTREACHED*/
10981096 }
1099
1100 return SDValue();
11011097 }
11021098
11031099 //! Custom lower double precision floating point constants
16951691 SDValue T = DAG.getConstant(Value32, MVT::i32);
16961692 return DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,
16971693 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T));
1698 break;
16991694 }
17001695 case MVT::v2f64: {
17011696 uint64_t f64val = uint64_t(SplatBits);
17051700 SDValue T = DAG.getConstant(f64val, MVT::i64);
17061701 return DAG.getNode(ISD::BITCAST, dl, MVT::v2f64,
17071702 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
1708 break;
17091703 }
17101704 case MVT::v16i8: {
17111705 // 8-bit constants have to be expanded to 16-bits
17321726 return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl);
17331727 }
17341728 }
1735
1736 return SDValue();
17371729 }
17381730
17391731 /*!
20071999 return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0);
20082000 }
20092001 }
2010
2011 return SDValue();
20122002 }
20132003
20142004 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
22212211 switch (Opc) {
22222212 default:
22232213 llvm_unreachable("Unhandled i8 math operator");
2224 /*NOTREACHED*/
2225 break;
22262214 case ISD::ADD: {
22272215 // 8-bit addition: Promote the arguments up to 16-bits and truncate
22282216 // the result:
23072295 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
23082296 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
23092297 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2310 break;
2311 }
2312 }
2313
2314 return SDValue();
2298 }
2299 }
23152300 }
23162301
23172302 //! Lower byte immediate operations for v16i8 vectors:
188188 case Type::VectorTyID: return "packed_";
189189 default: return "other_";
190190 }
191 return "unknown_";
192191 }
193192
194193 void CppWriter::error(const std::string& msg) {
222222 case MachineOperand::MO_Immediate:
223223 dbgs() << "printOp() does not handle immediate values\n";
224224 abort();
225 return;
226225
227226 case MachineOperand::MO_MachineBasicBlock:
228227 O << *MO.getMBB()->getSymbol();
570570 ReplaceUses(Froms, Tos, 3);
571571 return Result_1;
572572 }
573
574 return SelectCode(LD);
575573 }
576574
577575
112112 return false;
113113 }
114114 llvm_unreachable(0);
115
116 return true;
117115 }
118116
119117
13741374 default:
13751375 return false;
13761376 }
1377 return false;
13781377 }
13791378
13801379
14491448 default:
14501449 return false;
14511450 }
1452 return false;
1453 }
1451 }
346346 }
347347
348348 llvm_unreachable("Implement any new match types added!");
349 return true;
350349 }
351350
352351 MBlazeOperand *MBlazeAsmParser::
4040 default:
4141 llvm_unreachable("unknown mblaze machine relocation type");
4242 }
43 return 0;
4443 }
4544
4645 long int MBlazeELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
5352 default:
5453 llvm_unreachable("unknown mblaze relocation type");
5554 }
56 return 0;
5755 }
5856
5957 unsigned MBlazeELFWriterInfo::getRelocationTySize(unsigned RelTy) const {
601601 SDValue MBlazeTargetLowering::
602602 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
603603 llvm_unreachable("TLS not implemented for MicroBlaze.");
604 return SDValue(); // Not reached
605604 }
606605
607606 SDValue MBlazeTargetLowering::
10801079 case 'y':
10811080 case 'f':
10821081 return C_RegisterClass;
1083 break;
10841082 }
10851083 }
10861084 return TargetLowering::getConstraintType(Constraint);
183183
184184 unsigned MBlazeRegisterInfo::getEHExceptionRegister() const {
185185 llvm_unreachable("What is the exception register");
186 return 0;
187186 }
188187
189188 unsigned MBlazeRegisterInfo::getEHHandlerRegister() const {
190189 llvm_unreachable("What is the exception handler register");
191 return 0;
192190 }
9595 default:
9696 return false;
9797 }
98 return false; // Not reached
9998 }
10099
101100 /// getMBlazeRegisterNumbering - Given the enum value for some register, e.g.
160159 case MBlaze::RPVR11 : return 0x200B;
161160 default: llvm_unreachable("Unknown register number!");
162161 }
163 return 0; // Not reached
164162 }
165163
166164 /// getRegisterFromNumbering - Given the enum value for some register, e.g.
201199 case 31 : return MBlaze::R31;
202200 default: llvm_unreachable("Unknown register number!");
203201 }
204 return 0; // Not reached
205202 }
206203
207204 static inline unsigned getSpecialMBlazeRegisterFromNumbering(unsigned Reg) {
232229 case 0x200B : return MBlaze::RPVR11;
233230 default: llvm_unreachable("Unknown register number!");
234231 }
235 return 0; // Not reached
236232 }
237233
238234 } // end namespace llvm;
108108 const MCOperand &MO) const {
109109 if (MO.isReg())
110110 return getMBlazeRegisterNumbering(MO.getReg());
111 else if (MO.isImm())
111 if (MO.isImm())
112112 return static_cast(MO.getImm());
113 else if (MO.isExpr())
114 return 0; // The relocation has already been recorded at this point.
115 else {
113 if (MO.isExpr())
114 return 0; // The relocation has already been recorded at this point.
116115 #ifndef NDEBUG
117 errs() << MO;
116 errs() << MO;
118117 #endif
119 llvm_unreachable(0);
120 }
121 return 0;
118 llvm_unreachable(0);
122119 }
123120
124121 void MBlazeMCCodeEmitter::
9191 switch (CC) {
9292 default:
9393 llvm_unreachable("Unsupported CC code");
94 break;
9594 case MSP430CC::COND_E:
9695 O << "eq";
9796 break;
193193 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
194194 default:
195195 llvm_unreachable("unimplemented operand");
196 return SDValue();
197196 }
198197 }
199198
259258 case CallingConv::Fast:
260259 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
261260 case CallingConv::MSP430_INTR:
262 if (Ins.empty())
263 return Chain;
264 else {
261 if (Ins.empty())
262 return Chain;
265263 report_fatal_error("ISRs cannot have arguments");
266 return SDValue();
267 }
268264 }
269265 }
270266
289285 Outs, OutVals, Ins, dl, DAG, InVals);
290286 case CallingConv::MSP430_INTR:
291287 report_fatal_error("ISRs cannot be called directly");
292 return SDValue();
293288 }
294289 }
295290
390385 SmallVector RVLocs;
391386
392387 // ISRs cannot return any value.
393 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
388 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
394389 report_fatal_error("ISRs cannot return any value");
395 return SDValue();
396 }
397390
398391 // CCState - Info about the registers and stack slot.
399392 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
326326 case MSP430II::Size6Bytes:
327327 return 6;
328328 }
329
330 return 6;
331 }
329 }
196196 return 31;
197197 default: llvm_unreachable("Unknown register number!");
198198 }
199 return 0; // Not reached
200199 }
201200 }
202201
236236 return Ret;
237237 }
238238 llvm_unreachable("Unable to encode MCOperand!");
239 // Not reached
240 return 0;
241239 }
242240
243241 /// getMemEncoding - Return binary encoding of memory related operand.
28252825 case 'y':
28262826 case 'f':
28272827 return C_RegisterClass;
2828 break;
28292828 }
28302829 }
28312830 return TargetLowering::getConstraintType(Constraint);
251251 unsigned MipsRegisterInfo::
252252 getEHExceptionRegister() const {
253253 llvm_unreachable("What is the exception register");
254 return 0;
255254 }
256255
257256 unsigned MipsRegisterInfo::
258257 getEHHandlerRegister() const {
259258 llvm_unreachable("What is the exception handler register");
260 return 0;
261 }
259 }
214214 llvm_unreachable("Unknown rounding mode!");
215215 case PTXRoundingMode::RndDefault:
216216 llvm_unreachable("FP rounding-mode pass did not handle instruction!");
217 break;
218217 case PTXRoundingMode::RndNone:
219218 // Do not print anything.
220219 break;
357357 void PTXAsmPrinter::EmitFunctionEntryLabel() {
358358 // The function label could have already been emitted if two symbols end up
359359 // conflicting due to asm renaming. Detect this and emit an error.
360 if (!CurrentFnSym->isUndefined()) {
360 if (!CurrentFnSym->isUndefined())
361361 report_fatal_error("'" + Twine(CurrentFnSym->getName()) +
362362 "' label emitted multiple times to assembly file");
363 return;
364 }
365363
366364 const PTXMachineFunctionInfo *MFI = MF->getInfo();
367365 const PTXParamManager &PM = MFI->getParamManager();
210210 switch (CallConv) {
211211 default:
212212 llvm_unreachable("Unsupported calling convention");
213 break;
214213 case CallingConv::PTX_Kernel:
215214 MFI->setKernel(true);
216215 break;
4848
4949 virtual unsigned getFrameRegister(const MachineFunction &MF) const {
5050 llvm_unreachable("PTX does not have a frame register");
51 return 0;
5251 }
5352 }; // struct PTXRegisterInfo
5453 } // namespace llvm
601601 case ISD::SETULT: return 0;
602602 case ISD::SETUGT: return 1;
603603 }
604 return 0;
605604 }
606605
607606 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
45684568 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
45694569 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
45704570 }
4571 return SDValue();
45724571 }
45734572
45744573 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
117117
118118 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
119119 llvm_unreachable("What is the exception register");
120 return 0;
121120 }
122121
123122 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
124123 llvm_unreachable("What is the exception handler register");
125 return 0;
126124 }
495495 return cast(Ty)->getBitWidth();
496496 default:
497497 llvm_unreachable("TargetData::getTypeSizeInBits(): Unsupported type");
498 break;
499 }
500 return 0;
498 }
501499 }
502500
503501 /*!
552550 break;
553551 default:
554552 llvm_unreachable("Bad type for getAlignment!!!");
555 break;
556553 }
557554
558555 return getAlignmentInfo((AlignTypeEnum)AlignType, getTypeSizeInBits(Ty),
7171 *rECX = registers[2];
7272 *rEDX = registers[3];
7373 return false;
74 #else
75 return true;
7476 #endif
7577 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
7678 #if defined(__GNUC__)
9799 mov dword ptr [esi],edx
98100 }
99101 return false;
102 #else
103 return true;
100104 #endif
105 #else
106 return true;
101107 #endif
102 return true;
103108 }
104109
105110 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
130135 *rECX = registers[2];
131136 *rEDX = registers[3];
132137 return false;
138 #else
139 return true;
133140 #endif
141 #else
142 return true;
134143 #endif
135144 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
136145 #if defined(__GNUC__)
159168 mov dword ptr [esi],edx
160169 }
161170 return false;
171 #else
172 return true;
162173 #endif
174 #else
175 return true;
163176 #endif
164 return true;
165177 }
166178
167179 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
4343 case X86::reloc_riprel_4byte:
4444 case X86::reloc_riprel_4byte_movq_load:
4545 return Is64Bit ? COFF::IMAGE_REL_AMD64_REL32 : COFF::IMAGE_REL_I386_REL32;
46 break;
4746 case FK_Data_4:
4847 case X86::reloc_signed_4byte:
4948 return Is64Bit ? COFF::IMAGE_REL_AMD64_ADDR32 : COFF::IMAGE_REL_I386_DIR32;
50 break;
5149 case FK_Data_8:
5250 if (Is64Bit)
5351 return COFF::IMAGE_REL_AMD64_ADDR64;
54 else
55 llvm_unreachable("unsupported relocation type");
56 break;
52 llvm_unreachable("unsupported relocation type");
5753 case FK_SecRel_4:
5854 return Is64Bit ? COFF::IMAGE_REL_AMD64_SREL32 : COFF::IMAGE_REL_I386_SECREL;
59 break;
6055 default:
6156 llvm_unreachable("unsupported relocation type");
6257 }
5959 llvm_unreachable("unknown x86 machine relocation type");
6060 }
6161 }
62 return 0;
6362 }
6463
6564 long int X86ELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
8281 llvm_unreachable("unknown x86 relocation type");
8382 }
8483 }
85 return 0;
8684 }
8785
8886 unsigned X86ELFWriterInfo::getRelocationTySize(unsigned RelTy) const {
106104 llvm_unreachable("unknown x86 relocation type");
107105 }
108106 }
109 return 0;
110107 }
111108
112109 bool X86ELFWriterInfo::isPCRelativeRel(unsigned RelTy) const {
131128 llvm_unreachable("unknown x86 relocation type");
132129 }
133130 }
134 return 0;
135131 }
136132
137133 unsigned X86ELFWriterInfo::getAbsoluteLabelMachineRelTy() const {
13041304 /// the first register, false for the second.
13051305 static unsigned
13061306 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1307 if (Is64Bit) {
1307 if (Is64Bit)
13081308 return Primary ? X86::R11 : X86::R12;
1309 } else {
1310 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1311 bool IsNested = HasNestArgument(&MF);
1312
1313 if (CallingConvention == CallingConv::X86_FastCall ||
1314 CallingConvention == CallingConv::Fast) {
1315 if (IsNested) {
1316 report_fatal_error("Segmented stacks does not support fastcall with "
1317 "nested function.");
1318 return -1;
1319 } else {
1320 return Primary ? X86::EAX : X86::ECX;
1321 }
1322 } else {
1323 if (IsNested)
1324 return Primary ? X86::EDX : X86::EAX;
1325 else
1326 return Primary ? X86::ECX : X86::EAX;
1327 }
1328 }
1309
1310 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1311 bool IsNested = HasNestArgument(&MF);
1312
1313 if (CallingConvention == CallingConv::X86_FastCall ||
1314 CallingConvention == CallingConv::Fast) {
1315 if (IsNested)
1316 report_fatal_error("Segmented stacks does not support fastcall with "
1317 "nested function.");
1318 return Primary ? X86::EAX : X86::ECX;
1319 }
1320 if (IsNested)
1321 return Primary ? X86::EDX : X86::EAX;
1322 return Primary ? X86::ECX : X86::EAX;
13291323 }
13301324
13311325 // The stack limit in the TCB is set to this many bytes above the actual stack
19671967 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
19681968 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
19691969 getI8Imm(ShlVal));
1970 break;
19711970 }
19721971 case X86ISD::UMUL: {
19731972 SDValue N0 = Node->getOperand(0);
29082908 case X86ISD::VPERM2X128:
29092909 return true;
29102910 }
2911 return false;
29122911 }
29132912
29142913 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
29202919 case X86ISD::MOVDDUP:
29212920 return DAG.getNode(Opc, dl, VT, V1);
29222921 }
2923
2924 return SDValue();
29252922 }
29262923
29272924 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
29342931 case X86ISD::VPERMILP:
29352932 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
29362933 }
2937
2938 return SDValue();
29392934 }
29402935
29412936 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
29482943 return DAG.getNode(Opc, dl, VT, V1, V2,
29492944 DAG.getConstant(TargetMask, MVT::i8));
29502945 }
2951 return SDValue();
29522946 }
29532947
29542948 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
29662960 case X86ISD::UNPCKH:
29672961 return DAG.getNode(Opc, dl, VT, V1, V2);
29682962 }
2969 return SDValue();
29702963 }
29712964
29722965 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
74387431 Chain.getValue(1));
74397432 }
74407433
7441 assert(false &&
7442 "TLS not implemented for this target.");
7443
7444 llvm_unreachable("Unreachable");
7445 return SDValue();
7434 llvm_unreachable("TLS not implemented for this target.");
74467435 }
74477436
74487437
1350013489 switch (N->getOpcode()) {
1350113490 default:
1350213491 llvm_unreachable("Unknown shift opcode!");
13503 break;
1350413492 case ISD::SHL:
1350513493 if (VT == MVT::v2i64)
1350613494 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11631163 switch (MI.getOpcode()) {
11641164 default:
11651165 llvm_unreachable(0);
1166 break;
11671166 case X86::MOVSX16rr8:
11681167 case X86::MOVZX16rr8:
11691168 case X86::MOVSX32rr8:
12061205
12071206 static bool isFrameLoadOpcode(int Opcode) {
12081207 switch (Opcode) {
1209 default: break;
1208 default:
1209 return false;
12101210 case X86::MOV8rm:
12111211 case X86::MOV16rm:
12121212 case X86::MOV32rm:
12281228 case X86::MMX_MOVD64rm:
12291229 case X86::MMX_MOVQ64rm:
12301230 return true;
1231 break;
1232 }
1233 return false;
1231 }
12341232 }
12351233
12361234 static bool isFrameStoreOpcode(int Opcode) {
15741572 switch (MIOpc) {
15751573 default:
15761574 llvm_unreachable(0);
1577 break;
15781575 case X86::SHL16ri: {
15791576 unsigned ShAmt = MI->getOperand(2).getImm();
15801577 MIB.addReg(0).addImm(1 << ShAmt)
570570 return TLSOffset;
571571 #else
572572 llvm_unreachable("Cannot allocate thread local storage on this arch!");
573 return 0;
574 #endif
575 }
573 #endif
574 }
525525
526526 unsigned X86RegisterInfo::getEHExceptionRegister() const {
527527 llvm_unreachable("What is the exception register");
528 return 0;
529528 }
530529
531530 unsigned X86RegisterInfo::getEHHandlerRegister() const {
532531 llvm_unreachable("What is the exception handler register");
533 return 0;
534532 }
535533
536534 namespace llvm {
712710 return X86::R15;
713711 }
714712 }
715
716 return Reg;
717713 }
718714 }
719715
186186 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
187187 default:
188188 llvm_unreachable("unimplemented operand");
189 return SDValue();
190189 }
191190 }
192191
198197 switch (N->getOpcode()) {
199198 default:
200199 llvm_unreachable("Don't know how to custom expand this!");
201 return;
202200 case ISD::ADD:
203201 case ISD::SUB:
204202 Results.push_back(ExpandADDSUB(N, DAG));
274272 if (const GlobalAlias *GA = dyn_cast(GV))
275273 GVar = dyn_cast_or_null(GA->resolveAliasedGlobal());
276274 }
277 if (! GVar) {
275 if (!GVar) {
278276 llvm_unreachable("Thread local object not a GlobalVariable?");
279 return SDValue();
280277 }
281278 Type *Ty = cast(GV->getType())->getElementType();
282279 if (!Ty->isSized() || isZeroLengthArray(Ty)) {
756753 LowerVAARG(SDValue Op, SelectionDAG &DAG) const
757754 {
758755 llvm_unreachable("unimplemented");
759 // FIX Arguments passed by reference need a extra dereference.
756 // FIXME Arguments passed by reference need a extra dereference.
760757 SDNode *Node = Op.getNode();
761758 DebugLoc dl = Node->getDebugLoc();
762759 const Value *V = cast(Node->getOperand(2))->getValue();
16011598 // reg + reg<<2
16021599 return AM.Scale == 4 && AM.BaseOffs == 0;
16031600 }
1604
1605 return false;
16061601 }
16071602
16081603 //===----------------------------------------------------------------------===//
12091209 PHIsToRewrite.push_back(std::make_pair(PN, FieldNo));
12101210 } else {
12111211 llvm_unreachable("Unknown usable value");
1212 Result = 0;
12131212 }
12141213
12151214 return FieldVals[FieldNo] = Result;
8686 default:
8787 // Not expecting FCMP_FALSE and FCMP_TRUE;
8888 llvm_unreachable("Unexpected FCmp predicate!");
89 return 0;
9089 }
9190 }
9291
15541553 case ICmpInst::ICMP_SLT: // (X != 13 | X s< 15) -> true
15551554 return ConstantInt::getTrue(LHS->getContext());
15561555 }
1557 break;
15581556 case ICmpInst::ICMP_ULT:
15591557 switch (RHSCC) {
15601558 default: llvm_unreachable("Unknown integer condition code!");
214214 default:
215215 // TODO: Can handle more cases here.
216216 llvm_unreachable("Unreachable!");
217 break;
218217 }
219218
220219 Res->takeName(I);
183183 return BinaryOperator::Create(BO->getOpcode(), NewSI, MatchOp);
184184 }
185185 llvm_unreachable("Shouldn't get here");
186 return 0;
187186 }
188187
189188 static bool isSelect01(Constant *C1, Constant *C2) {
13171317 return AM.Scale == 0 || AM.Scale == -1;
13181318 }
13191319
1320 return false;
1320 llvm_unreachable("Invalid LSRUse Kind!");
13211321 }
13221322
13231323 static bool isLegalUse(TargetLowering::AddrMode AM,
19961996 // Nothing else matters for objc_retainAutorelease formation.
19971997 return false;
19981998 }
1999 break;
20001999
20012000 case RetainAutoreleaseRVDep: {
20022001 InstructionClass Class = GetBasicInstructionClass(Inst);
20102009 // retainAutoreleaseReturnValue formation.
20112010 return CanInterruptRV(Class);
20122011 }
2013 break;
20142012 }
20152013
20162014 case RetainRVDep:
19071907 APInt V1 = cast(C1)->getValue();
19081908 APInt V2 = cast(C2)->getValue();
19091909 switch (pred) {
1910 default: llvm_unreachable("Invalid ICmp Predicate"); return 0;
1910 default: llvm_unreachable("Invalid ICmp Predicate");
19111911 case ICmpInst::ICMP_EQ: return ConstantInt::get(ResultTy, V1 == V2);
19121912 case ICmpInst::ICMP_NE: return ConstantInt::get(ResultTy, V1 != V2);
19131913 case ICmpInst::ICMP_SLT: return ConstantInt::get(ResultTy, V1.slt(V2));
19241924 APFloat C2V = cast(C2)->getValueAPF();
19251925 APFloat::cmpResult R = C1V.compare(C2V);
19261926 switch (pred) {
1927 default: llvm_unreachable("Invalid FCmp Predicate"); return 0;
1927 default: llvm_unreachable("Invalid FCmp Predicate");
19281928 case FCmpInst::FCMP_FALSE: return Constant::getNullValue(ResultTy);
19291929 case FCmpInst::FCMP_TRUE: return Constant::getAllOnesValue(ResultTy);
19301930 case FCmpInst::FCMP_UNO:
12401240 switch (opc) {
12411241 default:
12421242 llvm_unreachable("Invalid cast opcode");
1243 break;
12441243 case Instruction::Trunc: return getTrunc(C, Ty);
12451244 case Instruction::ZExt: return getZExt(C, Ty);
12461245 case Instruction::SExt: return getSExt(C, Ty);
12541253 case Instruction::IntToPtr: return getIntToPtr(C, Ty);
12551254 case Instruction::BitCast: return getBitCast(C, Ty);
12561255 }
1257 return 0;
12581256 }
12591257
12601258 Constant *ConstantExpr::getZExtOrBitCast(Constant *C, Type *Ty) {
21732171 Replacement = ConstantExpr::get(getOpcode(), C1, C2, SubclassOptionalData);
21742172 } else {
21752173 llvm_unreachable("Unknown ConstantExpr type!");
2176 return;
21772174 }
21782175
21792176 assert(Replacement != this && "I didn't contain From!");
16161616 Value *V = unwrap(Instr);
16171617 if (CallInst *CI = dyn_cast(V))
16181618 return CI->getCallingConv();
1619 else if (InvokeInst *II = dyn_cast(V))
1619 if (InvokeInst *II = dyn_cast(V))
16201620 return II->getCallingConv();
16211621 llvm_unreachable("LLVMGetInstructionCallConv applies only to call and invoke!");
1622 return 0;
16231622 }
16241623
16251624 void LLVMSetInstructionCallConv(LLVMValueRef Instr, unsigned CC) {
624624
625625 BasicBlock *ReturnInst::getSuccessorV(unsigned idx) const {
626626 llvm_unreachable("ReturnInst has no successors!");
627 return 0;
628627 }
629628
630629 ReturnInst::~ReturnInst() {
654653
655654 BasicBlock *UnwindInst::getSuccessorV(unsigned idx) const {
656655 llvm_unreachable("UnwindInst has no successors!");
657 return 0;
658656 }
659657
660658 //===----------------------------------------------------------------------===//
689687
690688 BasicBlock *ResumeInst::getSuccessorV(unsigned idx) const {
691689 llvm_unreachable("ResumeInst has no successors!");
692 return 0;
693690 }
694691
695692 //===----------------------------------------------------------------------===//
716713
717714 BasicBlock *UnreachableInst::getSuccessorV(unsigned idx) const {
718715 llvm_unreachable("UnwindInst has no successors!");
719 return 0;
720716 }
721717
722718 //===----------------------------------------------------------------------===//
22722268 assert(0 && "Error in CastResults table!!!");
22732269 return 0;
22742270 }
2275 return 0;
22762271 }
22772272
22782273 CastInst *CastInst::Create(Instruction::CastOps op, Value *S, Type *Ty,
22942289 case BitCast: return new BitCastInst (S, Ty, Name, InsertBefore);
22952290 default:
22962291 assert(0 && "Invalid opcode provided");
2297 }
2298 return 0;
2292 return 0;
2293 }
22992294 }
23002295
23012296 CastInst *CastInst::Create(Instruction::CastOps op, Value *S, Type *Ty,
23172312 case BitCast: return new BitCastInst (S, Ty, Name, InsertAtEnd);
23182313 default:
23192314 assert(0 && "Invalid opcode provided");
2320 }
2321 return 0;
2315 return 0;
2316 }
23222317 }
23232318
23242319 CastInst *CastInst::CreateZExtOrBitCast(Value *S, Type *Ty,
162162 const Function *MDNode::getFunction() const {
163163 #ifndef NDEBUG
164164 return assertLocalFunction(this);
165 #endif
165 #else
166166 if (!isFunctionLocal()) return NULL;
167167 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
168168 if (const Function *F = getFunctionForValue(getOperand(i)))
169169 return F;
170170 return NULL;
171 #endif
171172 }
172173
173174 // destroy - Delete this node. Only when there are no uses.
154154 const std::string &Banner) const {
155155
156156 llvm_unreachable("BasicBlockPass printing unsupported.");
157 return 0;
158157 }
159158
160159 bool BasicBlockPass::doInitialization(Module &) {
100100 if (isInteger())
101101 return "i" + utostr(getSizeInBits());
102102 llvm_unreachable("Invalid EVT!");
103 return "?";
104103 case MVT::i1: return "i1";
105104 case MVT::i8: return "i8";
106105 case MVT::i16: return "i16";
200199 default:
201200 if (HandleUnknown) return MVT(MVT::Other);
202201 llvm_unreachable("Unknown type!");
203 return MVT::isVoid;
204202 case Type::VoidTyID:
205203 return MVT::isVoid;
206204 case Type::IntegerTyID:
3333 #include "llvm/Target/TargetMachine.h"
3434 #include "llvm/Target/TargetRegisterInfo.h"
3535 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
3637 #include "llvm/Support/FormattedStream.h"
3738 #include "llvm/Support/MemoryBuffer.h"
3839 #include "llvm/Support/SystemUtils.h"
110111 _emitDwarfDebugInfo = true;
111112 return false;
112113 }
113 errMsg = "unknown debug format";
114 return true;
114 llvm_unreachable("Unknown debug format!");
115115 }
116116
117117
125125 _codeModel = model;
126126 return false;
127127 }
128 errMsg = "unknown pic model";
129 return true;
128 llvm_unreachable("Unknown PIC model!");
130129 }
131130
132131 void LTOCodeGenerator::setCpu(const char* mCpu)