llvm.org GIT mirror llvm / 4d54e5b
Tail merging pass shall not break up IT blocks. rdar://8115404 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
8 changed file(s) with 190 addition(s) and 20 deletion(s). Raw diff Collapse all Expand all
326326 /// used by the tail merging pass.
327327 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
328328 MachineBasicBlock *NewDest) const = 0;
329
330 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
331 /// block at the specified instruction (i.e. instruction would be the start
332 /// of a new basic block).
333 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
334 MachineBasicBlock::iterator MBBI) const {
335 return true;
336 }
329337
330338 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
331339 /// returns false if the target does not how to copy between the specified
369369 /// iterator. This returns the new MBB.
370370 MachineBasicBlock *BranchFolder::SplitMBBAt(MachineBasicBlock &CurMBB,
371371 MachineBasicBlock::iterator BBI1) {
372 if (!TII->isLegalToSplitMBBAt(CurMBB, BBI1))
373 return 0;
374
372375 MachineFunction &MF = *CurMBB.getParent();
373376
374377 // Create the fall-through block.
613616
614617 /// CreateCommonTailOnlyBlock - None of the blocks to be tail-merged consist
615618 /// only of the common tail. Create a block that does by splitting one.
616 unsigned BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
617 unsigned maxCommonTailLength) {
618 unsigned commonTailIndex = 0;
619 bool BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
620 unsigned maxCommonTailLength,
621 unsigned &commonTailIndex) {
622 commonTailIndex = 0;
619623 unsigned TimeEstimate = ~0U;
620624 for (unsigned i = 0, e = SameTails.size(); i != e; ++i) {
621625 // Use PredBB if possible; that doesn't require a new branch.
643647 << maxCommonTailLength);
644648
645649 MachineBasicBlock *newMBB = SplitMBBAt(*MBB, BBI);
650 if (!newMBB) {
651 DEBUG(dbgs() << "... failed!");
652 return false;
653 }
654
646655 SameTails[commonTailIndex].setBlock(newMBB);
647656 SameTails[commonTailIndex].setTailStartPos(newMBB->begin());
648657
650659 if (PredBB == MBB)
651660 PredBB = newMBB;
652661
653 return commonTailIndex;
662 return true;
654663 }
655664
656665 // See if any of the blocks in MergePotentials (which all have a common single
745754 !SameTails[commonTailIndex].tailIsWholeBlock())) {
746755 // None of the blocks consist entirely of the common tail.
747756 // Split a block so that one does.
748 commonTailIndex = CreateCommonTailOnlyBlock(PredBB, maxCommonTailLength);
757 if (!CreateCommonTailOnlyBlock(PredBB,
758 maxCommonTailLength, commonTailIndex)) {
759 RemoveBlocksWithHash(CurHash, SuccBB, PredBB);
760 continue;
761 }
749762 }
750763
751764 MachineBasicBlock *MBB = SameTails[commonTailIndex].getBlock();
101101 MachineBasicBlock *PredBB);
102102 void RemoveBlocksWithHash(unsigned CurHash, MachineBasicBlock* SuccBB,
103103 MachineBasicBlock* PredBB);
104 unsigned CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
105 unsigned maxCommonTailLength);
104 bool CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
105 unsigned maxCommonTailLength,
106 unsigned &commonTailIndex);
106107
107108 bool OptimizeBranches(MachineFunction &MF);
108109 bool OptimizeBlock(MachineBasicBlock *MBB);
2727 #include "llvm/Support/raw_ostream.h"
2828 using namespace llvm;
2929
30 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
31 /// after it, replacing it with an unconditional branch to NewDest.
3032 void
3133 TargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
3234 MachineBasicBlock *NewDest) const {
5959 bool InsertITInstructions(MachineBasicBlock &MBB);
6060 };
6161 char Thumb2ITBlockPass::ID = 0;
62 }
63
64 static ARMCC::CondCodes getPredicate(const MachineInstr *MI, unsigned &PredReg){
65 unsigned Opc = MI->getOpcode();
66 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
67 return ARMCC::AL;
68 return llvm::getInstrPredicate(MI, PredReg);
6962 }
7063
7164 bool
8174 for (unsigned i = 0; i < 4; ++i) {
8275 MachineInstr *MI = &*I;
8376 unsigned MPredReg = 0;
84 ARMCC::CondCodes MCC = getPredicate(MI, MPredReg);
77 ARMCC::CondCodes MCC = llvm::getITInstrPredicate(MI, MPredReg);
8578 if (MCC != ARMCC::AL) {
8679 if (MPredReg != PredReg || (MCC != CC && MCC != OCC))
8780 return false;
208201 return false;
209202
210203 unsigned PredReg = 0;
211 ARMCC::CondCodes CC = getPredicate(First, PredReg);
204 ARMCC::CondCodes CC = llvm::getITInstrPredicate(First, PredReg);
212205 if (CC == ARMCC::AL)
213206 return Modified;
214207
221214 return Modified;
222215 MachineInstr *NMI = &*MBBI;
223216 unsigned NPredReg = 0;
224 ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
217 ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg);
225218 if (NCC != CC && NCC != OCC) {
226219 if (NCC != ARMCC::AL)
227220 return Modified;
320313 while (I != E && I->isDebugValue())
321314 ++I;
322315 unsigned NPredReg = 0;
323 ARMCC::CondCodes NCC = getPredicate(I, NPredReg);
316 ARMCC::CondCodes NCC = llvm::getITInstrPredicate(I, NPredReg);
324317 if (NCC == CC || NCC == OCC)
325318 return true;
326319 }
338331 MachineInstr *MI = &*MBBI;
339332 DebugLoc dl = MI->getDebugLoc();
340333 unsigned PredReg = 0;
341 ARMCC::CondCodes CC = getPredicate(MI, PredReg);
334 ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg);
342335 if (CC == ARMCC::AL) {
343336 ++MBBI;
344337 continue;
374367 MI = NMI;
375368
376369 unsigned NPredReg = 0;
377 ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
370 ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg);
378371 if (NCC == CC || NCC == OCC) {
379372 Mask |= (NCC & 1) << Pos;
380373 // Add implicit use of ITSTATE.
8585 // formation pass.
8686 }
8787 }
88
89 bool
90 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator MBBI) const {
92 unsigned PredReg = 0;
93 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
94 }
95
8896
8997 bool
9098 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
604612 MBB->insert(++MBBI, SrcMI);
605613 }
606614 }
615
616 ARMCC::CondCodes
617 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
618 unsigned Opc = MI->getOpcode();
619 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
620 return ARMCC::AL;
621 return llvm::getInstrPredicate(MI, PredReg);
622 }
3434 void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
3535 MachineBasicBlock *NewDest) const;
3636
37 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MBBI) const;
39
3740 bool copyRegToReg(MachineBasicBlock &MBB,
3841 MachineBasicBlock::iterator I,
3942 unsigned DestReg, unsigned SrcReg,
6770 ScheduleHazardRecognizer *
6871 CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const;
6972 };
73
74 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
75 /// to llvm::getInstrPredicate except it returns AL for conditional branch
76 /// instructions which are "predicated", but are not in IT blocks.
77 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
78
79
7080 }
7181
7282 #endif // THUMB2INSTRUCTIONINFO_H
0 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O3 -relocation-model=pic -mcpu=cortex-a8 | FileCheck %s
1 ; rdar://8115404
2 ; Tail merging must not split an IT block.
3
4 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
5 %struct._RuneCharClass = type { [14 x i8], i32 }
6 %struct._RuneEntry = type { i32, i32, i32, i32* }
7 %struct._RuneLocale = type { [8 x i8], [32 x i8], i32 (i8*, i32, i8**)*, i32 (i32, i8*, i32, i8**)*, i32, [256 x i32], [256 x i32], [256 x i32], %struct._RuneRange, %struct._RuneRange, %struct._RuneRange, i8*, i32, i32, %struct._RuneCharClass* }
8 %struct._RuneRange = type { i32, %struct._RuneEntry* }
9 %struct.__sFILEX = type opaque
10 %struct.__sbuf = type { i8*, i32 }
11
12 @finput = external global %struct.FILE* ; <%struct.FILE**> [#uses=1]
13 @_DefaultRuneLocale = external global %struct._RuneLocale ; <%struct._RuneLocale*> [#uses=0]
14 @token_buffer = external global [1025 x i8], align 4 ; <[1025 x i8]*> [#uses=1]
15 @.str73 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=0]
16 @.str174 = external constant [5 x i8], align 4 ; <[5 x i8]*> [#uses=0]
17 @.str275 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=0]
18 @.str376 = external constant [5 x i8], align 4 ; <[5 x i8]*> [#uses=0]
19 @.str477 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=0]
20 @.str578 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=0]
21 @.str679 = external constant [7 x i8], align 4 ; <[7 x i8]*> [#uses=0]
22 @.str780 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=0]
23 @.str881 = external constant [5 x i8], align 4 ; <[5 x i8]*> [#uses=0]
24 @.str982 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=0]
25 @.str1083 = external constant [9 x i8], align 4 ; <[9 x i8]*> [#uses=0]
26 @.str1184 = external constant [7 x i8], align 4 ; <[7 x i8]*> [#uses=0]
27 @.str1285 = external constant [16 x i8], align 4 ; <[16 x i8]*> [#uses=0]
28 @.str1386 = external constant [12 x i8], align 4 ; <[12 x i8]*> [#uses=0]
29 @.str1487 = external constant [5 x i8], align 4 ; <[5 x i8]*> [#uses=0]
30 @llvm.used = external global [1 x i8*] ; <[1 x i8*]*> [#uses=0]
31
32 define fastcc i32 @parse_percent_token() nounwind {
33 entry:
34 ; CHECK: ittt eq
35 ; CHECK: ittt eq
36 ; CHECK: ittt eq
37 ; CHECK: ittt eq
38 ; CHECK: ittt eq
39 ; CHECK: moveq r0
40 ; CHECK-NOT: LBB0_
41 ; CHECK: ldreq
42 ; CHECK: popeq
43 switch i32 undef, label %bb7 [
44 i32 37, label %bb43
45 i32 48, label %bb5
46 i32 50, label %bb4
47 i32 60, label %bb2
48 i32 61, label %bb6
49 i32 62, label %bb3
50 i32 123, label %bb1
51 ]
52
53 bb1: ; preds = %entry
54 ret i32 8
55
56 bb2: ; preds = %entry
57 ret i32 15
58
59 bb3: ; preds = %entry
60 ret i32 16
61
62 bb4: ; preds = %entry
63 ret i32 17
64
65 bb5: ; preds = %entry
66 ret i32 9
67
68 bb6: ; preds = %entry
69 ret i32 18
70
71 bb7: ; preds = %entry
72 br i1 undef, label %bb.i.i, label %bb1.i.i
73
74 bb.i.i: ; preds = %bb7
75 br i1 undef, label %bb43, label %bb12
76
77 bb1.i.i: ; preds = %bb7
78 unreachable
79
80 bb9: ; preds = %bb.i.i2
81 br i1 undef, label %bb10, label %bb11
82
83 bb10: ; preds = %bb9
84 br label %bb11
85
86 bb11: ; preds = %bb10, %bb9
87 %p.0 = phi i8* [ undef, %bb10 ], [ %p.1, %bb9 ] ; [#uses=1]
88 %0 = load %struct.FILE** @finput, align 4 ; <%struct.FILE*> [#uses=1]
89 %1 = tail call i32 @getc(%struct.FILE* %0) nounwind ; [#uses=0]
90 br label %bb12
91
92 bb12: ; preds = %bb11, %bb.i.i
93 %p.1 = phi i8* [ %p.0, %bb11 ], [ getelementptr inbounds ([1025 x i8]* @token_buffer, i32 0, i32 0), %bb.i.i ] ; [#uses=2]
94 %2 = icmp ult i32 undef, 128 ; [#uses=1]
95 br i1 %2, label %bb.i.i2, label %bb1.i.i3
96
97 bb.i.i2: ; preds = %bb12
98 %3 = load i32* null, align 4 ; [#uses=1]
99 %4 = lshr i32 %3, 8 ; [#uses=1]
100 %.lobit.i1 = and i32 %4, 1 ; [#uses=1]
101 %.not = icmp ne i32 %.lobit.i1, 0 ; [#uses=1]
102 %or.cond = or i1 %.not, undef ; [#uses=1]
103 br i1 %or.cond, label %bb9, label %bb14
104
105 bb1.i.i3: ; preds = %bb12
106 unreachable
107
108 bb14: ; preds = %bb.i.i2
109 store i8 0, i8* %p.1, align 1
110 br i1 undef, label %bb43, label %bb15
111
112 bb15: ; preds = %bb14
113 unreachable
114
115 bb43: ; preds = %bb14, %bb.i.i, %entry
116 %.0 = phi i32 [ 7, %entry ], [ 24, %bb.i.i ], [ 9, %bb14 ] ; [#uses=1]
117 ret i32 %.0
118 }
119
120 declare i32 @getc(%struct.FILE* nocapture) nounwind
121
122 declare i32 @strcmp(i8* nocapture, i8* nocapture) nounwind readonly
123
124 declare i32 @__maskrune(i32, i32)
125
126 declare i32 @ungetc(i32, %struct.FILE* nocapture) nounwind