llvm.org GIT mirror llvm / 4d53e77
Don't reserve R2 on Darwin/PPC Now that only the register-scavenger version of the CR spilling code remains, we no longer need the Darwin R2 hack. Darwin can use R0 as a spare register in any case where the System V ABI uses it (R0 is special architecturally, and so is reserved under all common ABIs). A few test cases needed to be updated to reflect the register-allocation changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176868 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 7 years ago
7 changed file(s) with 36 addition(s) and 49 deletion(s). Raw diff Collapse all Expand all
120120 Reserved.set(PPC::R2); // System-reserved register
121121 Reserved.set(PPC::R13); // Small Data Area pointer register
122122 }
123 // Reserve R2 on Darwin to hack around the problem of save/restore of CR
124 // when the stack frame is too big to address directly; we need two regs.
125 // This is a hack.
126 if (Subtarget.isDarwinABI()) {
127 Reserved.set(PPC::R2);
128 }
129123
130124 // On PPC64, r13 is the thread pointer. Never allocate this register.
131125 // Note that this is over conservative, as it also prevents allocation of R31
141135
142136 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
143137 if (Subtarget.isSVR4ABI()) {
144 Reserved.set(PPC::X2);
145 }
146 // Reserve X2 on Darwin to hack around the problem of save/restore of CR
147 // when the stack frame is too big to address directly; we need two regs.
148 // This is a hack.
149 if (Subtarget.isDarwinABI()) {
150138 Reserved.set(PPC::X2);
151139 }
152140 }
333321 (void) RS;
334322
335323 bool LP64 = Subtarget.isPPC64();
336 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) :
337 (LP64 ? PPC::X0 : PPC::R0);
324 unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
338325 unsigned SrcReg = MI.getOperand(0).getReg();
339326
340327 // We need to store the CR in the low 4-bits of the saved value. First, issue
376363 (void) RS;
377364
378365 bool LP64 = Subtarget.isPPC64();
379 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) :
380 (LP64 ? PPC::X0 : PPC::R0);
366 unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
381367 unsigned DestReg = MI.getOperand(0).getReg();
382368 assert(MI.definesRegister(DestReg) &&
383369 "RESTORE_CR does not define its destination");
99 define void @foo(i32 %y) nounwind ssp {
1010 entry:
1111 ; CHECK: foo
12 ; CHECK: add r3
13 ; CHECK: 0(r3)
12 ; CHECK: add r2
13 ; CHECK: 0(r2)
1414 %y_addr = alloca i32 ; [#uses=2]
1515 %"alloca point" = bitcast i32 0 to i32 ; [#uses=0]
1616 store i32 %y, i32* %y_addr
55
66 define void @foo() nounwind {
77 entry:
8 ;CHECK: mfcr r2
9 ;CHECK: lis r3, 1
10 ;CHECK: rlwinm r2, r2, 8, 0, 31
11 ;CHECK: ori r3, r3, 34524
12 ;CHECK: stwx r2, r1, r3
8 ;CHECK: mfcr r0
9 ;CHECK: lis r2, 1
10 ;CHECK: rlwinm r0, r0, 8, 0, 31
11 ;CHECK: ori r2, r2, 34524
12 ;CHECK: stwx r0, r1, r2
1313 ; Make sure that the register scavenger returns the same temporary register.
14 ;CHECK: mfcr r2
15 ;CHECK: lis r3, 1
16 ;CHECK: rlwinm r2, r2, 12, 0, 31
17 ;CHECK: ori r3, r3, 34520
18 ;CHECK: stwx r2, r1, r3
14 ;CHECK: lis r2, 1
15 ;CHECK: mfcr r0
16 ;CHECK: ori r2, r2, 34520
17 ;CHECK: rlwinm r0, r0, 12, 0, 31
18 ;CHECK: stwx r0, r1, r2
1919 %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
2020 %"alloca point" = bitcast i32 0 to i32 ; [#uses=0]
2121 %x1 = bitcast [100000 x i8]* %x to i8* ; [#uses=1]
2424 br label %return
2525
2626 return: ; preds = %entry
27 ;CHECK: lis r3, 1
28 ;CHECK: ori r3, r3, 34524
29 ;CHECK: lwzx r2, r1, r3
30 ;CHECK: rlwinm r2, r2, 24, 0, 31
31 ;CHECK: mtcrf 32, r2
27 ;CHECK: lis r2, 1
28 ;CHECK: ori r2, r2, 34524
29 ;CHECK: lwzx r0, r1, r2
30 ;CHECK: rlwinm r0, r0, 24, 0, 31
31 ;CHECK: mtcrf 32, r0
3232 ret void
3333 }
3434
1717 ; CHECK: _g:
1818 ; CHECK: mflr r0
1919 ; CHECK: stw r0, 8(r1)
20 ; CHECK: lwz r3, 0(r1)
21 ; CHECK: lwz r3, 8(r3)
20 ; CHECK: lwz r2, 0(r1)
21 ; CHECK: lwz r3, 8(r2)
2222 %0 = tail call i8* @llvm.returnaddress(i32 1) ; [#uses=1]
2323 ret i8* %0
2424 }
66 entry:
77 ; Make sure we're generating references using the red zone
88 ; CHECK: main:
9 ; CHECK: stw r3, -12(r1)
9 ; CHECK: stw r2, -12(r1)
1010 %retval = alloca i32
1111 %0 = alloca i32
1212 %"alloca point" = bitcast i32 0 to i32
0 ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \
1 ; RUN: grep "stw r4, 32751"
1 ; RUN: grep "stw r3, 32751"
22 ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
3 ; RUN: grep "stw r4, 32751"
3 ; RUN: grep "stw r3, 32751"
44 ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
5 ; RUN: grep "std r4, 9024"
5 ; RUN: grep "std r3, 9024"
66
77 define void @test() nounwind {
88 store i32 0, i32* inttoptr (i64 48725999 to i32*)
77 }
88
99 ; P32: test1:
10 ; P32: lwz r4, 0(r3)
11 ; P32: addi r5, r4, 4
12 ; P32: stw r5, 0(r3)
13 ; P32: lwz r3, 0(r4)
14 ; P32: blr
10 ; P32: lwz r2, 0(r3)
11 ; P32: addi r4, r2, 4
12 ; P32: stw r4, 0(r3)
13 ; P32: lwz r3, 0(r2)
14 ; P32: blr
1515
1616 ; P64: test1:
17 ; P64: ld r4, 0(r3)
18 ; P64: addi r5, r4, 8
19 ; P64: std r5, 0(r3)
20 ; P64: ld r3, 0(r4)
21 ; P64: blr
17 ; P64: ld r2, 0(r3)
18 ; P64: addi r4, r2, 8
19 ; P64: std r4, 0(r3)
20 ; P64: ld r3, 0(r2)
21 ; P64: blr
22