llvm.org GIT mirror llvm / 4d2f077
Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8 Richard Barton 8 years ago
3 changed file(s) with 7 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
72137213 // The mask bits for all but the first condition are represented as
72147214 // the low bit of the condition code value implies 't'. We currently
72157215 // always have 1 implies 't', so XOR toggle the bits if the low bit
7216 // of the condition code is zero. The encoding also expects the low
7217 // bit of the condition to be encoded as bit 4 of the mask operand,
7218 // so mask that in if needed
7216 // of the condition code is zero.
72197217 MCOperand &MO = Inst.getOperand(1);
72207218 unsigned Mask = MO.getImm();
72217219 unsigned OrigMask = Mask;
72247222 assert(Mask && TZ <= 3 && "illegal IT mask value!");
72257223 for (unsigned i = 3; i != TZ; --i)
72267224 Mask ^= 1 << i;
7227 } else
7228 Mask |= 0x10;
7225 }
72297226 MO.setImm(Mask);
72307227
72317228 // Set up the IT block state according to the IT instruction we just
6262 // fields in the IT instruction encoding.
6363 void setITState(char Firstcond, char Mask) {
6464 // (3 - the number of trailing zeros) is the number of then / else.
65 unsigned CondBit0 = Mask >> 4 & 1;
65 unsigned CondBit0 = Firstcond & 1;
6666 unsigned NumTZ = CountTrailingZeros_32(Mask);
6767 unsigned char CCBits = static_cast(Firstcond & 0xf);
6868 assert(NumTZ <= 3 && "Invalid IT mask!");
42164216 uint64_t Address, const void *Decoder) {
42174217 DecodeStatus S = MCDisassembler::Success;
42184218 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
4219 // The InstPrinter needs to have the low bit of the predicate in
4220 // the mask operand to be able to print it properly.
4221 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
4219 unsigned mask = fieldFromInstruction16(Insn, 0, 4);
42224220
42234221 if (pred == 0xF) {
42244222 pred = 0xE;
42254223 S = MCDisassembler::SoftFail;
42264224 }
42274225
4228 if ((mask & 0xF) == 0) {
4229 // Preserve the high bit of the mask, which is the low bit of
4230 // the predicate.
4231 mask &= 0x10;
4226 if (mask == 0x0) {
42324227 mask |= 0x8;
42334228 S = MCDisassembler::SoftFail;
42344229 }
753753 raw_ostream &O) {
754754 // (3 - the number of trailing zeros) is the number of then / else.
755755 unsigned Mask = MI->getOperand(OpNum).getImm();
756 unsigned CondBit0 = Mask >> 4 & 1;
756 unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
757 unsigned CondBit0 = Firstcond & 1;
757758 unsigned NumTZ = CountTrailingZeros_32(Mask);
758759 assert(NumTZ <= 3 && "Invalid IT mask!");
759760 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {