llvm.org GIT mirror llvm / 4d0983a
ARM more NEON VLD/VST composite physical register refactoring. Register pair, all lanes subscripting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
6 changed file(s) with 59 addition(s) and 40 deletion(s). Raw diff Collapse all Expand all
162162 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
163163 }
164164 // Register list of two D registers spaced by 2 (two sequential Q registers).
165 def VecListTwoQAllLanesAsmOperand : AsmOperandClass {
166 let Name = "VecListTwoQAllLanes";
165 def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass {
166 let Name = "VecListDPairSpacedAllLanes";
167167 let ParserMethod = "parseVectorList";
168168 let RenderMethod = "addVecListOperands";
169169 }
170 def VecListTwoQAllLanes : RegisterOperand,
170 def VecListDPairSpacedAllLanes : RegisterOperand,
171171 "printVectorListTwoSpacedAllLanes"> {
172 let ParserMatchClass = VecListTwoQAllLanesAsmOperand;
172 let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
173173 }
174174 // Register list of three D registers, with "all lanes" subscripting.
175175 def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
13681368 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>;
13691369 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>;
13701370
1371 // ...with double-spaced registers (not used for codegen):
1372 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListTwoQAllLanes>;
1373 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListTwoQAllLanes>;
1374 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListTwoQAllLanes>;
1371 // ...with double-spaced registers
1372 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes>;
1373 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1374 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
13751375
13761376 // ...with address register writeback:
13771377 multiclass VLD2DUPWB op7_4, string Dt, RegisterOperand VdTy> {
14001400 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>;
14011401 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>;
14021402
1403 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListTwoQAllLanes>;
1404 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListTwoQAllLanes>;
1405 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListTwoQAllLanes>;
1403 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes>;
1404 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1405 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
14061406
14071407 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
14081408 class VLD3DUP op7_4, string Dt>
11001100 return VectorList.Count == 4;
11011101 }
11021102
1103 bool isVecListTwoQ() const {
1104 if (!isDoubleSpacedVectorList()) return false;
1105 return VectorList.Count == 2;
1106 }
1107
11081103 bool isVecListDPairSpaced() const {
11091104 if (!isSingleSpacedVectorList()) return false;
11101105 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
11381133 .contains(VectorList.RegNum));
11391134 }
11401135
1141 bool isVecListTwoQAllLanes() const {
1136 bool isVecListDPairSpacedAllLanes() const {
11421137 if (!isDoubleSpacedVectorAllLanes()) return false;
11431138 return VectorList.Count == 2;
11441139 }
31683163 case AllLanes:
31693164 // Two-register operands have been converted to the
31703165 // composite register classes.
3171 if (Count == 2 && Spacing == 1) {
3172 const MCRegisterClass *RC = &ARMMCRegisterClasses[ARM::DPairRegClassID];
3166 if (Count == 2) {
3167 const MCRegisterClass *RC = (Spacing == 1) ?
3168 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3169 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
31733170 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
31743171 }
31753172 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
25712571 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
25722572 return MCDisassembler::Fail;
25732573 break;
2574 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2575 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2576 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2577 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2578 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2579 return MCDisassembler::Fail;
2580 break;
25742581 default:
25752582 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
25762583 return MCDisassembler::Fail;
11031103 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
11041104 unsigned OpNum,
11051105 raw_ostream &O) {
1106 // Normally, it's not safe to use register enum values directly with
1107 // addition to get the next register, but for VFP registers, the
1108 // sort order is guaranteed because they're all of the form D.
1109 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1110 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
1106 unsigned Reg = MI->getOperand(OpNum).getReg();
1107 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1108 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1109 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
11111110 }
11121111
11131112 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
186186 case S31: case D31: return 31;
187187
188188 // Composite registers use the regnum of the first register in the list.
189 case D1_D2: return 1;
190 case D3_D5: return 3;
191 case D5_D7: return 5;
192 case D7_D9: return 7;
193 case D9_D10: return 9;
194 case D11_D12: return 11;
195 case D13_D14: return 13;
196 case D15_D16: return 15;
197 case D17_D18: return 17;
198 case D19_D20: return 19;
199 case D21_D22: return 21;
200 case D23_D24: return 23;
201 case D25_D26: return 25;
202 case D27_D28: return 27;
203 case D29_D30: return 29;
189 /* Q0 */ case D0_D2: return 0;
190 case D1_D2: case D1_D3: return 1;
191 /* Q1 */ case D2_D4: return 2;
192 case D3_D4: case D3_D5: return 3;
193 /* Q2 */ case D4_D6: return 4;
194 case D5_D6: case D5_D7: return 5;
195 /* Q3 */ case D6_D8: return 6;
196 case D7_D8: case D7_D9: return 7;
197 /* Q4 */ case D8_D10: return 8;
198 case D9_D10: case D9_D11: return 9;
199 /* Q5 */ case D10_D12: return 10;
200 case D11_D12: case D11_D13: return 11;
201 /* Q6 */ case D12_D14: return 12;
202 case D13_D14: case D13_D15: return 13;
203 /* Q7 */ case D14_D16: return 14;
204 case D15_D16: case D15_D17: return 15;
205 /* Q8 */ case D16_D18: return 16;
206 case D17_D18: case D17_D19: return 17;
207 /* Q9 */ case D18_D20: return 18;
208 case D19_D20: case D19_D21: return 19;
209 /* Q10 */ case D20_D22: return 20;
210 case D21_D22: case D21_D23: return 21;
211 /* Q11 */ case D22_D24: return 22;
212 case D23_D24: case D23_D25: return 23;
213 /* Q12 */ case D24_D26: return 24;
214 case D25_D26: case D25_D27: return 25;
215 /* Q13 */ case D26_D28: return 26;
216 case D27_D28: case D27_D29: return 27;
217 /* Q14 */ case D28_D30: return 28;
218 case D29_D30: case D29_D31: return 29;
219 /* Q15 */
204220 }
205221 }
206222
579579 REG("VecListFourD");
580580 REG("VecListOneDAllLanes");
581581 REG("VecListDPairAllLanes");
582 REG("VecListTwoQAllLanes");
582 REG("VecListDPairSpacedAllLanes");
583583
584584 IMM("i32imm");
585585 IMM("fbits16");