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[SelectionDAG] Add fcmp UNDEF handling to SelectionDAG::FoldSetCC Second half of PR40800, this patch adds DAG undef handling to fcmp instructions to match the behavior in llvm::ConstantFoldCompareInstruction, this permits constant folding of vector comparisons where some elements had been reduced to UNDEF (by SimplifyDemandedVectorElts etc.). This involves a lot of tweaking to reduced tests as bugpoint loves to reduce fcmp arguments to undef........ Differential Revision: https://reviews.llvm.org/D60006 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357765 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 9 months ago
8 changed file(s) with 228 addition(s) and 226 deletion(s). Raw diff Collapse all Expand all
20842084 case ISD::SETUGE: return getBoolConstant(R!=APFloat::cmpLessThan, dl, VT,
20852085 OpVT);
20862086 }
2087 } else if (N1CFP && OpVT.isSimple()) {
2087 } else if (N1CFP && OpVT.isSimple() && !N2.isUndef()) {
20882088 // Ensure that the constant occurs on the RHS.
20892089 ISD::CondCode SwappedCond = ISD::getSetCCSwappedOperands(Cond);
20902090 if (!TLI->isCondCodeLegal(SwappedCond, OpVT.getSimpleVT()))
20912091 return SDValue();
20922092 return getSetCC(dl, VT, N2, N1, SwappedCond);
2093 } else if (N2CFP && N2CFP->getValueAPF().isNaN()) {
2094 // If an operand is known to be a nan, we can fold it.
2093 } else if ((N2CFP && N2CFP->getValueAPF().isNaN()) ||
2094 (OpVT.isFloatingPoint() && (N1.isUndef() || N2.isUndef()))) {
2095 // If an operand is known to be a nan (or undef that could be a nan), we can
2096 // fold it.
2097 // Choosing NaN for the undef will always make unordered comparison succeed
2098 // and ordered comparison fails.
2099 // Matches behavior in llvm::ConstantFoldCompareInstruction.
20952100 switch (ISD::getUnorderedFlavor(Cond)) {
20962101 default:
20972102 llvm_unreachable("Unknown flavor!");
9595 ret void
9696 }
9797
98 define i16 @test_fccmp(i1 %a) {
98 define i16 @test_fccmp(i1 %a, i16 %in) {
9999 ; CHECK-LABEL: test_fccmp:
100100 ; CHECK: // %bb.0:
101101 ; CHECK-NEXT: mov w8, #24576
102 ; CHECK-NEXT: fmov s0, w1
102103 ; CHECK-NEXT: movk w8, #15974, lsl #16
103104 ; CHECK-NEXT: mov w9, #16384
105 ; CHECK-NEXT: fcvt s0, h0
104106 ; CHECK-NEXT: movk w9, #15428, lsl #16
105 ; CHECK-NEXT: fmov s0, w8
106 ; CHECK-NEXT: fcmp s0, s0
107 ; CHECK-NEXT: fmov s0, w9
107 ; CHECK-NEXT: fmov s1, w8
108 ; CHECK-NEXT: fcmp s0, s1
109 ; CHECK-NEXT: fmov s1, w9
108110 ; CHECK-NEXT: cset w8, pl
109 ; CHECK-NEXT: fccmp s0, s0, #8, pl
111 ; CHECK-NEXT: fccmp s0, s1, #8, pl
110112 ; CHECK-NEXT: mov w9, #4
111113 ; CHECK-NEXT: csinc w9, w9, wzr, mi
112114 ; CHECK-NEXT: add w0, w8, w9
113115 ; CHECK-NEXT: ret
114 %cmp0 = fcmp ogt half 0xH3333, undef
115 %cmp1 = fcmp ogt half 0xH2222, undef
116 %f16 = bitcast i16 %in to half
117 %cmp0 = fcmp ogt half 0xH3333, %f16
118 %cmp1 = fcmp ogt half 0xH2222, %f16
116119 %x = select i1 %cmp0, i16 0, i16 1
117120 %or = or i1 %cmp1, %cmp0
118121 %y = select i1 %or, i16 4, i16 1
11 ; RUN: llc < %s -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR
22 ; RUN: llc < %s -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8,+neon,+neonfp | FileCheck %s --check-prefixes=CHECK,NEON
33
4 define arm_aapcs_vfpcc float @foo0() local_unnamed_addr {
4 define arm_aapcs_vfpcc float @foo0(float %a0) local_unnamed_addr {
55 ; CHECK-LABEL: foo0:
66 ; CHECK: @ %bb.0:
7 ; CHECK-NEXT: vmov.f32 s0, #5.000000e-01
8 ; CHECK-NEXT: vmov.f32 s2, #-5.000000e-01
97 ; CHECK-NEXT: vcmpe.f32 s0, #0
8 ; CHECK-NEXT: vmov.f32 s2, #5.000000e-01
109 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
10 ; CHECK-NEXT: vmov.f32 s4, #-5.000000e-01
1111 ; CHECK-NEXT: it mi
12 ; CHECK-NEXT: vmovmi.f32 s0, s2
12 ; CHECK-NEXT: vmovmi.f32 s2, s4
13 ; CHECK-NEXT: vmov.f32 s0, s2
1314 ; CHECK-NEXT: bx lr
14 %1 = fcmp nsz olt float undef, 0.000000e+00
15 %1 = fcmp nsz olt float %a0, 0.000000e+00
1516 %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
1617 ret float %2
1718 }
1819
19 define arm_aapcs_vfpcc float @float1() local_unnamed_addr {
20 define arm_aapcs_vfpcc float @float1(float %a0) local_unnamed_addr {
2021 ; CHECK-LABEL: float1:
2122 ; CHECK: @ %bb.0: @ %.end
22 ; CHECK-NEXT: vmov.f32 s0, #1.000000e+00
23 ; CHECK-NEXT: vmov.f32 s2, #5.000000e-01
24 ; CHECK-NEXT: vmov.f32 s4, #-5.000000e-01
25 ; CHECK-NEXT: vcmpe.f32 s0, s0
23 ; CHECK-NEXT: vmov.f32 s2, #1.000000e+00
24 ; CHECK-NEXT: vmov.f32 s4, #5.000000e-01
25 ; CHECK-NEXT: vmov.f32 s6, #-5.000000e-01
26 ; CHECK-NEXT: vcmpe.f32 s2, s0
2627 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
27 ; CHECK-NEXT: vselgt.f32 s0, s4, s2
28 ; CHECK-NEXT: vselgt.f32 s0, s6, s4
2829 ; CHECK-NEXT: bx lr
2930 br i1 undef, label %.end, label %1
3031
31 %2 = fcmp nsz olt float undef, 1.000000e+00
32 %2 = fcmp nsz olt float %a0, 1.000000e+00
3233 %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
3334 br label %.end
3435
3738 ret float %4
3839 }
3940
40 define arm_aapcs_vfpcc float @float128() local_unnamed_addr {
41 define arm_aapcs_vfpcc float @float128(float %a0) local_unnamed_addr {
4142 ; VMOVSR-LABEL: float128:
4243 ; VMOVSR: @ %bb.0:
4344 ; VMOVSR-NEXT: mov.w r0, #1124073472
44 ; VMOVSR-NEXT: vmov.f32 s2, #5.000000e-01
45 ; VMOVSR-NEXT: vmov s0, r0
46 ; VMOVSR-NEXT: vmov.f32 s4, #-5.000000e-01
47 ; VMOVSR-NEXT: vcmpe.f32 s0, s0
45 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01
46 ; VMOVSR-NEXT: vmov s2, r0
47 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01
48 ; VMOVSR-NEXT: vcmpe.f32 s2, s0
4849 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr
49 ; VMOVSR-NEXT: vselgt.f32 s0, s4, s2
50 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4
5051 ; VMOVSR-NEXT: bx lr
5152 ;
5253 ; NEON-LABEL: float128:
5354 ; NEON: @ %bb.0:
54 ; NEON-NEXT: vmov.f32 s0, #5.000000e-01
5555 ; NEON-NEXT: mov.w r0, #1124073472
56 ; NEON-NEXT: vmov d2, r0, r0
57 ; NEON-NEXT: vmov.f32 s2, #-5.000000e-01
58 ; NEON-NEXT: vcmpe.f32 s4, s0
56 ; NEON-NEXT: vmov.f32 s2, #5.000000e-01
57 ; NEON-NEXT: vmov d3, r0, r0
58 ; NEON-NEXT: vmov.f32 s4, #-5.000000e-01
59 ; NEON-NEXT: vcmpe.f32 s6, s0
5960 ; NEON-NEXT: vmrs APSR_nzcv, fpscr
60 ; NEON-NEXT: vselgt.f32 s0, s2, s0
61 ; NEON-NEXT: vselgt.f32 s0, s4, s2
6162 ; NEON-NEXT: bx lr
62 %1 = fcmp nsz olt float undef, 128.000000e+00
63 %1 = fcmp nsz olt float %a0, 128.000000e+00
6364 %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
6465 ret float %2
6566 }
6667
67 define arm_aapcs_vfpcc double @double1() local_unnamed_addr {
68 define arm_aapcs_vfpcc double @double1(double %a0) local_unnamed_addr {
6869 ; CHECK-LABEL: double1:
6970 ; CHECK: @ %bb.0:
71 ; CHECK-NEXT: vmov.f64 d18, #1.000000e+00
72 ; CHECK-NEXT: vcmpe.f64 d18, d0
73 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
7074 ; CHECK-NEXT: vmov.f64 d16, #5.000000e-01
71 ; CHECK-NEXT: vmov.f64 d18, #1.000000e+00
72 ; CHECK-NEXT: vcmpe.f64 d18, d16
75 ; CHECK-NEXT: vmov.f64 d17, #-5.000000e-01
76 ; CHECK-NEXT: vselgt.f64 d0, d17, d16
77 ; CHECK-NEXT: bx lr
78 %1 = fcmp nsz olt double %a0, 1.000000e+00
79 %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
80 ret double %2
81 }
82
83 define arm_aapcs_vfpcc double @double128(double %a0) local_unnamed_addr {
84 ; CHECK-LABEL: double128:
85 ; CHECK: @ %bb.0:
86 ; CHECK-NEXT: movs r0, #0
87 ; CHECK-NEXT: movs r1, #0
88 ; CHECK-NEXT: movt r0, #16480
89 ; CHECK-NEXT: vmov.f64 d16, #5.000000e-01
90 ; CHECK-NEXT: vmov d18, r1, r0
91 ; CHECK-NEXT: vcmpe.f64 d18, d0
7392 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
7493 ; CHECK-NEXT: vmov.f64 d17, #-5.000000e-01
7594 ; CHECK-NEXT: vselgt.f64 d0, d17, d16
7695 ; CHECK-NEXT: bx lr
77 %1 = fcmp nsz olt double undef, 1.000000e+00
96 %1 = fcmp nsz olt double %a0, 128.000000e+00
7897 %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
7998 ret double %2
8099 }
81
82 define arm_aapcs_vfpcc double @double128() local_unnamed_addr {
83 ; CHECK-LABEL: double128:
84 ; CHECK: @ %bb.0:
85 ; CHECK-NEXT: vmov.f64 d16, #5.000000e-01
86 ; CHECK-NEXT: movs r0, #0
87 ; CHECK-NEXT: movt r0, #16480
88 ; CHECK-NEXT: movs r1, #0
89 ; CHECK-NEXT: vmov d18, r1, r0
90 ; CHECK-NEXT: vcmpe.f64 d18, d16
91 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
92 ; CHECK-NEXT: vmov.f64 d17, #-5.000000e-01
93 ; CHECK-NEXT: vselgt.f64 d0, d17, d16
94 ; CHECK-NEXT: bx lr
95 %1 = fcmp nsz olt double undef, 128.000000e+00
96 %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
97 ret double %2
98 }
700700 ; 34. VRINTZ
701701
702702 ; 35. VSELEQ
703 define half @select_cc1() {
704 %1 = fcmp nsz oeq half undef, 0xH0001
705 %2 = select i1 %1, half 0xHC000, half 0xH0002
706 ret half %2
703 define half @select_cc1(half* %a0) {
704 %1 = load half, half* %a0
705 %2 = fcmp nsz oeq half %1, 0xH0001
706 %3 = select i1 %2, half 0xHC000, half 0xH0002
707 ret half %3
707708
708709 ; CHECK-LABEL: select_cc1:
709710
710 ; CHECK-HARDFP-FULLFP16: vcmp.f16 s0, s0
711 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
711 ; CHECK-HARDFP-FULLFP16: vcmp.f16 s6, s0
712 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
712713 ; CHECK-HARDFP-FULLFP16: vseleq.f16 s0, s{{.}}, s{{.}}
713714
714 ; CHECK-SOFTFP-FP16-A32: vcmp.f32 s0, s0
715 ; CHECK-SOFTFP-FP16-A32: vcmp.f32 s6, s0
715716 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
716717 ; CHECK-SOFTFP-FP16-A32-NEXT: vmoveq.f32 s{{.}}, s{{.}}
717718
718 ; CHECK-SOFTFP-FP16-T32: vcmp.f32 s0, s0
719 ; CHECK-SOFTFP-FP16-T32: vcmp.f32 s6, s0
719720 ; CHECK-SOFTFP-FP16-T32: vmrs APSR_nzcv, fpscr
720721 ; CHECK-SOFTFP-FP16-T32: it eq
721722 ; CHECK-SOFTFP-FP16-T32: vmoveq.f32 s{{.}}, s{{.}}
726727 ; be encoded as an FP16 immediate need to be added here.
727728 ;
728729 ; 36. VSELGE
729 define half @select_cc_ge1() {
730 %1 = fcmp nsz oge half undef, 0xH0001
731 %2 = select i1 %1, half 0xHC000, half 0xH0002
732 ret half %2
730 define half @select_cc_ge1(half* %a0) {
731 %1 = load half, half* %a0
732 %2 = fcmp nsz oge half %1, 0xH0001
733 %3 = select i1 %2, half 0xHC000, half 0xH0002
734 ret half %3
733735
734736 ; CHECK-LABEL: select_cc_ge1:
735737
736 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s0
737 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
738 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s6, s0
739 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
738740 ; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0, s{{.}}, s{{.}}
739741
740 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
742 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s6, s0
741743 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
742744 ; CHECK-SOFTFP-FP16-A32-NEXT: vmovge.f32 s{{.}}, s{{.}}
743745
744 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s0, s0
746 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s6, s0
745747 ; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
746748 ; CHECK-SOFTFP-FP16-T32-NEXT: it ge
747749 ; CHECK-SOFTFP-FP16-T32-NEXT: vmovge.f32 s{{.}}, s{{.}}
748750 }
749751
750 define half @select_cc_ge2() {
751 %1 = fcmp nsz ole half undef, 0xH0001
752 %2 = select i1 %1, half 0xHC000, half 0xH0002
753 ret half %2
752 define half @select_cc_ge2(half* %a0) {
753 %1 = load half, half* %a0
754 %2 = fcmp nsz ole half %1, 0xH0001
755 %3 = select i1 %2, half 0xHC000, half 0xH0002
756 ret half %3
754757
755758 ; CHECK-LABEL: select_cc_ge2:
756759
757 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s0
760 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s6
758761 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
759762 ; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0, s{{.}}, s{{.}}
760763
761 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
764 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s6, s0
762765 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
763766 ; CHECK-SOFTFP-FP16-A32-NEXT: vmovls.f32 s{{.}}, s{{.}}
764767
765 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s0, s0
768 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s6, s0
766769 ; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
767770 ; CHECK-SOFTFP-FP16-T32-NEXT: it ls
768771 ; CHECK-SOFTFP-FP16-T32-NEXT: vmovls.f32 s{{.}}, s{{.}}
769772 }
770773
771 define half @select_cc_ge3() {
772 %1 = fcmp nsz ugt half undef, 0xH0001
773 %2 = select i1 %1, half 0xHC000, half 0xH0002
774 ret half %2
774 define half @select_cc_ge3(half* %a0) {
775 %1 = load half, half* %a0
776 %2 = fcmp nsz ugt half %1, 0xH0001
777 %3 = select i1 %2, half 0xHC000, half 0xH0002
778 ret half %3
775779
776780 ; CHECK-LABEL: select_cc_ge3:
777781
778 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s0
782 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s6
779783 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
780784 ; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0, s{{.}}, s{{.}}
781785
782 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
786 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s6, s0
783787 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
784788 ; CHECK-SOFTFP-FP16-A32-NEXT: vmovhi.f32 s{{.}}, s{{.}}
785789
786 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s0, s0
790 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s6, s0
787791 ; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
788792 ; CHECK-SOFTFP-FP16-T32-NEXT: it hi
789793 ; CHECK-SOFTFP-FP16-T32-NEXT: vmovhi.f32 s{{.}}, s{{.}}
790794 }
791795
792 define half @select_cc_ge4() {
793 %1 = fcmp nsz ult half undef, 0xH0001
794 %2 = select i1 %1, half 0xHC000, half 0xH0002
795 ret half %2
796 define half @select_cc_ge4(half* %a0) {
797 %1 = load half, half* %a0
798 %2 = fcmp nsz ult half %1, 0xH0001
799 %3 = select i1 %2, half 0xHC000, half 0xH0002
800 ret half %3
796801
797802 ; CHECK-LABEL: select_cc_ge4:
798803
799 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s0
804 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s6, s0
800805 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
801806 ; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0, s{{.}}, s{{.}}
802807
803 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
808 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s6, s0
804809 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
805810 ; CHECK-SOFTFP-FP16-A32-NEXT: vmovlt.f32 s{{.}}, s{{.}}
806811
807 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s0, s0
812 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s6, s0
808813 ; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
809814 ; CHECK-SOFTFP-FP16-T32-NEXT: it lt
810815 ; CHECK-SOFTFP-FP16-T32-NEXT: vmovlt.f32 s{{.}}, s{{.}}
811816 }
812817
813818 ; 37. VSELGT
814 define half @select_cc_gt1() {
815 %1 = fcmp nsz ogt half undef, 0xH0001
816 %2 = select i1 %1, half 0xHC000, half 0xH0002
817 ret half %2
819 define half @select_cc_gt1(half* %a0) {
820 %1 = load half, half* %a0
821 %2 = fcmp nsz ogt half %1, 0xH0001
822 %3 = select i1 %2, half 0xHC000, half 0xH0002
823 ret half %3
818824
819825 ; CHECK-LABEL: select_cc_gt1:
820826
821 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s0
827 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s6, s0
822828 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
823829 ; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
824830
825 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
831 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s6, s0
826832 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
827833 ; CHECK-SOFTFP-FP16-A32-NEXT: vmovgt.f32 s{{.}}, s{{.}}
828834
829 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s0, s0
835 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s6, s0
830836 ; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
831837 ; CHECK-SOFTFP-FP16-T32-NEXT: it gt
832838 ; CHECK-SOFTFP-FP16-T32-NEXT: vmovgt.f32 s{{.}}, s{{.}}
833839 }
834840
835 define half @select_cc_gt2() {
836 %1 = fcmp nsz uge half undef, 0xH0001
837 %2 = select i1 %1, half 0xHC000, half 0xH0002
838 ret half %2
841 define half @select_cc_gt2(half* %a0) {
842 %1 = load half, half* %a0
843 %2 = fcmp nsz uge half %1, 0xH0001
844 %3 = select i1 %2, half 0xHC000, half 0xH0002
845 ret half %3
839846
840847 ; CHECK-LABEL: select_cc_gt2:
841848
842 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s0
849 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s6
843850 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
844851 ; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
845852
846 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
853 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s6, s0
847854 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
848855 ; CHECK-SOFTFP-FP16-A32-NEXT: vmovpl.f32 s{{.}}, s{{.}}
849856
850 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s0, s0
857 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s6, s0
851858 ; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
852859 ; CHECK-SOFTFP-FP16-T32-NEXT: it pl
853860 ; CHECK-SOFTFP-FP16-T32-NEXT: vmovpl.f32 s{{.}}, s{{.}}
854861 }
855862
856 define half @select_cc_gt3() {
857 %1 = fcmp nsz ule half undef, 0xH0001
858 %2 = select i1 %1, half 0xHC000, half 0xH0002
859 ret half %2
863 define half @select_cc_gt3(half* %a0) {
864 %1 = load half, half* %a0
865 %2 = fcmp nsz ule half %1, 0xH0001
866 %3 = select i1 %2, half 0xHC000, half 0xH0002
867 ret half %3
860868
861869 ; CHECK-LABEL: select_cc_gt3:
862870
863 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s0
871 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s6, s0
864872 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
865873 ; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
866874
867 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
875 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s6, s0
868876 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
869877 ; CHECK-SOFTFP-FP16-A32-NEXT: vmovle.f32 s{{.}}, s{{.}}
870878
871 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s0, s0
879 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s6, s0
872880 ; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
873881 ; CHECK-SOFTFP-FP16-T32-NEXT: it le
874882 ; CHECK-SOFTFP-FP16-T32-NEXT: vmovle.f32 s{{.}}, s{{.}}
875883 }
876884
877 define half @select_cc_gt4() {
878 %1 = fcmp nsz olt half undef, 0xH0001
879 %2 = select i1 %1, half 0xHC000, half 0xH0002
880 ret half %2
885 define half @select_cc_gt4(half* %a0) {
886 %1 = load half, half* %a0
887 %2 = fcmp nsz olt half %1, 0xH0001
888 %3 = select i1 %2, half 0xHC000, half 0xH0002
889 ret half %3
881890
882891 ; CHECK-LABEL: select_cc_gt4:
883892
884 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s0
893 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s6
885894 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
886895 ; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
887896
888 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
897 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s6, s0
889898 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
890899 ; CHECK-SOFTFP-FP16-A32-NEXT: vmovmi.f32 s{{.}}, s{{.}}
891900
892 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s0, s0
901 ; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s6, s0
893902 ; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
894903 ; CHECK-SOFTFP-FP16-T32-NEXT: it mi
895904 ; CHECK-SOFTFP-FP16-T32-NEXT: vmovmi.f32 s{{.}}, s{{.}}
278278 ; Radar 8782191
279279 ; Floating-point comparisons against zero produce results with integer
280280 ; elements, not floating-point elements.
281 define void @test_vclez_fp() nounwind optsize {
281 define void @test_vclez_fp(<4 x float>* %A) nounwind optsize {
282282 ; CHECK-LABEL: test_vclez_fp:
283283 ; CHECK: @ %bb.0: @ %entry
284 ; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
284285 ; CHECK-NEXT: vcle.f32 q8, q8, #0
285286 ; CHECK-NEXT: vmovn.i32 d16, q8
286287 ; CHECK-NEXT: vmov.i8 d17, #0x1
288289 ; CHECK-NEXT: vadd.i8 d16, d16, d17
289290 ; CHECK-NEXT: vst1.8 {d16}, [r0]
290291 entry:
291 %0 = fcmp ole <4 x float> undef, zeroinitializer
292 %ld = load <4 x float>, <4 x float>* %A
293 %0 = fcmp ole <4 x float> %ld, zeroinitializer
292294 %1 = sext <4 x i1> %0 to <4 x i16>
293295 %2 = add <4 x i16> %1, zeroinitializer
294296 %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32>
7272 ; SOFT: _Q_cmp
7373 ; SOFT: cmp
7474
75 define i32 @f128_compare2() {
76 entry:
77 %0 = fcmp ogt fp128 undef, 0xL00000000000000000000000000000000
78 br i1 %0, label %"5", label %"7"
75 define i32 @f128_compare2(fp128* byval %f0) {
76 entry:
77 %0 = load fp128, fp128* %f0, align 8
78 %1 = fcmp ogt fp128 %0, 0xL00000000000000000000000000000000
79 br i1 %1, label %"5", label %"7"
7980
8081 "5": ; preds = %entry
8182 ret i32 0
468468 ret i32 %merge
469469 }
470470
471 define void @fpcmp_unanalyzable_branch(i1 %cond) {
471 define void @fpcmp_unanalyzable_branch(i1 %cond, double %a0) {
472472 ; This function's CFG contains an once-unanalyzable branch (une on floating
473473 ; points). As now it becomes analyzable, we should get best layout in which each
474474 ; edge in 'entry' -> 'entry.if.then_crit_edge' -> 'if.then' -> 'if.end' is
497497 br i1 undef, label %if.end, label %exit
498498
499499 exit:
500 %cmp.i = fcmp une double 0.000000e+00, undef
500 %cmp.i = fcmp une double 0.000000e+00, %a0
501501 br i1 %cmp.i, label %if.then, label %if.end, !prof !3
502502
503503 if.then:
640640 br label %loop1
641641 }
642642
643 define void @unanalyzable_branch_to_loop_header() {
643 define void @unanalyzable_branch_to_loop_header(double %a0) {
644644 ; Ensure that we can handle unanalyzable branches into loop headers. We
645645 ; pre-form chains for unanalyzable branches, and will find the tail end of that
646646 ; at the start of the loop. This function uses floating point comparison
653653 ; CHECK: %exit
654654
655655 entry:
656 %cmp = fcmp une double 0.000000e+00, undef
656 %cmp = fcmp une double 0.000000e+00, %a0
657657 br i1 %cmp, label %loop, label %exit
658658
659659 loop:
664664 ret void
665665 }
666666
667 define void @unanalyzable_branch_to_best_succ(i1 %cond) {
667 define void @unanalyzable_branch_to_best_succ(i1 %cond, double %a0) {
668668 ; Ensure that we can handle unanalyzable branches where the destination block
669669 ; gets selected as the optimal successor to merge.
670670 ;
682682 br i1 %cond, label %bar, label %foo, !prof !1
683683
684684 foo:
685 %cmp = fcmp une double 0.000000e+00, undef
685 %cmp = fcmp une double 0.000000e+00, %a0
686686 br i1 %cmp, label %bar, label %exit
687687
688688 bar:
712712 br label %c
713713
714714 b:
715 %cmp = fcmp une float %x, undef
715 %cmp = fcmp une float %x, 0.0
716716 br i1 %cmp, label %c, label %exit
717717
718718 c:
735735 br label %0
736736
737737 %val0 = load volatile float, float* undef
738 %cmp0 = fcmp une float %val0, undef
738 %cmp0 = fcmp une float %val0, 0.0
739739 br i1 %cmp0, label %1, label %0
740740 %val1 = load volatile float, float* undef
741 %cmp1 = fcmp une float %val1, undef
741 %cmp1 = fcmp une float %val1, 0.0
742742 br i1 %cmp1, label %2, label %1
743743 %val2 = load volatile float, float* undef
744 %cmp2 = fcmp une float %val2, undef
744 %cmp2 = fcmp une float %val2, 0.0
745745 br i1 %cmp2, label %3, label %2
746746 %val3 = load volatile float, float* undef
747 %cmp3 = fcmp une float %val3, undef
747 %cmp3 = fcmp une float %val3, 0.0
748748 br i1 %cmp3, label %4, label %3
749749 %val4 = load volatile float, float* undef
750 %cmp4 = fcmp une float %val4, undef
750 %cmp4 = fcmp une float %val4, 0.0
751751 br i1 %cmp4, label %5, label %4
752752 %val5 = load volatile float, float* undef
753 %cmp5 = fcmp une float %val5, undef
753 %cmp5 = fcmp une float %val5, 0.0
754754 br i1 %cmp5, label %6, label %5
755755 %val6 = load volatile float, float* undef
756 %cmp6 = fcmp une float %val6, undef
756 %cmp6 = fcmp une float %val6, 0.0
757757 br i1 %cmp6, label %7, label %6
758758 %val7 = load volatile float, float* undef
759 %cmp7 = fcmp une float %val7, undef
759 %cmp7 = fcmp une float %val7, 0.0
760760 br i1 %cmp7, label %8, label %7
761761 %val8 = load volatile float, float* undef
762 %cmp8 = fcmp une float %val8, undef
762 %cmp8 = fcmp une float %val8, 0.0
763763 br i1 %cmp8, label %9, label %8
764764 %val9 = load volatile float, float* undef
765 %cmp9 = fcmp une float %val9, undef
765 %cmp9 = fcmp une float %val9, 0.0
766766 br i1 %cmp9, label %10, label %9
767767 %val10 = load volatile float, float* undef
768 %cmp10 = fcmp une float %val10, undef
768 %cmp10 = fcmp une float %val10, 0.0
769769 br i1 %cmp10, label %11, label %10
770770 %val11 = load volatile float, float* undef
771 %cmp11 = fcmp une float %val11, undef
771 %cmp11 = fcmp une float %val11, 0.0
772772 br i1 %cmp11, label %12, label %11
773773 %val12 = load volatile float, float* undef
774 %cmp12 = fcmp une float %val12, undef
774 %cmp12 = fcmp une float %val12, 0.0
775775 br i1 %cmp12, label %13, label %12
776776 %val13 = load volatile float, float* undef
777 %cmp13 = fcmp une float %val13, undef
777 %cmp13 = fcmp une float %val13, 0.0
778778 br i1 %cmp13, label %14, label %13
779779 %val14 = load volatile float, float* undef
780 %cmp14 = fcmp une float %val14, undef
780 %cmp14 = fcmp une float %val14, 0.0
781781 br i1 %cmp14, label %15, label %14
782782 %val15 = load volatile float, float* undef
783 %cmp15 = fcmp une float %val15, undef
783 %cmp15 = fcmp une float %val15, 0.0
784784 br i1 %cmp15, label %16, label %15
785785 %val16 = load volatile float, float* undef
786 %cmp16 = fcmp une float %val16, undef
786 %cmp16 = fcmp une float %val16, 0.0
787787 br i1 %cmp16, label %17, label %16
788788 %val17 = load volatile float, float* undef
789 %cmp17 = fcmp une float %val17, undef
789 %cmp17 = fcmp une float %val17, 0.0
790790 br i1 %cmp17, label %18, label %17
791791 %val18 = load volatile float, float* undef
792 %cmp18 = fcmp une float %val18, undef
792 %cmp18 = fcmp une float %val18, 0.0
793793 br i1 %cmp18, label %19, label %18
794794 %val19 = load volatile float, float* undef
795 %cmp19 = fcmp une float %val19, undef
795 %cmp19 = fcmp une float %val19, 0.0
796796 br i1 %cmp19, label %20, label %19
797797 %val20 = load volatile float, float* undef
798 %cmp20 = fcmp une float %val20, undef
798 %cmp20 = fcmp une float %val20, 0.0
799799 br i1 %cmp20, label %21, label %20
800800 %val21 = load volatile float, float* undef
801 %cmp21 = fcmp une float %val21, undef
801 %cmp21 = fcmp une float %val21, 0.0
802802 br i1 %cmp21, label %22, label %21
803803 %val22 = load volatile float, float* undef
804 %cmp22 = fcmp une float %val22, undef
804 %cmp22 = fcmp une float %val22, 0.0
805805 br i1 %cmp22, label %23, label %22
806806 %val23 = load volatile float, float* undef
807 %cmp23 = fcmp une float %val23, undef
807 %cmp23 = fcmp une float %val23, 0.0
808808 br i1 %cmp23, label %24, label %23
809809 %val24 = load volatile float, float* undef
810 %cmp24 = fcmp une float %val24, undef
810 %cmp24 = fcmp une float %val24, 0.0
811811 br i1 %cmp24, label %25, label %24
812812 %val25 = load volatile float, float* undef
813 %cmp25 = fcmp une float %val25, undef
813 %cmp25 = fcmp une float %val25, 0.0
814814 br i1 %cmp25, label %26, label %25
815815 %val26 = load volatile float, float* undef
816 %cmp26 = fcmp une float %val26, undef
816 %cmp26 = fcmp une float %val26, 0.0
817817 br i1 %cmp26, label %27, label %26
818818 %val27 = load volatile float, float* undef
819 %cmp27 = fcmp une float %val27, undef
819 %cmp27 = fcmp une float %val27, 0.0
820820 br i1 %cmp27, label %28, label %27
821821 %val28 = load volatile float, float* undef
822 %cmp28 = fcmp une float %val28, undef
822 %cmp28 = fcmp une float %val28, 0.0
823823 br i1 %cmp28, label %29, label %28
824824 %val29 = load volatile float, float* undef
825 %cmp29 = fcmp une float %val29, undef
825 %cmp29 = fcmp une float %val29, 0.0
826826 br i1 %cmp29, label %30, label %29
827827 %val30 = load volatile float, float* undef
828 %cmp30 = fcmp une float %val30, undef
828 %cmp30 = fcmp une float %val30, 0.0
829829 br i1 %cmp30, label %31, label %30
830830 %val31 = load volatile float, float* undef
831 %cmp31 = fcmp une float %val31, undef
831 %cmp31 = fcmp une float %val31, 0.0
832832 br i1 %cmp31, label %32, label %31
833833 %val32 = load volatile float, float* undef
834 %cmp32 = fcmp une float %val32, undef
834 %cmp32 = fcmp une float %val32, 0.0
835835 br i1 %cmp32, label %33, label %32
836836 %val33 = load volatile float, float* undef
837 %cmp33 = fcmp une float %val33, undef
837 %cmp33 = fcmp une float %val33, 0.0
838838 br i1 %cmp33, label %34, label %33
839839 %val34 = load volatile float, float* undef
840 %cmp34 = fcmp une float %val34, undef
840 %cmp34 = fcmp une float %val34, 0.0
841841 br i1 %cmp34, label %35, label %34
842842 %val35 = load volatile float, float* undef
843 %cmp35 = fcmp une float %val35, undef
843 %cmp35 = fcmp une float %val35, 0.0
844844 br i1 %cmp35, label %36, label %35
845845 %val36 = load volatile float, float* undef
846 %cmp36 = fcmp une float %val36, undef
846 %cmp36 = fcmp une float %val36, 0.0
847847 br i1 %cmp36, label %37, label %36
848848 %val37 = load volatile float, float* undef
849 %cmp37 = fcmp une float %val37, undef
849 %cmp37 = fcmp une float %val37, 0.0
850850 br i1 %cmp37, label %38, label %37
851851 %val38 = load volatile float, float* undef
852 %cmp38 = fcmp une float %val38, undef
852 %cmp38 = fcmp une float %val38, 0.0
853853 br i1 %cmp38, label %39, label %38
854854 %val39 = load volatile float, float* undef
855 %cmp39 = fcmp une float %val39, undef
855 %cmp39 = fcmp une float %val39, 0.0
856856 br i1 %cmp39, label %40, label %39
857857 %val40 = load volatile float, float* undef
858 %cmp40 = fcmp une float %val40, undef
858 %cmp40 = fcmp une float %val40, 0.0
859859 br i1 %cmp40, label %41, label %40
860860 %val41 = load volatile float, float* undef
861861 %cmp41 = fcmp une float %val41, undef
862862 br i1 %cmp41, label %42, label %41
863863 %val42 = load volatile float, float* undef
864 %cmp42 = fcmp une float %val42, undef
864 %cmp42 = fcmp une float %val42, 0.0
865865 br i1 %cmp42, label %43, label %42
866866 %val43 = load volatile float, float* undef
867 %cmp43 = fcmp une float %val43, undef
867 %cmp43 = fcmp une float %val43, 0.0
868868 br i1 %cmp43, label %44, label %43
869869 %val44 = load volatile float, float* undef
870 %cmp44 = fcmp une float %val44, undef
870 %cmp44 = fcmp une float %val44, 0.0
871871 br i1 %cmp44, label %45, label %44
872872 %val45 = load volatile float, float* undef
873 %cmp45 = fcmp une float %val45, undef
873 %cmp45 = fcmp une float %val45, 0.0
874874 br i1 %cmp45, label %46, label %45
875875 %val46 = load volatile float, float* undef
876 %cmp46 = fcmp une float %val46, undef
876 %cmp46 = fcmp une float %val46, 0.0
877877 br i1 %cmp46, label %47, label %46
878878 %val47 = load volatile float, float* undef
879 %cmp47 = fcmp une float %val47, undef
879 %cmp47 = fcmp une float %val47, 0.0
880880 br i1 %cmp47, label %48, label %47
881881 %val48 = load volatile float, float* undef
882 %cmp48 = fcmp une float %val48, undef
882 %cmp48 = fcmp une float %val48, 0.0
883883 br i1 %cmp48, label %49, label %48
884884 %val49 = load volatile float, float* undef
885 %cmp49 = fcmp une float %val49, undef
885 %cmp49 = fcmp une float %val49, 0.0
886886 br i1 %cmp49, label %50, label %49
887887 %val50 = load volatile float, float* undef
888 %cmp50 = fcmp une float %val50, undef
888 %cmp50 = fcmp une float %val50, 0.0
889889 br i1 %cmp50, label %51, label %50
890890 %val51 = load volatile float, float* undef
891 %cmp51 = fcmp une float %val51, undef
891 %cmp51 = fcmp une float %val51, 0.0
892892 br i1 %cmp51, label %52, label %51
893893 %val52 = load volatile float, float* undef
894 %cmp52 = fcmp une float %val52, undef
894 %cmp52 = fcmp une float %val52, 0.0
895895 br i1 %cmp52, label %53, label %52
896896 %val53 = load volatile float, float* undef
897 %cmp53 = fcmp une float %val53, undef
897 %cmp53 = fcmp une float %val53, 0.0
898898 br i1 %cmp53, label %54, label %53
899899 %val54 = load volatile float, float* undef
900 %cmp54 = fcmp une float %val54, undef
900 %cmp54 = fcmp une float %val54, 0.0
901901 br i1 %cmp54, label %55, label %54
902902 %val55 = load volatile float, float* undef
903 %cmp55 = fcmp une float %val55, undef
903 %cmp55 = fcmp une float %val55, 0.0
904904 br i1 %cmp55, label %56, label %55
905905 %val56 = load volatile float, float* undef
906 %cmp56 = fcmp une float %val56, undef
906 %cmp56 = fcmp une float %val56, 0.0
907907 br i1 %cmp56, label %57, label %56
908908 %val57 = load volatile float, float* undef
909 %cmp57 = fcmp une float %val57, undef
909 %cmp57 = fcmp une float %val57, 0.0
910910 br i1 %cmp57, label %58, label %57
911911 %val58 = load volatile float, float* undef
912 %cmp58 = fcmp une float %val58, undef
912 %cmp58 = fcmp une float %val58, 0.0
913913 br i1 %cmp58, label %59, label %58
914914 %val59 = load volatile float, float* undef
915 %cmp59 = fcmp une float %val59, undef
915 %cmp59 = fcmp une float %val59, 0.0
916916 br i1 %cmp59, label %60, label %59
917917 %val60 = load volatile float, float* undef
918 %cmp60 = fcmp une float %val60, undef
918 %cmp60 = fcmp une float %val60, 0.0
919919 br i1 %cmp60, label %61, label %60
920920 %val61 = load volatile float, float* undef
921 %cmp61 = fcmp une float %val61, undef
921 %cmp61 = fcmp une float %val61, 0.0
922922 br i1 %cmp61, label %62, label %61
923923 %val62 = load volatile float, float* undef
924 %cmp62 = fcmp une float %val62, undef
924 %cmp62 = fcmp une float %val62, 0.0
925925 br i1 %cmp62, label %63, label %62
926926 %val63 = load volatile float, float* undef
927 %cmp63 = fcmp une float %val63, undef
927 %cmp63 = fcmp une float %val63, 0.0
928928 br i1 %cmp63, label %64, label %63
929929 %val64 = load volatile float, float* undef
930 %cmp64 = fcmp une float %val64, undef
930 %cmp64 = fcmp une float %val64, 0.0
931931 br i1 %cmp64, label %65, label %64
932932
933933 br label %exit
1717 define <2 x i64> @fcmp_oeq_v2f64_undef() {
1818 ; CHECK-LABEL: fcmp_oeq_v2f64_undef:
1919 ; CHECK: # %bb.0:
20 ; CHECK-NEXT: cmpeqpd {{.*}}(%rip), %xmm0
20 ; CHECK-NEXT: xorps %xmm0, %xmm0
2121 ; CHECK-NEXT: retq
2222 %1 = fcmp oeq <2 x double> , undef
2323 %2 = sext <2 x i1> %1 to <2 x i64>
2727 define <2 x i64> @fcmp_oeq_v2f64_undef_elt() {
2828 ; CHECK-LABEL: fcmp_oeq_v2f64_undef_elt:
2929 ; CHECK: # %bb.0:
30 ; CHECK-NEXT: movapd {{.*#+}} xmm0 =
31 ; CHECK-NEXT: cmpeqpd {{.*}}(%rip), %xmm0
30 ; CHECK-NEXT: xorps %xmm0, %xmm0
3231 ; CHECK-NEXT: retq
3332 %1 = fcmp oeq <2 x double> ,
3433 %2 = sext <2 x i1> %1 to <2 x i64>
4847 define <4 x i32> @fcmp_oeq_v4f32_undef() {
4948 ; CHECK-LABEL: fcmp_oeq_v4f32_undef:
5049 ; CHECK: # %bb.0:
51 ; CHECK-NEXT: cmpeqps {{.*}}(%rip), %xmm0
50 ; CHECK-NEXT: xorps %xmm0, %xmm0
5251 ; CHECK-NEXT: retq
5352 %1 = fcmp oeq <4 x float> , undef
5453 %2 = sext <4 x i1> %1 to <4 x i32>
5857 define <4 x i32> @fcmp_oeq_v4f32_undef_elt() {
5958 ; CHECK-LABEL: fcmp_oeq_v4f32_undef_elt:
6059 ; CHECK: # %bb.0:
61 ; CHECK-NEXT: movaps {{.*#+}} xmm0 =
62 ; CHECK-NEXT: cmpeqps {{.*}}(%rip), %xmm0
60 ; CHECK-NEXT: movaps {{.*#+}} xmm0 = [0,4294967295,4294967295,0]
6361 ; CHECK-NEXT: retq
6462 %1 = fcmp oeq <4 x float> ,
6563 %2 = sext <4 x i1> %1 to <4 x i32>
8381 define <2 x i64> @fcmp_ueq_v2f64_undef() {
8482 ; CHECK-LABEL: fcmp_ueq_v2f64_undef:
8583 ; CHECK: # %bb.0:
86 ; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.0E+0,-1.7976931348623157E+308]
87 ; CHECK-NEXT: movapd %xmm0, %xmm1
88 ; CHECK-NEXT: cmpeqpd %xmm0, %xmm1
89 ; CHECK-NEXT: cmpunordpd %xmm0, %xmm0
90 ; CHECK-NEXT: orpd %xmm1, %xmm0
84 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
9185 ; CHECK-NEXT: retq
9286 %1 = fcmp ueq <2 x double> , undef
9387 %2 = sext <2 x i1> %1 to <2 x i64>
9791 define <2 x i64> @fcmp_ueq_v2f64_undef_elt() {
9892 ; CHECK-LABEL: fcmp_ueq_v2f64_undef_elt:
9993 ; CHECK: # %bb.0:
100 ; CHECK-NEXT: movapd {{.*#+}} xmm1 =
101 ; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.0E+0,-1.7976931348623157E+308]
102 ; CHECK-NEXT: movapd %xmm0, %xmm2
103 ; CHECK-NEXT: cmpeqpd %xmm1, %xmm2
104 ; CHECK-NEXT: cmpunordpd %xmm1, %xmm0
105 ; CHECK-NEXT: orpd %xmm2, %xmm0
94 ; CHECK-NEXT: movq $-1, %rax
95 ; CHECK-NEXT: movq %rax, %xmm0
10696 ; CHECK-NEXT: retq
10797 %1 = fcmp ueq <2 x double> ,
10898 %2 = sext <2 x i1> %1 to <2 x i64>
122112 define <4 x i32> @fcmp_ueq_v4f32_undef() {
123113 ; CHECK-LABEL: fcmp_ueq_v4f32_undef:
124114 ; CHECK: # %bb.0:
125 ; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,-1.0E+0,2.0E+0,-0.0E+0]
126 ; CHECK-NEXT: movaps %xmm0, %xmm1
127 ; CHECK-NEXT: cmpeqps %xmm0, %xmm1
128 ; CHECK-NEXT: cmpunordps %xmm0, %xmm0
129 ; CHECK-NEXT: orps %xmm1, %xmm0
115 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
130116 ; CHECK-NEXT: retq
131117 %1 = fcmp ueq <4 x float> , undef
132118 %2 = sext <4 x i1> %1 to <4 x i32>
136122 define <4 x i32> @fcmp_ueq_v4f32_undef_elt() {
137123 ; CHECK-LABEL: fcmp_ueq_v4f32_undef_elt:
138124 ; CHECK: # %bb.0:
139 ; CHECK-NEXT: movaps {{.*#+}} xmm1 =
140 ; CHECK-NEXT: movaps {{.*#+}} xmm0 = <-0.0E+0,1.0E+0,-1.0E+0,u>
141 ; CHECK-NEXT: movaps %xmm0, %xmm2
142 ; CHECK-NEXT: cmpeqps %xmm1, %xmm2
143 ; CHECK-NEXT: cmpunordps %xmm1, %xmm0
144 ; CHECK-NEXT: orps %xmm2, %xmm0
125 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
145126 ; CHECK-NEXT: retq
146127 %1 = fcmp ueq <4 x float> ,
147128 %2 = sext <4 x i1> %1 to <4 x i32>