llvm.org GIT mirror llvm / 4ccc33a
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280778 91177308-0d34-0410-b5e6-96231b3b80d8 Saleem Abdulrasool 3 years ago
6 changed file(s) with 293 addition(s) and 297 deletion(s). Raw diff Collapse all Expand all
487487 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize";
488488 }
489489
490 /// Set default libcall CallingConvs.
491 static void InitLibcallCallingConvs(CallingConv::ID *CCs, const Triple &T) {
492 bool IsARM = T.getArch() == Triple::arm || T.getArch() == Triple::thumb;
493 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
494 CCs[LC] = IsARM ? CallingConv::ARM_AAPCS : CallingConv::C;
490 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
491 ///
492 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
493 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
494 CCs[i] = CallingConv::C;
495 }
495496 }
496497
497498 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
833834
834835 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple());
835836 InitCmpLibcallCCs(CmpLibcallCCs);
836 InitLibcallCallingConvs(LibcallCallingConvs, TM.getTargetTriple());
837 InitLibcallCallingConvs(LibcallCallingConvs);
837838 }
838839
839840 void TargetLoweringBase::initActions() {
33
44 ; CHECK-LABEL: test1
55 ; CHECK: vrintm.f32
6 define arm_aapcs_vfpcc float @test1(float %a) {
6 define float @test1(float %a) {
77 entry:
8 %call = call arm_aapcs_vfpcc float @floorf(float %a) nounwind readnone
8 %call = call float @floorf(float %a) nounwind readnone
99 ret float %call
1010 }
1111
1212 ; CHECK-LABEL: test2
13 ; SP: bl floor
13 ; SP: b floor
1414 ; DP: vrintm.f64
15 define arm_aapcs_vfpcc double @test2(double %a) {
15 define double @test2(double %a) {
1616 entry:
17 %call = call arm_aapcscc double @floor(double %a) nounwind readnone
17 %call = call double @floor(double %a) nounwind readnone
1818 ret double %call
1919 }
2020
2121 ; CHECK-LABEL: test3
2222 ; CHECK: vrintp.f32
23 define arm_aapcs_vfpcc float @test3(float %a) {
23 define float @test3(float %a) {
2424 entry:
25 %call = call arm_aapcs_vfpcc float @ceilf(float %a) nounwind readnone
25 %call = call float @ceilf(float %a) nounwind readnone
2626 ret float %call
2727 }
2828
2929 ; CHECK-LABEL: test4
30 ; SP: bl ceil
30 ; SP: b ceil
3131 ; DP: vrintp.f64
32 define arm_aapcs_vfpcc double @test4(double %a) {
32 define double @test4(double %a) {
3333 entry:
34 %call = call arm_aapcscc double @ceil(double %a) nounwind readnone
34 %call = call double @ceil(double %a) nounwind readnone
3535 ret double %call
3636 }
3737
3838 ; CHECK-LABEL: test5
3939 ; CHECK: vrinta.f32
40 define arm_aapcs_vfpcc float @test5(float %a) {
40 define float @test5(float %a) {
4141 entry:
42 %call = call arm_aapcs_vfpcc float @roundf(float %a) nounwind readnone
42 %call = call float @roundf(float %a) nounwind readnone
4343 ret float %call
4444 }
4545
4646 ; CHECK-LABEL: test6
47 ; SP: bl round
47 ; SP: b round
4848 ; DP: vrinta.f64
49 define arm_aapcs_vfpcc double @test6(double %a) {
49 define double @test6(double %a) {
5050 entry:
51 %call = call arm_aapcscc double @round(double %a) nounwind readnone
51 %call = call double @round(double %a) nounwind readnone
5252 ret double %call
5353 }
5454
5555 ; CHECK-LABEL: test7
5656 ; CHECK: vrintz.f32
57 define arm_aapcs_vfpcc float @test7(float %a) {
57 define float @test7(float %a) {
5858 entry:
59 %call = call arm_aapcs_vfpcc float @truncf(float %a) nounwind readnone
59 %call = call float @truncf(float %a) nounwind readnone
6060 ret float %call
6161 }
6262
6363 ; CHECK-LABEL: test8
64 ; SP: bl trunc
64 ; SP: b trunc
6565 ; DP: vrintz.f64
66 define arm_aapcs_vfpcc double @test8(double %a) {
66 define double @test8(double %a) {
6767 entry:
68 %call = call arm_aapcscc double @trunc(double %a) nounwind readnone
68 %call = call double @trunc(double %a) nounwind readnone
6969 ret double %call
7070 }
7171
7272 ; CHECK-LABEL: test9
7373 ; CHECK: vrintr.f32
74 define arm_aapcs_vfpcc float @test9(float %a) {
74 define float @test9(float %a) {
7575 entry:
76 %call = call arm_aapcs_vfpcc float @nearbyintf(float %a) nounwind readnone
76 %call = call float @nearbyintf(float %a) nounwind readnone
7777 ret float %call
7878 }
7979
8080 ; CHECK-LABEL: test10
81 ; SP: bl nearbyint
81 ; SP: b nearbyint
8282 ; DP: vrintr.f64
83 define arm_aapcs_vfpcc double @test10(double %a) {
83 define double @test10(double %a) {
8484 entry:
85 %call = call arm_aapcscc double @nearbyint(double %a) nounwind readnone
85 %call = call double @nearbyint(double %a) nounwind readnone
8686 ret double %call
8787 }
8888
8989 ; CHECK-LABEL: test11
9090 ; CHECK: vrintx.f32
91 define arm_aapcs_vfpcc float @test11(float %a) {
91 define float @test11(float %a) {
9292 entry:
93 %call = call arm_aapcs_vfpcc float @rintf(float %a) nounwind readnone
93 %call = call float @rintf(float %a) nounwind readnone
9494 ret float %call
9595 }
9696
9797 ; CHECK-LABEL: test12
98 ; SP: bl rint
98 ; SP: b rint
9999 ; DP: vrintx.f64
100 define arm_aapcs_vfpcc double @test12(double %a) {
100 define double @test12(double %a) {
101101 entry:
102 %call = call arm_aapcscc double @rint(double %a) nounwind readnone
102 %call = call double @rint(double %a) nounwind readnone
103103 ret double %call
104104 }
105105
106 declare arm_aapcs_vfpcc float @floorf(float) nounwind readnone
107 declare arm_aapcscc double @floor(double) nounwind readnone
108 declare arm_aapcs_vfpcc float @ceilf(float) nounwind readnone
109 declare arm_aapcscc double @ceil(double) nounwind readnone
110 declare arm_aapcs_vfpcc float @roundf(float) nounwind readnone
111 declare arm_aapcscc double @round(double) nounwind readnone
112 declare arm_aapcs_vfpcc float @truncf(float) nounwind readnone
113 declare arm_aapcscc double @trunc(double) nounwind readnone
114 declare arm_aapcs_vfpcc float @nearbyintf(float) nounwind readnone
115 declare arm_aapcscc double @nearbyint(double) nounwind readnone
116 declare arm_aapcs_vfpcc float @rintf(float) nounwind readnone
117 declare arm_aapcscc double @rint(double) nounwind readnone
118
106 declare float @floorf(float) nounwind readnone
107 declare double @floor(double) nounwind readnone
108 declare float @ceilf(float) nounwind readnone
109 declare double @ceil(double) nounwind readnone
110 declare float @roundf(float) nounwind readnone
111 declare double @round(double) nounwind readnone
112 declare float @truncf(float) nounwind readnone
113 declare double @trunc(double) nounwind readnone
114 declare float @nearbyintf(float) nounwind readnone
115 declare double @nearbyint(double) nounwind readnone
116 declare float @rintf(float) nounwind readnone
117 declare double @rint(double) nounwind readnone
0 ; RUN: llc -mtriple=thumbv7-linux-gnueabihf %s -o - | FileCheck %s
11
2 define arm_aapcs_vfpcc i64 @test_mismatched_call(double %in) {
2 define i64 @test_mismatched_call(double %in) {
33 ; CHECK-LABEL: test_mismatched_call:
4 ; CHECK: bl floor
45 ; CHECK: vmov r0, r1, d0
5 ; CHECK: bl floor
66
7 %val = tail call arm_aapcscc double @floor(double %in)
7 %val = tail call double @floor(double %in)
88 %res = bitcast double %val to i64
99 ret i64 %res
1010 }
1111
12 define arm_aapcs_vfpcc double @test_matched_call(double %in) {
12 define double @test_matched_call(double %in) {
1313 ; CHECK-LABEL: test_matched_call:
14 ; CHECK: b _floor
14 ; CHECK: b floor
1515
16 %val = tail call arm_aapcs_vfpcc double @_floor(double %in)
16 %val = tail call double @floor(double %in)
1717 ret double %val
1818 }
1919
20 define arm_aapcs_vfpcc void @test_irrelevant_call(double %in) {
20 define void @test_irrelevant_call(double %in) {
2121 ; CHECK-LABEL: test_irrelevant_call:
2222 ; CHECK-NOT: bl floor
2323
24 %val = tail call arm_aapcscc double @floor(double %in)
24 %val = tail call double @floor(double %in)
2525 ret void
2626 }
2727
28 define arm_aapcs_vfpcc double @test_callingconv(double %in) {
28 define arm_aapcscc double @test_callingconv(double %in) {
2929 ; CHECK: test_callingconv:
3030 ; CHECK: bl floor
3131
32 %val = tail call arm_aapcscc double @floor(double %in)
32 %val = tail call double @floor(double %in)
3333 ret double %val
3434 }
3535
36 declare arm_aapcs_vfpcc double @_floor(double) nounwind readonly
37 declare arm_aapcscc double @floor(double) nounwind readonly
36 declare double @floor(double) nounwind readonly
44 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4
55 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv8
66
7 declare arm_aapcscc double @llvm.sqrt.f64(double %Val)
7 declare double @llvm.sqrt.f64(double %Val)
88 define double @sqrt_d(double %a) {
99 ; CHECK-LABEL: sqrt_d:
1010 ; SOFT: {{(bl|b)}} sqrt
1111 ; HARD: vsqrt.f64 d0, d0
12 %1 = call arm_aapcscc double @llvm.sqrt.f64(double %a)
13 ret double %1
14 }
15
16 declare arm_aapcscc double @llvm.powi.f64(double %Val, i32 %power)
12 %1 = call double @llvm.sqrt.f64(double %a)
13 ret double %1
14 }
15
16 declare double @llvm.powi.f64(double %Val, i32 %power)
1717 define double @powi_d(double %a, i32 %b) {
1818 ; CHECK-LABEL: powi_d:
1919 ; SOFT: {{(bl|b)}} __powidf2
20 ; HARD: bl __powidf2
21 %1 = call arm_aapcscc double @llvm.powi.f64(double %a, i32 %b)
22 ret double %1
23 }
24
25 declare arm_aapcscc double @llvm.sin.f64(double %Val)
20 ; HARD: b __powidf2
21 %1 = call double @llvm.powi.f64(double %a, i32 %b)
22 ret double %1
23 }
24
25 declare double @llvm.sin.f64(double %Val)
2626 define double @sin_d(double %a) {
2727 ; CHECK-LABEL: sin_d:
2828 ; SOFT: {{(bl|b)}} sin
29 ; HARD: bl sin
30 %1 = call arm_aapcscc double @llvm.sin.f64(double %a)
31 ret double %1
32 }
33
34 declare arm_aapcscc double @llvm.cos.f64(double %Val)
29 ; HARD: b sin
30 %1 = call double @llvm.sin.f64(double %a)
31 ret double %1
32 }
33
34 declare double @llvm.cos.f64(double %Val)
3535 define double @cos_d(double %a) {
3636 ; CHECK-LABEL: cos_d:
3737 ; SOFT: {{(bl|b)}} cos
38 ; HARD: bl cos
39 %1 = call arm_aapcscc double @llvm.cos.f64(double %a)
40 ret double %1
41 }
42
43 declare arm_aapcscc double @llvm.pow.f64(double %Val, double %power)
38 ; HARD: b cos
39 %1 = call double @llvm.cos.f64(double %a)
40 ret double %1
41 }
42
43 declare double @llvm.pow.f64(double %Val, double %power)
4444 define double @pow_d(double %a, double %b) {
4545 ; CHECK-LABEL: pow_d:
4646 ; SOFT: {{(bl|b)}} pow
47 ; HARD: bl pow
48 %1 = call arm_aapcscc double @llvm.pow.f64(double %a, double %b)
49 ret double %1
50 }
51
52 declare arm_aapcscc double @llvm.exp.f64(double %Val)
47 ; HARD: b pow
48 %1 = call double @llvm.pow.f64(double %a, double %b)
49 ret double %1
50 }
51
52 declare double @llvm.exp.f64(double %Val)
5353 define double @exp_d(double %a) {
5454 ; CHECK-LABEL: exp_d:
5555 ; SOFT: {{(bl|b)}} exp
56 ; HARD: bl exp
57 %1 = call arm_aapcscc double @llvm.exp.f64(double %a)
58 ret double %1
59 }
60
61 declare arm_aapcscc double @llvm.exp2.f64(double %Val)
56 ; HARD: b exp
57 %1 = call double @llvm.exp.f64(double %a)
58 ret double %1
59 }
60
61 declare double @llvm.exp2.f64(double %Val)
6262 define double @exp2_d(double %a) {
6363 ; CHECK-LABEL: exp2_d:
6464 ; SOFT: {{(bl|b)}} exp2
65 ; HARD: bl exp2
66 %1 = call arm_aapcscc double @llvm.exp2.f64(double %a)
67 ret double %1
68 }
69
70 declare arm_aapcscc double @llvm.log.f64(double %Val)
65 ; HARD: b exp2
66 %1 = call double @llvm.exp2.f64(double %a)
67 ret double %1
68 }
69
70 declare double @llvm.log.f64(double %Val)
7171 define double @log_d(double %a) {
7272 ; CHECK-LABEL: log_d:
7373 ; SOFT: {{(bl|b)}} log
74 ; HARD: bl log
75 %1 = call arm_aapcscc double @llvm.log.f64(double %a)
76 ret double %1
77 }
78
79 declare arm_aapcscc double @llvm.log10.f64(double %Val)
74 ; HARD: b log
75 %1 = call double @llvm.log.f64(double %a)
76 ret double %1
77 }
78
79 declare double @llvm.log10.f64(double %Val)
8080 define double @log10_d(double %a) {
8181 ; CHECK-LABEL: log10_d:
8282 ; SOFT: {{(bl|b)}} log10
83 ; HARD: bl log10
84 %1 = call arm_aapcscc double @llvm.log10.f64(double %a)
85 ret double %1
86 }
87
88 declare arm_aapcscc double @llvm.log2.f64(double %Val)
83 ; HARD: b log10
84 %1 = call double @llvm.log10.f64(double %a)
85 ret double %1
86 }
87
88 declare double @llvm.log2.f64(double %Val)
8989 define double @log2_d(double %a) {
9090 ; CHECK-LABEL: log2_d:
9191 ; SOFT: {{(bl|b)}} log2
92 ; HARD: bl log2
93 %1 = call arm_aapcscc double @llvm.log2.f64(double %a)
94 ret double %1
95 }
96
97 declare arm_aapcscc double @llvm.fma.f64(double %a, double %b, double %c)
92 ; HARD: b log2
93 %1 = call double @llvm.log2.f64(double %a)
94 ret double %1
95 }
96
97 declare double @llvm.fma.f64(double %a, double %b, double %c)
9898 define double @fma_d(double %a, double %b, double %c) {
9999 ; CHECK-LABEL: fma_d:
100100 ; SOFT: {{(bl|b)}} fma
101101 ; HARD: vfma.f64
102 %1 = call arm_aapcscc double @llvm.fma.f64(double %a, double %b, double %c)
102 %1 = call double @llvm.fma.f64(double %a, double %b, double %c)
103103 ret double %1
104104 }
105105
106106 ; FIXME: the FPv4-SP version is less efficient than the no-FPU version
107 declare arm_aapcscc double @llvm.fabs.f64(double %Val)
107 declare double @llvm.fabs.f64(double %Val)
108108 define double @abs_d(double %a) {
109109 ; CHECK-LABEL: abs_d:
110110 ; NONE: bic r1, r1, #-2147483648
115115 ; SP: bfi r1, r2, #31, #1
116116 ; SP: vmov d0, r0, r1
117117 ; DP: vabs.f64 d0, d0
118 %1 = call arm_aapcscc double @llvm.fabs.f64(double %a)
119 ret double %1
120 }
121
122 declare arm_aapcscc double @llvm.copysign.f64(double %Mag, double %Sgn)
118 %1 = call double @llvm.fabs.f64(double %a)
119 ret double %1
120 }
121
122 declare double @llvm.copysign.f64(double %Mag, double %Sgn)
123123 define double @copysign_d(double %a, double %b) {
124124 ; CHECK-LABEL: copysign_d:
125125 ; SOFT: lsrs [[REG:r[0-9]+]], r3, #31
129129 ; NEON: vmov.i32 [[REG:d[0-9]+]], #0x80000000
130130 ; NEON: vshl.i64 [[REG]], [[REG]], #32
131131 ; NEON: vbsl [[REG]], d
132 %1 = call arm_aapcscc double @llvm.copysign.f64(double %a, double %b)
133 ret double %1
134 }
135
136 declare arm_aapcscc double @llvm.floor.f64(double %Val)
132 %1 = call double @llvm.copysign.f64(double %a, double %b)
133 ret double %1
134 }
135
136 declare double @llvm.floor.f64(double %Val)
137137 define double @floor_d(double %a) {
138138 ; CHECK-LABEL: floor_d:
139139 ; SOFT: {{(bl|b)}} floor
140 ; VFP4: bl floor
140 ; VFP4: b floor
141141 ; FP-ARMv8: vrintm.f64
142 %1 = call arm_aapcscc double @llvm.floor.f64(double %a)
143 ret double %1
144 }
145
146 declare arm_aapcscc double @llvm.ceil.f64(double %Val)
142 %1 = call double @llvm.floor.f64(double %a)
143 ret double %1
144 }
145
146 declare double @llvm.ceil.f64(double %Val)
147147 define double @ceil_d(double %a) {
148148 ; CHECK-LABEL: ceil_d:
149149 ; SOFT: {{(bl|b)}} ceil
150 ; VFP4: bl ceil
150 ; VFP4: b ceil
151151 ; FP-ARMv8: vrintp.f64
152 %1 = call arm_aapcscc double @llvm.ceil.f64(double %a)
153 ret double %1
154 }
155
156 declare arm_aapcscc double @llvm.trunc.f64(double %Val)
152 %1 = call double @llvm.ceil.f64(double %a)
153 ret double %1
154 }
155
156 declare double @llvm.trunc.f64(double %Val)
157157 define double @trunc_d(double %a) {
158158 ; CHECK-LABEL: trunc_d:
159159 ; SOFT: {{(bl|b)}} trunc
160 ; FFP4: bl trunc
160 ; FFP4: b trunc
161161 ; FP-ARMv8: vrintz.f64
162 %1 = call arm_aapcscc double @llvm.trunc.f64(double %a)
163 ret double %1
164 }
165
166 declare arm_aapcscc double @llvm.rint.f64(double %Val)
162 %1 = call double @llvm.trunc.f64(double %a)
163 ret double %1
164 }
165
166 declare double @llvm.rint.f64(double %Val)
167167 define double @rint_d(double %a) {
168168 ; CHECK-LABEL: rint_d:
169169 ; SOFT: {{(bl|b)}} rint
170 ; VFP4: bl rint
170 ; VFP4: b rint
171171 ; FP-ARMv8: vrintx.f64
172 %1 = call arm_aapcscc double @llvm.rint.f64(double %a)
173 ret double %1
174 }
175
176 declare arm_aapcscc double @llvm.nearbyint.f64(double %Val)
172 %1 = call double @llvm.rint.f64(double %a)
173 ret double %1
174 }
175
176 declare double @llvm.nearbyint.f64(double %Val)
177177 define double @nearbyint_d(double %a) {
178178 ; CHECK-LABEL: nearbyint_d:
179179 ; SOFT: {{(bl|b)}} nearbyint
180 ; VFP4: bl nearbyint
180 ; VFP4: b nearbyint
181181 ; FP-ARMv8: vrintr.f64
182 %1 = call arm_aapcscc double @llvm.nearbyint.f64(double %a)
183 ret double %1
184 }
185
186 declare arm_aapcscc double @llvm.round.f64(double %Val)
182 %1 = call double @llvm.nearbyint.f64(double %a)
183 ret double %1
184 }
185
186 declare double @llvm.round.f64(double %Val)
187187 define double @round_d(double %a) {
188188 ; CHECK-LABEL: round_d:
189189 ; SOFT: {{(bl|b)}} round
190 ; VFP4: bl round
190 ; VFP4: b round
191191 ; FP-ARMv8: vrinta.f64
192 %1 = call arm_aapcscc double @llvm.round.f64(double %a)
193 ret double %1
194 }
195
196 declare arm_aapcscc double @llvm.fmuladd.f64(double %a, double %b, double %c)
192 %1 = call double @llvm.round.f64(double %a)
193 ret double %1
194 }
195
196 declare double @llvm.fmuladd.f64(double %a, double %b, double %c)
197197 define double @fmuladd_d(double %a, double %b, double %c) {
198198 ; CHECK-LABEL: fmuladd_d:
199199 ; SOFT: bl __aeabi_dmul
201201 ; VFP4: vmul.f64
202202 ; VFP4: vadd.f64
203203 ; FP-ARMv8: vmla.f64
204 %1 = call arm_aapcscc double @llvm.fmuladd.f64(double %a, double %b, double %c)
205 ret double %1
206 }
207
208 declare arm_aapcscc i16 @llvm.convert.to.fp16.f64(double %a)
204 %1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
205 ret double %1
206 }
207
208 declare i16 @llvm.convert.to.fp16.f64(double %a)
209209 define i16 @d_to_h(double %a) {
210210 ; CHECK-LABEL: d_to_h:
211211 ; SOFT: bl __aeabi_d2h
212212 ; VFP4: bl __aeabi_d2h
213213 ; FP-ARMv8: vcvt{{[bt]}}.f16.f64
214 %1 = call arm_aapcscc i16 @llvm.convert.to.fp16.f64(double %a)
214 %1 = call i16 @llvm.convert.to.fp16.f64(double %a)
215215 ret i16 %1
216216 }
217217
218 declare arm_aapcscc double @llvm.convert.from.fp16.f64(i16 %a)
218 declare double @llvm.convert.from.fp16.f64(i16 %a)
219219 define double @h_to_d(i16 %a) {
220220 ; CHECK-LABEL: h_to_d:
221221 ; NONE: bl __aeabi_h2f
225225 ; VFPv4: vcvt{{[bt]}}.f32.f16
226226 ; VFPv4: vcvt.f64.f32
227227 ; FP-ARMv8: vcvt{{[bt]}}.f64.f16
228 %1 = call arm_aapcscc double @llvm.convert.from.fp16.f64(i16 %a)
229 ret double %1
230 }
231
228 %1 = call double @llvm.convert.from.fp16.f64(i16 %a)
229 ret double %1
230 }
1313 ret float %1
1414 }
1515
16 declare arm_aapcscc float @llvm.powi.f32(float %Val, i32 %power)
16 declare float @llvm.powi.f32(float %Val, i32 %power)
1717 define float @powi_f(float %a, i32 %b) {
1818 ; CHECK-LABEL: powi_f:
1919 ; SOFT: bl __powisf2
20 ; HARD: bl __powisf2
21 %1 = call arm_aapcscc float @llvm.powi.f32(float %a, i32 %b)
22 ret float %1
23 }
24
25 declare arm_aapcscc float @llvm.sin.f32(float %Val)
20 ; HARD: b __powisf2
21 %1 = call float @llvm.powi.f32(float %a, i32 %b)
22 ret float %1
23 }
24
25 declare float @llvm.sin.f32(float %Val)
2626 define float @sin_f(float %a) {
2727 ; CHECK-LABEL: sin_f:
2828 ; SOFT: bl sinf
29 ; HARD: bl sinf
30 %1 = call arm_aapcscc float @llvm.sin.f32(float %a)
31 ret float %1
32 }
33
34 declare arm_aapcscc float @llvm.cos.f32(float %Val)
29 ; HARD: b sinf
30 %1 = call float @llvm.sin.f32(float %a)
31 ret float %1
32 }
33
34 declare float @llvm.cos.f32(float %Val)
3535 define float @cos_f(float %a) {
3636 ; CHECK-LABEL: cos_f:
3737 ; SOFT: bl cosf
38 ; HARD: bl cosf
39 %1 = call arm_aapcscc float @llvm.cos.f32(float %a)
40 ret float %1
41 }
42
43 declare arm_aapcscc float @llvm.pow.f32(float %Val, float %power)
38 ; HARD: b cosf
39 %1 = call float @llvm.cos.f32(float %a)
40 ret float %1
41 }
42
43 declare float @llvm.pow.f32(float %Val, float %power)
4444 define float @pow_f(float %a, float %b) {
4545 ; CHECK-LABEL: pow_f:
4646 ; SOFT: bl powf
47 ; HARD: bl powf
48 %1 = call arm_aapcscc float @llvm.pow.f32(float %a, float %b)
49 ret float %1
50 }
51
52 declare arm_aapcscc float @llvm.exp.f32(float %Val)
47 ; HARD: b powf
48 %1 = call float @llvm.pow.f32(float %a, float %b)
49 ret float %1
50 }
51
52 declare float @llvm.exp.f32(float %Val)
5353 define float @exp_f(float %a) {
5454 ; CHECK-LABEL: exp_f:
5555 ; SOFT: bl expf
56 ; HARD: bl expf
57 %1 = call arm_aapcscc float @llvm.exp.f32(float %a)
58 ret float %1
59 }
60
61 declare arm_aapcscc float @llvm.exp2.f32(float %Val)
56 ; HARD: b expf
57 %1 = call float @llvm.exp.f32(float %a)
58 ret float %1
59 }
60
61 declare float @llvm.exp2.f32(float %Val)
6262 define float @exp2_f(float %a) {
6363 ; CHECK-LABEL: exp2_f:
6464 ; SOFT: bl exp2f
65 ; HARD: bl exp2f
66 %1 = call arm_aapcscc float @llvm.exp2.f32(float %a)
67 ret float %1
68 }
69
70 declare arm_aapcscc float @llvm.log.f32(float %Val)
65 ; HARD: b exp2f
66 %1 = call float @llvm.exp2.f32(float %a)
67 ret float %1
68 }
69
70 declare float @llvm.log.f32(float %Val)
7171 define float @log_f(float %a) {
7272 ; CHECK-LABEL: log_f:
7373 ; SOFT: bl logf
74 ; HARD: bl logf
75 %1 = call arm_aapcscc float @llvm.log.f32(float %a)
76 ret float %1
77 }
78
79 declare arm_aapcscc float @llvm.log10.f32(float %Val)
74 ; HARD: b logf
75 %1 = call float @llvm.log.f32(float %a)
76 ret float %1
77 }
78
79 declare float @llvm.log10.f32(float %Val)
8080 define float @log10_f(float %a) {
8181 ; CHECK-LABEL: log10_f:
8282 ; SOFT: bl log10f
83 ; HARD: bl log10f
84 %1 = call arm_aapcscc float @llvm.log10.f32(float %a)
85 ret float %1
86 }
87
88 declare arm_aapcscc float @llvm.log2.f32(float %Val)
83 ; HARD: b log10f
84 %1 = call float @llvm.log10.f32(float %a)
85 ret float %1
86 }
87
88 declare float @llvm.log2.f32(float %Val)
8989 define float @log2_f(float %a) {
9090 ; CHECK-LABEL: log2_f:
9191 ; SOFT: bl log2f
92 ; HARD: bl log2f
93 %1 = call arm_aapcscc float @llvm.log2.f32(float %a)
94 ret float %1
95 }
96
97 declare arm_aapcscc float @llvm.fma.f32(float %a, float %b, float %c)
92 ; HARD: b log2f
93 %1 = call float @llvm.log2.f32(float %a)
94 ret float %1
95 }
96
97 declare float @llvm.fma.f32(float %a, float %b, float %c)
9898 define float @fma_f(float %a, float %b, float %c) {
9999 ; CHECK-LABEL: fma_f:
100100 ; SOFT: bl fmaf
101101 ; HARD: vfma.f32
102 %1 = call arm_aapcscc float @llvm.fma.f32(float %a, float %b, float %c)
103 ret float %1
104 }
105
106 declare arm_aapcscc float @llvm.fabs.f32(float %Val)
102 %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
103 ret float %1
104 }
105
106 declare float @llvm.fabs.f32(float %Val)
107107 define float @abs_f(float %a) {
108108 ; CHECK-LABEL: abs_f:
109109 ; SOFT: bic r0, r0, #-2147483648
110110 ; HARD: vabs.f32
111 %1 = call arm_aapcscc float @llvm.fabs.f32(float %a)
112 ret float %1
113 }
114
115 declare arm_aapcscc float @llvm.copysign.f32(float %Mag, float %Sgn)
111 %1 = call float @llvm.fabs.f32(float %a)
112 ret float %1
113 }
114
115 declare float @llvm.copysign.f32(float %Mag, float %Sgn)
116116 define float @copysign_f(float %a, float %b) {
117117 ; CHECK-LABEL: copysign_f:
118118 ; NONE: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
123123 ; VFP: bfi r{{[0-9]+}}, [[REG]], #31, #1
124124 ; NEON: vmov.i32 [[REG:d[0-9]+]], #0x80000000
125125 ; NEON: vbsl [[REG]], d
126 %1 = call arm_aapcscc float @llvm.copysign.f32(float %a, float %b)
127 ret float %1
128 }
129
130 declare arm_aapcscc float @llvm.floor.f32(float %Val)
126 %1 = call float @llvm.copysign.f32(float %a, float %b)
127 ret float %1
128 }
129
130 declare float @llvm.floor.f32(float %Val)
131131 define float @floor_f(float %a) {
132132 ; CHECK-LABEL: floor_f:
133133 ; SOFT: bl floorf
134 ; VFP4: bl floorf
134 ; VFP4: b floorf
135135 ; FP-ARMv8: vrintm.f32
136 %1 = call arm_aapcscc float @llvm.floor.f32(float %a)
137 ret float %1
138 }
139
140 declare arm_aapcscc float @llvm.ceil.f32(float %Val)
136 %1 = call float @llvm.floor.f32(float %a)
137 ret float %1
138 }
139
140 declare float @llvm.ceil.f32(float %Val)
141141 define float @ceil_f(float %a) {
142142 ; CHECK-LABEL: ceil_f:
143143 ; SOFT: bl ceilf
144 ; VFP4: bl ceilf
144 ; VFP4: b ceilf
145145 ; FP-ARMv8: vrintp.f32
146 %1 = call arm_aapcscc float @llvm.ceil.f32(float %a)
147 ret float %1
148 }
149
150 declare arm_aapcscc float @llvm.trunc.f32(float %Val)
146 %1 = call float @llvm.ceil.f32(float %a)
147 ret float %1
148 }
149
150 declare float @llvm.trunc.f32(float %Val)
151151 define float @trunc_f(float %a) {
152152 ; CHECK-LABEL: trunc_f:
153153 ; SOFT: bl truncf
154 ; VFP4: bl truncf
154 ; VFP4: b truncf
155155 ; FP-ARMv8: vrintz.f32
156 %1 = call arm_aapcscc float @llvm.trunc.f32(float %a)
157 ret float %1
158 }
159
160 declare arm_aapcscc float @llvm.rint.f32(float %Val)
156 %1 = call float @llvm.trunc.f32(float %a)
157 ret float %1
158 }
159
160 declare float @llvm.rint.f32(float %Val)
161161 define float @rint_f(float %a) {
162162 ; CHECK-LABEL: rint_f:
163163 ; SOFT: bl rintf
164 ; VFP4: bl rintf
164 ; VFP4: b rintf
165165 ; FP-ARMv8: vrintx.f32
166 %1 = call arm_aapcscc float @llvm.rint.f32(float %a)
167 ret float %1
168 }
169
170 declare arm_aapcscc float @llvm.nearbyint.f32(float %Val)
166 %1 = call float @llvm.rint.f32(float %a)
167 ret float %1
168 }
169
170 declare float @llvm.nearbyint.f32(float %Val)
171171 define float @nearbyint_f(float %a) {
172172 ; CHECK-LABEL: nearbyint_f:
173173 ; SOFT: bl nearbyintf
174 ; VFP4: bl nearbyintf
174 ; VFP4: b nearbyintf
175175 ; FP-ARMv8: vrintr.f32
176 %1 = call arm_aapcscc float @llvm.nearbyint.f32(float %a)
177 ret float %1
178 }
179
180 declare arm_aapcscc float @llvm.round.f32(float %Val)
176 %1 = call float @llvm.nearbyint.f32(float %a)
177 ret float %1
178 }
179
180 declare float @llvm.round.f32(float %Val)
181181 define float @round_f(float %a) {
182182 ; CHECK-LABEL: round_f:
183183 ; SOFT: bl roundf
184 ; VFP4: bl roundf
184 ; VFP4: b roundf
185185 ; FP-ARMv8: vrinta.f32
186 %1 = call arm_aapcscc float @llvm.round.f32(float %a)
186 %1 = call float @llvm.round.f32(float %a)
187187 ret float %1
188188 }
189189
190190 ; FIXME: why does cortex-m4 use vmla, while cortex-a7 uses vmul+vadd?
191191 ; (these should be equivalent, even the rounding is the same)
192 declare arm_aapcscc float @llvm.fmuladd.f32(float %a, float %b, float %c)
192 declare float @llvm.fmuladd.f32(float %a, float %b, float %c)
193193 define float @fmuladd_f(float %a, float %b, float %c) {
194194 ; CHECK-LABEL: fmuladd_f:
195195 ; SOFT: bl __aeabi_fmul
197197 ; VMLA: vmla.f32
198198 ; NO-VMLA: vmul.f32
199199 ; NO-VMLA: vadd.f32
200 %1 = call arm_aapcscc float @llvm.fmuladd.f32(float %a, float %b, float %c)
201 ret float %1
202 }
203
204 declare arm_aapcscc i16 @llvm.convert.to.fp16.f32(float %a)
200 %1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
201 ret float %1
202 }
203
204 declare i16 @llvm.convert.to.fp16.f32(float %a)
205205 define i16 @f_to_h(float %a) {
206206 ; CHECK-LABEL: f_to_h:
207207 ; SOFT: bl __aeabi_f2h
208208 ; HARD: vcvt{{[bt]}}.f16.f32
209 %1 = call arm_aapcscc i16 @llvm.convert.to.fp16.f32(float %a)
209 %1 = call i16 @llvm.convert.to.fp16.f32(float %a)
210210 ret i16 %1
211211 }
212212
213 declare arm_aapcscc float @llvm.convert.from.fp16.f32(i16 %a)
213 declare float @llvm.convert.from.fp16.f32(i16 %a)
214214 define float @h_to_f(i16 %a) {
215215 ; CHECK-LABEL: h_to_f:
216216 ; SOFT: bl __aeabi_h2f
217217 ; HARD: vcvt{{[bt]}}.f32.f16
218 %1 = call arm_aapcscc float @llvm.convert.from.fp16.f32(i16 %a)
219 ret float %1
220 }
221
218 %1 = call float @llvm.convert.from.fp16.f32(i16 %a)
219 ret float %1
220 }
33 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP4-ALL -check-prefix=VFP4-DP
44
55 define float @add_f(float %a, float %b) {
6
76 entry:
87 ; CHECK-LABEL: add_f:
98 ; NONE: bl __aeabi_fadd
8382 entry:
8483 ; CHECK-LABEL: rem_f:
8584 ; NONE: bl fmodf
86 ; HARD: bl fmodf
85 ; HARD: b fmodf
8786 %0 = frem float %a, %b
8887 ret float %0
8988 }
9291 entry:
9392 ; CHECK-LABEL: rem_d:
9493 ; NONE: bl fmod
95 ; HARD: bl fmod
94 ; HARD: b fmod
9695 %0 = frem double %a, %b
9796 ret double %0
9897 }