llvm.org GIT mirror llvm / 4cbbbf4
This reverts r155000. The cdp2 instruction should have the same restrictions as cdp on the co-processor registers. VFP instructions on v8/AArch32 share the same encoding space as cdp2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184445 91177308-0d34-0410-b5e6-96231b3b80d8 Joey Gouly 7 years ago
4 changed file(s) with 7 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
10041004 let PrintMethod = "printPImmediate";
10051005 let ParserMatchClass = CoprocNumAsmOperand;
10061006 let DecoderMethod = "DecodeCoprocessor";
1007 }
1008
1009 def pf_imm : Operand {
1010 let PrintMethod = "printPImmediate";
1011 let ParserMatchClass = CoprocNumAsmOperand;
10121007 }
10131008
10141009 def CoprocRegAsmOperand : AsmOperandClass {
44464441 let Inst{23-20} = opc1;
44474442 }
44484443
4449 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4444 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
44504445 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
44514446 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
44524447 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
458458 @------------------------------------------------------------------------------
459459 cdp p7, #1, c1, c1, c1, #4
460460 cdp2 p7, #1, c1, c1, c1, #4
461 cdp2 p10, #0, c6, c12, c0, #7
461462
462463 @ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
463464 @ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
465 @ CHECK: cdp2 p10, #0, c6, c12, c0, #7 @ encoding: [0xe0,0x6a,0x0c,0xfe]
464466
465467
466468 @------------------------------------------------------------------------------
361361
362362 # CHECK: ldmgt sp!, {r9}
363363 0x00 0x02 0xbd 0xc8
364
365 # CHECK: cdp2 p10, #0, c6, c12, c0, #7
366 0xe0 0x6a 0x0c 0xfe
367
0 # RUN: llvm-mc --disassemble %s -triple=arm 2>&1 | FileCheck %s
1
2 # CHECK: invalid instruction encoding
3 0xe0 0x6a 0x0c 0xfe