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[MIRPrinter] Use %subreg.xxx syntax for subregister index operands Summary: Print %subreg.<subregidxname> instead of just the subregister index when printing immediate operands corresponding to subreg indices in INSERT_SUBREG, EXTRACT_SUBREG, SUBREG_TO_REG and REG_SEQUENCE. Reviewers: qcolombet, MatzeB Reviewed By: MatzeB Subscribers: nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D39696 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317513 91177308-0d34-0410-b5e6-96231b3b80d8 Bjorn Pettersson 3 years ago
13 changed file(s) with 108 addition(s) and 88 deletion(s). Raw diff Collapse all Expand all
300300 return Operands[i];
301301 }
302302
303 /// Return true if operand \p OpIdx is a subregister index.
304 bool isOperandSubregIdx(unsigned OpIdx) const {
305 assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&
306 "Expected MO_Immediate operand type.");
307 if (isExtractSubreg() && OpIdx == 2)
308 return true;
309 if (isInsertSubreg() && OpIdx == 3)
310 return true;
311 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
312 return true;
313 if (isSubregToReg() && OpIdx == 3)
314 return true;
315 return false;
316 }
317
303318 /// Returns the number of non-implicit operands.
304319 unsigned getNumExplicitOperands() const;
305320
161161 void printStackObjectReference(int FrameIndex);
162162 void printOffset(int64_t Offset);
163163 void printTargetFlags(const MachineOperand &Op);
164 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
165 unsigned I, bool ShouldPrintRegisterTies,
164 void print(const MachineInstr &MI, unsigned OpIdx,
165 const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
166166 LLT TypeToPrint, bool IsDef = false);
167167 void print(const LLVMContext &Context, const TargetInstrInfo &TII,
168168 const MachineMemOperand &Op);
733733 ++I) {
734734 if (I)
735735 OS << ", ";
736 print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies,
736 print(MI, I, TRI, ShouldPrintRegisterTies,
737737 getTypeToPrint(MI, I, PrintedTypes, MRI),
738738 /*IsDef=*/true);
739739 }
750750 for (; I < E; ++I) {
751751 if (NeedComma)
752752 OS << ", ";
753 print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies,
753 print(MI, I, TRI, ShouldPrintRegisterTies,
754754 getTypeToPrint(MI, I, PrintedTypes, MRI));
755755 NeedComma = true;
756756 }
922922 return nullptr;
923923 }
924924
925 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
926 unsigned I, bool ShouldPrintRegisterTies, LLT TypeToPrint,
925 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
926 const TargetRegisterInfo *TRI,
927 bool ShouldPrintRegisterTies, LLT TypeToPrint,
927928 bool IsDef) {
929 const MachineOperand &Op = MI.getOperand(OpIdx);
928930 printTargetFlags(Op);
929931 switch (Op.getType()) {
930932 case MachineOperand::MO_Register: {
958960 }
959961 }
960962 if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
961 OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
963 OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(OpIdx) << ")";
962964 if (TypeToPrint.isValid())
963965 OS << '(' << TypeToPrint << ')';
964966 break;
965967 }
966968 case MachineOperand::MO_Immediate:
967 OS << Op.getImm();
969 if (MI.isOperandSubregIdx(OpIdx))
970 OS << "%subreg." << TRI->getSubRegIndexName(Op.getImm());
971 else
972 OS << Op.getImm();
968973 break;
969974 case MachineOperand::MO_CImmediate:
970975 Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
1414 %1:gpr(s64) = G_IMPLICIT_DEF
1515
1616 ; CHECK: body:
17 ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, 15
17 ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32
1818 ; CHECK: %2:gpr64 = BFMXri %1, [[TMP]], 0, 31
1919 %2:gpr(s64) = G_INSERT %1, %0, 0
2020
21 ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, 15
21 ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32
2222 ; CHECK: %3:gpr64 = BFMXri %1, [[TMP]], 51, 31
2323 %3:gpr(s64) = G_INSERT %1, %0, 13
2424
3232
3333 ; CHECK-LABEL: name: anyext_s64_from_s32
3434 ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
35 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], 15
35 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
3636 ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[SUBREG_TO_REG]]
3737 ; CHECK: %x0 = COPY [[COPY1]]
3838 %0(s32) = COPY %w0
7979
8080 ; CHECK-LABEL: name: zext_s64_from_s32
8181 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
82 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], 15
82 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
8383 ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
8484 ; CHECK: %x0 = COPY [[UBFMXri]]
8585 %0(s32) = COPY %w0
176176
177177 ; CHECK-LABEL: name: sext_s64_from_s32
178178 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
179 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], 15
179 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
180180 ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31
181181 ; CHECK: %x0 = COPY [[SBFMXri]]
182182 %0(s32) = COPY %w0
4343 # Max immediate for CI
4444 # SIVI: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967292
4545 # SIVI: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 3
46 # SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
46 # SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
4747 # SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0
4848 # SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0
4949 # SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
5050 # SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1
5151 # SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
5252 # SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
53 # SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
53 # SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
5454 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
5555 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 0
5656
5757 # Immediate overflow for CI
5858 # GCN: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 0
5959 # GCN: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 4
60 # GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
60 # GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
6161 # GCN-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0
6262 # GCN-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0
6363 # GCN: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
6464 # GCN-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1
6565 # GCN-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
6666 # GCN: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
67 # GCN: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
67 # GCN: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
6868 # GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
6969
7070 # Max 32-bit byte offset
7575 # Overflow 32-bit byte offset
7676 # SIVI: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 0
7777 # SIVI: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 1
78 # SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
78 # SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
7979 # SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0
8080 # SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0
8181 # SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
8282 # SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1
8383 # SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
8484 # SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
85 # SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
85 # SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
8686 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
8787 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 0
8888
55 # CHECK: S_NOP 0, implicit-def %0
66 # CHECK: S_NOP 0, implicit-def %1
77 # CHECK: S_NOP 0, implicit-def dead %2
8 # CHECK: %3:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
8 # CHECK: %3:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub3
99 # CHECK: S_NOP 0, implicit %3.sub0
1010 # CHECK: S_NOP 0, implicit %3.sub1
1111 # CHECK: S_NOP 0, implicit undef %3.sub2
4141 # Check defined lanes transfer; Includes checking for some special cases like
4242 # undef operands or IMPLICIT_DEF definitions.
4343 # CHECK-LABEL: name: test1
44 # CHECK: %0:sreg_128 = REG_SEQUENCE %sgpr0, {{[0-9]+}}, %sgpr0, {{[0-9]+}}
45 # CHECK: %1:sreg_128 = INSERT_SUBREG %0, %sgpr1, {{[0-9]+}}
46 # CHECK: %2:sreg_64 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, {{[0-9]+}}
44 # CHECK: %0:sreg_128 = REG_SEQUENCE %sgpr0, %subreg.sub0, %sgpr0, %subreg.sub2
45 # CHECK: %1:sreg_128 = INSERT_SUBREG %0, %sgpr1, %subreg.sub3
46 # CHECK: %2:sreg_64 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, %subreg.sub0
4747 # CHECK: S_NOP 0, implicit %1.sub0
4848 # CHECK: S_NOP 0, implicit undef %1.sub1
4949 # CHECK: S_NOP 0, implicit %1.sub2
5252 # CHECK: S_NOP 0, implicit undef %2.sub1
5353
5454 # CHECK: %3:sreg_32_xm0 = IMPLICIT_DEF
55 # CHECK: %4:sreg_128 = INSERT_SUBREG %0, undef %3, {{[0-9]+}}
55 # CHECK: %4:sreg_128 = INSERT_SUBREG %0, undef %3, %subreg.sub0
5656 # CHECK: S_NOP 0, implicit undef %4.sub0
5757 # CHECK: S_NOP 0, implicit undef %4.sub1
5858 # CHECK: S_NOP 0, implicit %4.sub2
5959 # CHECK: S_NOP 0, implicit undef %4.sub3
6060
61 # CHECK: %5:sreg_64 = EXTRACT_SUBREG %0, {{[0-9]+}}
62 # CHECK: %6:sreg_32_xm0 = EXTRACT_SUBREG %5, {{[0-9]+}}
63 # CHECK: %7:sreg_32_xm0 = EXTRACT_SUBREG %5, {{[0-9]+}}
61 # CHECK: %5:sreg_64 = EXTRACT_SUBREG %0, %subreg.sub0_sub1
62 # CHECK: %6:sreg_32_xm0 = EXTRACT_SUBREG %5, %subreg.sub0
63 # CHECK: %7:sreg_32_xm0 = EXTRACT_SUBREG %5, %subreg.sub1
6464 # CHECK: S_NOP 0, implicit %5
6565 # CHECK: S_NOP 0, implicit %6
6666 # CHECK: S_NOP 0, implicit undef %7
6767
6868 # CHECK: %8:sreg_64 = IMPLICIT_DEF
69 # CHECK: %9:sreg_32_xm0 = EXTRACT_SUBREG undef %8, {{[0-9]+}}
69 # CHECK: %9:sreg_32_xm0 = EXTRACT_SUBREG undef %8, %subreg.sub1
7070 # CHECK: S_NOP 0, implicit undef %9
7171
72 # CHECK: %10:sreg_128 = EXTRACT_SUBREG undef %0, {{[0-9]+}}
72 # CHECK: %10:sreg_128 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub3
7373 # CHECK: S_NOP 0, implicit undef %10
7474 name: test1
7575 registers:
124124 # CHECK: S_NOP 0, implicit-def dead %0
125125 # CHECK: S_NOP 0, implicit-def %1
126126 # CHECK: S_NOP 0, implicit-def %2
127 # CHECK: %3:sreg_128 = REG_SEQUENCE undef %0, {{[0-9]+}}, %1, {{[0-9]+}}, %2, {{[0-9]+}}
127 # CHECK: %3:sreg_128 = REG_SEQUENCE undef %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3
128128 # CHECK: S_NOP 0, implicit %3.sub1
129129 # CHECK: S_NOP 0, implicit %3.sub3
130130
131131 # CHECK: S_NOP 0, implicit-def %4
132132 # CHECK: S_NOP 0, implicit-def dead %5
133 # CHECK: %6:sreg_64 = REG_SEQUENCE %4, {{[0-9]+}}, undef %5, {{[0-9]+}}
133 # CHECK: %6:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1
134134 # CHECK: S_NOP 0, implicit %6
135135
136136 # CHECK: S_NOP 0, implicit-def dead %7
137137 # CHECK: S_NOP 0, implicit-def %8
138 # CHECK: %9:sreg_128 = INSERT_SUBREG undef %7, %8, {{[0-9]+}}
138 # CHECK: %9:sreg_128 = INSERT_SUBREG undef %7, %8, %subreg.sub2_sub3
139139 # CHECK: S_NOP 0, implicit %9.sub2
140140
141141 # CHECK: S_NOP 0, implicit-def %10
142142 # CHECK: S_NOP 0, implicit-def dead %11
143 # CHECK: %12:sreg_128 = INSERT_SUBREG %10, undef %11, {{[0-9]+}}
143 # CHECK: %12:sreg_128 = INSERT_SUBREG %10, undef %11, %subreg.sub0_sub1
144144 # CHECK: S_NOP 0, implicit %12.sub3
145145
146146 # CHECK: S_NOP 0, implicit-def %13
147147 # CHECK: S_NOP 0, implicit-def dead %14
148 # CHECK: %15:sreg_128 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}}
149 # CHECK: %16:sreg_64 = EXTRACT_SUBREG %15, {{[0-9]+}}
148 # CHECK: %15:sreg_128 = REG_SEQUENCE %13, %subreg.sub0_sub1, undef %14, %subreg.sub2_sub3
149 # CHECK: %16:sreg_64 = EXTRACT_SUBREG %15, %subreg.sub0_sub1
150150 # CHECK: S_NOP 0, implicit %16.sub1
151151
152152 name: test2
244244 # used.
245245 # CHECK-LABEL: name: test5
246246 # CHECK: S_NOP 0, implicit-def %0
247 # CHECK: %1:sreg_64 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}}
247 # CHECK: %1:sreg_64 = REG_SEQUENCE undef %0, %subreg.sub0, %0, %subreg.sub1
248248 # CHECK: S_NOP 0, implicit %1.sub1
249249 name: test5
250250 tracksRegLiveness: true
264264 # CHECK: S_NOP 0, implicit-def %0
265265 # CHECK: S_NOP 0, implicit-def dead %1
266266 # CHECK: S_NOP 0, implicit-def dead %2
267 # CHECK: %3:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}, undef %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
267 # CHECK: %3:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, undef %1, %subreg.sub1, undef %2, %subreg.sub2
268268
269269 # CHECK: bb.1:
270270 # CHECK: %4:sreg_128 = PHI %3, %bb.0, %5, %bb.1
314314 # CHECK: S_NOP 0, implicit-def %1
315315 # CHECK: S_NOP 0, implicit-def dead %2
316316 # CHECK: S_NOP 0, implicit-def %3
317 # CHECK: %4:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}, %3, {{[0-9]+}}
317 # CHECK: %4:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub2, %3, %subreg.sub3
318318
319319 # CHECK: bb.1:
320320 # CHECK: %5:sreg_128 = PHI %4, %bb.0, %6, %bb.1
321321
322 # CHECK: %6:sreg_128 = REG_SEQUENCE %5.sub1, {{[0-9]+}}, %5.sub3, {{[0-9]+}}, undef %5.sub2, {{[0-9]+}}, %5.sub0, {{[0-9]+}}
322 # CHECK: %6:sreg_128 = REG_SEQUENCE %5.sub1, %subreg.sub0, %5.sub3, %subreg.sub1, undef %5.sub2, %subreg.sub2, %5.sub0, %subreg.sub3
323323
324324 # CHECK: bb.2:
325325 # CHECK: S_NOP 0, implicit %6.sub3
360360 # CHECK-LABEL: name: loop2
361361 # CHECK: bb.0:
362362 # CHECK: S_NOP 0, implicit-def %0
363 # CHECK: %1:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}
363 # CHECK: %1:sreg_128 = REG_SEQUENCE %0, %subreg.sub0
364364
365365 # CHECK: bb.1:
366366 # CHECK: %2:sreg_128 = PHI %1, %bb.0, %3, %bb.1
367367
368 # CHECK: %3:sreg_128 = REG_SEQUENCE %2.sub3, {{[0-9]+}}, undef %2.sub1, {{[0-9]+}}, %2.sub0, {{[0-9]+}}, %2.sub2, {{[0-9]+}}
368 # CHECK: %3:sreg_128 = REG_SEQUENCE %2.sub3, %subreg.sub0, undef %2.sub1, %subreg.sub1, %2.sub0, %subreg.sub2, %2.sub2, %subreg.sub3
369369
370370 # CHECK: bb.2:
371371 # CHECK: S_NOP 0, implicit %2.sub0
44 # GCN-LABEL: {{^}}name: const_to_sgpr{{$}}
55 # GCN: %[[HI:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
66 # GCN-NEXT: %[[LO:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576
7 # GCN-NEXT: %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], 1, killed %[[HI]], 2
7 # GCN-NEXT: %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], %subreg.sub0, killed %[[HI]], %subreg.sub1
88 # GCN-NEXT: V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit %exec
99
1010
1111 # GCN-LABEL: {{^}}name: const_to_sgpr_multiple_use{{$}}
1212 # GCN: %[[HI:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
1313 # GCN-NEXT: %[[LO:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576
14 # GCN-NEXT: %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], 1, killed %[[HI]], 2
14 # GCN-NEXT: %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], %subreg.sub0, killed %[[HI]], %subreg.sub1
1515 # GCN-NEXT: V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit %exec
1616 # GCN-NEXT: V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit %exec
1717
1818 # GCN-LABEL: {{^}}name: const_to_sgpr_subreg{{$}}
19 # GCN: %[[OP0:[0-9]+]]:vreg_64 = REG_SEQUENCE killed %{{[0-9]+}}, 1, killed %{{[0-9]+}}, 2
19 # GCN: %[[OP0:[0-9]+]]:vreg_64 = REG_SEQUENCE killed %{{[0-9]+}}, %subreg.sub0, killed %{{[0-9]+}}, %subreg.sub1
2020 # GCN-NEXT: V_CMP_LT_U32_e64 killed %[[OP0]].sub0, 12, implicit %exec
2121
2222 --- |
108108 %8 = S_LOAD_DWORDX2_IMM %3, 11, 0
109109 %6 = COPY %7
110110 %9 = S_MOV_B32 0
111 %10 = REG_SEQUENCE %2, 1, killed %9, 2
111 %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1
112112 %0 = COPY %10
113113 %11 = COPY %10.sub0
114114 %12 = COPY %10.sub1
116116 %14 = COPY %8.sub1
117117 %15 = S_ADD_U32 killed %11, killed %13, implicit-def %scc
118118 %16 = S_ADDC_U32 killed %12, killed %14, implicit-def dead %scc, implicit %scc
119 %17 = REG_SEQUENCE killed %15, 1, killed %16, 2
119 %17 = REG_SEQUENCE killed %15, %subreg.sub0, killed %16, %subreg.sub1
120120 %18 = S_MOV_B32 0
121121 %19 = S_MOV_B32 1048576
122 %20 = REG_SEQUENCE killed %19, 1, killed %18, 2
122 %20 = REG_SEQUENCE killed %19, %subreg.sub0, killed %18, %subreg.sub1
123123 %22 = COPY killed %20
124124 %21 = V_CMP_LT_U64_e64 killed %17, %22, implicit %exec
125125 %1 = SI_IF killed %21, %bb.2.bb2, implicit-def dead %exec, implicit-def dead %scc, implicit %exec
132132 %24 = S_LSHL_B64 %0, killed %23, implicit-def dead %scc
133133 %25 = S_MOV_B32 61440
134134 %26 = S_MOV_B32 0
135 %27 = REG_SEQUENCE killed %26, 1, killed %25, 2
135 %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1
136136 %28 = REG_SEQUENCE %6, 17, killed %27, 18
137137 %29 = V_MOV_B32_e32 0, implicit %exec
138138 %30 = COPY %24
207207 %9 = S_LOAD_DWORDX2_IMM %3, 13, 0
208208 %6 = COPY %7
209209 %10 = S_MOV_B32 0
210 %11 = REG_SEQUENCE %2, 1, killed %10, 2
210 %11 = REG_SEQUENCE %2, %subreg.sub0, killed %10, %subreg.sub1
211211 %0 = COPY %11
212212 %12 = COPY %11.sub0
213213 %13 = COPY %11.sub1
215215 %15 = COPY %8.sub1
216216 %16 = S_ADD_U32 %12, killed %14, implicit-def %scc
217217 %17 = S_ADDC_U32 %13, killed %15, implicit-def dead %scc, implicit %scc
218 %18 = REG_SEQUENCE killed %16, 1, killed %17, 2
218 %18 = REG_SEQUENCE killed %16, %subreg.sub0, killed %17, %subreg.sub1
219219 %19 = COPY %9.sub0
220220 %20 = COPY %9.sub1
221221 %21 = S_ADD_U32 %12, killed %19, implicit-def %scc
222222 %22 = S_ADDC_U32 %13, killed %20, implicit-def dead %scc, implicit %scc
223 %23 = REG_SEQUENCE killed %21, 1, killed %22, 2
223 %23 = REG_SEQUENCE killed %21, %subreg.sub0, killed %22, %subreg.sub1
224224 %24 = S_MOV_B32 0
225225 %25 = S_MOV_B32 1048576
226 %26 = REG_SEQUENCE killed %25, 1, killed %24, 2
226 %26 = REG_SEQUENCE killed %25, %subreg.sub0, killed %24, %subreg.sub1
227227 %28 = COPY %26
228228 %27 = V_CMP_LT_U64_e64 killed %18, %28, implicit %exec
229229 %29 = V_CMP_LT_U64_e64 killed %23, %28, implicit %exec
238238 %33 = S_LSHL_B64 %0, killed %32, implicit-def dead %scc
239239 %34 = S_MOV_B32 61440
240240 %35 = S_MOV_B32 0
241 %36 = REG_SEQUENCE killed %35, 1, killed %34, 2
241 %36 = REG_SEQUENCE killed %35, %subreg.sub0, killed %34, %subreg.sub1
242242 %37 = REG_SEQUENCE %6, 17, killed %36, 18
243243 %38 = V_MOV_B32_e32 0, implicit %exec
244244 %39 = COPY %33
303303 %8 = S_LOAD_DWORDX2_IMM %3, 11, 0
304304 %6 = COPY %7
305305 %9 = S_MOV_B32 0
306 %10 = REG_SEQUENCE %2, 1, killed %9, 2
306 %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1
307307 %0 = COPY %10
308308 %11 = COPY %10.sub0
309309 %12 = COPY %10.sub1
311311 %14 = COPY %8.sub1
312312 %15 = S_ADD_U32 killed %11, killed %13, implicit-def %scc
313313 %16 = S_ADDC_U32 killed %12, killed %14, implicit-def dead %scc, implicit %scc
314 %17 = REG_SEQUENCE killed %15, 1, killed %16, 2
314 %17 = REG_SEQUENCE killed %15, %subreg.sub0, killed %16, %subreg.sub1
315315 %18 = S_MOV_B32 12
316316 %19 = S_MOV_B32 1048576
317 %20 = REG_SEQUENCE killed %19, 1, killed %18, 2
317 %20 = REG_SEQUENCE killed %19, %subreg.sub0, killed %18, %subreg.sub1
318318 %22 = COPY killed %20.sub1
319319 %21 = V_CMP_LT_U32_e64 killed %17.sub0, %22, implicit %exec
320320 %1 = SI_IF killed %21, %bb.2.bb2, implicit-def dead %exec, implicit-def dead %scc, implicit %exec
327327 %24 = S_LSHL_B64 %0, killed %23, implicit-def dead %scc
328328 %25 = S_MOV_B32 61440
329329 %26 = S_MOV_B32 0
330 %27 = REG_SEQUENCE killed %26, 1, killed %25, 2
330 %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1
331331 %28 = REG_SEQUENCE %6, 17, killed %27, 18
332332 %29 = V_MOV_B32_e32 0, implicit %exec
333333 %30 = COPY %24
2121 liveins: %edi, %eax
2222 ; CHECK-LABEL: name: t
2323 ; CHECK: liveins: %edi, %eax
24 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG %edi, %al, 1
25 ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG %eax, 2
26 ; CHECK: %ax = REG_SEQUENCE [[EXTRACT_SUBREG]], 1, [[EXTRACT_SUBREG]], 2
24 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
25 ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi
26 ; CHECK: %ax = REG_SEQUENCE [[EXTRACT_SUBREG]], %subreg.sub_8bit, [[EXTRACT_SUBREG]], %subreg.sub_8bit_hi
2727 ; CHECK: RETQ %ax
2828 %0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
2929 %1 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi
9999 ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY %sil
100100 ; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def %eflags
101101 ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit %eflags
102 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], 1
102 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
103103 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
104104 ; CHECK: %eax = COPY [[AND32ri8_]]
105105 ; CHECK: RET 0, implicit %eax
130130 ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY %si
131131 ; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def %eflags
132132 ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit %eflags
133 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], 1
133 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
134134 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
135135 ; CHECK: %eax = COPY [[AND32ri8_]]
136136 ; CHECK: RET 0, implicit %eax
161161 ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi
162162 ; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def %eflags
163163 ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit %eflags
164 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], 1
164 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
165165 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
166166 ; CHECK: %eax = COPY [[AND32ri8_]]
167167 ; CHECK: RET 0, implicit %eax
192192 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
193193 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
194194 ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit %eflags
195 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], 1
195 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
196196 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
197197 ; CHECK: %eax = COPY [[AND32ri8_]]
198198 ; CHECK: RET 0, implicit %eax
223223 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
224224 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
225225 ; CHECK: [[SETNEr:%[0-9]+]]:gr8 = SETNEr implicit %eflags
226 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETNEr]], 1
226 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETNEr]], %subreg.sub_8bit
227227 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
228228 ; CHECK: %eax = COPY [[AND32ri8_]]
229229 ; CHECK: RET 0, implicit %eax
254254 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
255255 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
256256 ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit %eflags
257 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAr]], 1
257 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAr]], %subreg.sub_8bit
258258 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
259259 ; CHECK: %eax = COPY [[AND32ri8_]]
260260 ; CHECK: RET 0, implicit %eax
285285 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
286286 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
287287 ; CHECK: [[SETAEr:%[0-9]+]]:gr8 = SETAEr implicit %eflags
288 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAEr]], 1
288 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAEr]], %subreg.sub_8bit
289289 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
290290 ; CHECK: %eax = COPY [[AND32ri8_]]
291291 ; CHECK: RET 0, implicit %eax
316316 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
317317 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
318318 ; CHECK: [[SETBr:%[0-9]+]]:gr8 = SETBr implicit %eflags
319 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBr]], 1
319 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBr]], %subreg.sub_8bit
320320 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
321321 ; CHECK: %eax = COPY [[AND32ri8_]]
322322 ; CHECK: RET 0, implicit %eax
347347 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
348348 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
349349 ; CHECK: [[SETBEr:%[0-9]+]]:gr8 = SETBEr implicit %eflags
350 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBEr]], 1
350 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBEr]], %subreg.sub_8bit
351351 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
352352 ; CHECK: %eax = COPY [[AND32ri8_]]
353353 ; CHECK: RET 0, implicit %eax
378378 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
379379 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
380380 ; CHECK: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit %eflags
381 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGr]], 1
381 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGr]], %subreg.sub_8bit
382382 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
383383 ; CHECK: %eax = COPY [[AND32ri8_]]
384384 ; CHECK: RET 0, implicit %eax
409409 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
410410 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
411411 ; CHECK: [[SETGEr:%[0-9]+]]:gr8 = SETGEr implicit %eflags
412 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGEr]], 1
412 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGEr]], %subreg.sub_8bit
413413 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
414414 ; CHECK: %eax = COPY [[AND32ri8_]]
415415 ; CHECK: RET 0, implicit %eax
440440 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
441441 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
442442 ; CHECK: [[SETLr:%[0-9]+]]:gr8 = SETLr implicit %eflags
443 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLr]], 1
443 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLr]], %subreg.sub_8bit
444444 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
445445 ; CHECK: %eax = COPY [[AND32ri8_]]
446446 ; CHECK: RET 0, implicit %eax
471471 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
472472 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
473473 ; CHECK: [[SETLEr:%[0-9]+]]:gr8 = SETLEr implicit %eflags
474 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLEr]], 1
474 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLEr]], %subreg.sub_8bit
475475 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
476476 ; CHECK: %eax = COPY [[AND32ri8_]]
477477 ; CHECK: RET 0, implicit %eax
4141 - { id: 0, class: gpr, preferred-register: '' }
4242 - { id: 1, class: gpr, preferred-register: '' }
4343 # ALL: %0:gr8 = COPY %al
44 # ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, 1
44 # ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit
4545 # ALL-NEXT: %1:gr32 = AND32ri8 %2, 1, implicit-def %eflags
4646 # ALL-NEXT: %eax = COPY %1
4747 # ALL-NEXT: RET 0, implicit %eax
145145 registers:
146146 - { id: 0, class: gpr, preferred-register: '' }
147147 # ALL: %0:gr8 = COPY %dl
148 # ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, 1
148 # ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit
149149 # ALL-NEXT: %eax = COPY %1
150150 # ALL-NEXT: RET 0, implicit %eax
151151 body: |
169169 registers:
170170 - { id: 0, class: gpr, preferred-register: '' }
171171 # ALL: %0:gr16 = COPY %dx
172 # ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, 3
172 # ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_16bit
173173 # ALL-NEXT: %eax = COPY %1
174174 # ALL-NEXT: RET 0, implicit %eax
175175 body: |
3838 ; ALL-LABEL: name: test_zext_i1
3939 ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
4040 ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]]
41 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 1
41 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
4242 ; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
4343 ; ALL: %rax = COPY [[AND64ri8_]]
4444 ; ALL: RET 0, implicit %rax
111111 ; ALL-LABEL: name: anyext_s64_from_s1
112112 ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY %rdi
113113 ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
114 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 1
114 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
115115 ; ALL: %rax = COPY [[SUBREG_TO_REG]]
116116 ; ALL: RET 0, implicit %rax
117117 %0(s64) = COPY %rdi
136136 ; ALL-LABEL: name: anyext_s64_from_s8
137137 ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY %rdi
138138 ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
139 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 1
139 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
140140 ; ALL: %rax = COPY [[SUBREG_TO_REG]]
141141 ; ALL: RET 0, implicit %rax
142142 %0(s64) = COPY %rdi
161161 ; ALL-LABEL: name: anyext_s64_from_s16
162162 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
163163 ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
164 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 3
164 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_16bit
165165 ; ALL: %rax = COPY [[SUBREG_TO_REG]]
166166 ; ALL: RET 0, implicit %rax
167167 %0(s64) = COPY %rdi
186186 ; ALL-LABEL: name: anyext_s64_from_s32
187187 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
188188 ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
189 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 4
189 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32bit
190190 ; ALL: %rax = COPY [[SUBREG_TO_REG]]
191191 ; ALL: RET 0, implicit %rax
192192 %0(s64) = COPY %rdi
8484 - { id: 0, class: gpr, preferred-register: '' }
8585 - { id: 1, class: gpr, preferred-register: '' }
8686 # ALL: %0:gr8 = COPY %dil
87 # ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %0, 1
87 # ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit
8888 # ALL-NEXT: %1:gr16 = AND16ri8 %2, 1, implicit-def %eflags
8989 # ALL-NEXT: %ax = COPY %1
9090 # ALL-NEXT: RET 0, implicit %ax
112112 - { id: 0, class: gpr }
113113 - { id: 1, class: gpr }
114114 # ALL: %0:gr8 = COPY %dil
115 # ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, 1
115 # ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit
116116 # ALL-NEXT: %1:gr32 = AND32ri8 %2, 1, implicit-def %eflags
117117 # ALL-NEXT: %eax = COPY %1
118118 # ALL-NEXT: RET 0, implicit %eax
287287 # X32: %0:gr32_abcd = COPY %edi
288288 # X64: %0:gr32 = COPY %edi
289289 # ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
290 # ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, 1
290 # ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
291291 # ALL-NEXT: %ax = COPY %2
292292 # ALL-NEXT: RET 0, implicit %ax
293293 body: |
322322 # X32: %0:gr32_abcd = COPY %edi
323323 # X64: %0:gr32 = COPY %edi
324324 # ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
325 # ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, 1
325 # ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
326326 # ALL-NEXT: %eax = COPY %2
327327 # ALL-NEXT: RET 0, implicit %eax
328328 body: |
357357 # X32: %0:gr32_abcd = COPY %edi
358358 # X64: %0:gr32 = COPY %edi
359359 # ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
360 # ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, 1
360 # ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
361361 # ALL-NEXT: %ax = COPY %2
362362 # ALL-NEXT: RET 0, implicit %ax
363363 body: |
421421 - { id: 2, class: gpr }
422422 # ALL: %0:gr32 = COPY %edi
423423 # ALL-NEXT: %1:gr16 = COPY %0.sub_16bit
424 # ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, 3
424 # ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_16bit
425425 # ALL-NEXT: %eax = COPY %2
426426 # ALL-NEXT: RET 0, implicit %eax
427427 body: |
1919 bb.0:
2020 ; CHECK-LABEL: name: read_flags
2121 ; CHECK: [[RDFLAGS32_:%[0-9]+]]:gr32 = RDFLAGS32 implicit-def %esp, implicit %esp
22 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[RDFLAGS32_]], 4
22 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[RDFLAGS32_]], %subreg.sub_32bit
2323 ; CHECK: %rax = COPY [[SUBREG_TO_REG]]
2424 %0(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.read.u32)
2525 %rax = COPY %0(s32)