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Merging r329852: ------------------------------------------------------------------------ r329852 | nemanjai | 2018-04-11 14:25:44 -0700 (Wed, 11 Apr 2018) | 8 lines [PowerPC] Fix condition for 64-bit rotate when replacing r+r instr with r+i This patch fixes https://bugs.llvm.org/show_bug.cgi?id=37039 The condition only covers one of the two 64-bit rotate instructions. This just adds the second (RLDICLo). Patch by Josh Stone. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@330076 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
2 changed file(s) with 66 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
24302430 // Use APInt's rotate function.
24312431 int64_t SH = MI.getOperand(2).getImm();
24322432 int64_t MB = MI.getOperand(3).getImm();
2433 APInt InVal(Opc == PPC::RLDICL ? 64 : 32, SExtImm, true);
2433 APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
2434 64 : 32, SExtImm, true);
24342435 InVal = InVal.rotl(SH);
24352436 uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
24362437 InVal &= Mask;
551551
552552 ; Function Attrs: norecurse nounwind readnone
553553 define i64 @testRLDICLo(i64 %a, i64 %b) local_unnamed_addr #0 {
554 entry:
555 %shr = lshr i64 %a, 11
556 %and = and i64 %shr, 16777215
557 %tobool = icmp eq i64 %and, 0
558 %cond = select i1 %tobool, i64 %b, i64 %and
559 ret i64 %cond
560 }
561
562 ; Function Attrs: norecurse nounwind readnone
563 define i64 @testRLDICLo3(i64 %a, i64 %b) local_unnamed_addr #0 {
554564 entry:
555565 %shr = lshr i64 %a, 11
556566 %and = and i64 %shr, 16777215
39033913
39043914 ...
39053915 ---
3916 name: testRLDICLo3
3917 # CHECK-ALL: name: testRLDICLo3
3918 alignment: 4
3919 exposesReturnsTwice: false
3920 legalized: false
3921 regBankSelected: false
3922 selected: false
3923 tracksRegLiveness: true
3924 registers:
3925 - { id: 0, class: g8rc, preferred-register: '' }
3926 - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
3927 - { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }
3928 - { id: 3, class: crrc, preferred-register: '' }
3929 - { id: 4, class: g8rc, preferred-register: '' }
3930 liveins:
3931 - { reg: '%x3', virtual-reg: '%0' }
3932 - { reg: '%x4', virtual-reg: '%1' }
3933 frameInfo:
3934 isFrameAddressTaken: false
3935 isReturnAddressTaken: false
3936 hasStackMap: false
3937 hasPatchPoint: false
3938 stackSize: 0
3939 offsetAdjustment: 0
3940 maxAlignment: 0
3941 adjustsStack: false
3942 hasCalls: false
3943 stackProtector: ''
3944 maxCallFrameSize: 4294967295
3945 hasOpaqueSPAdjustment: false
3946 hasVAStart: false
3947 hasMustTailInVarArgFunc: false
3948 savePoint: ''
3949 restorePoint: ''
3950 fixedStack:
3951 stack:
3952 constants:
3953 body: |
3954 bb.0.entry:
3955 liveins: %x3, %x4
3956
3957 %1 = COPY %x4
3958 %0 = LI8 2
3959 %2 = RLDICLo %0, 32, 32, implicit-def %cr0
3960 ; CHECK: ANDIo8 %0, 0
3961 ; CHECK-LATE: li 3, 2
3962 ; CHECK-LATE: andi. 3, 3, 0
3963 %3 = COPY killed %cr0
3964 %4 = ISEL8 %1, %2, %3.sub_eq
3965 %x3 = COPY %4
3966 BLR8 implicit %lr8, implicit %rm, implicit %x3
3967
3968 ...
3969 ---
39063970 name: testRLWINM
39073971 # CHECK-ALL: name: testRLWINM
39083972 alignment: 4