llvm.org GIT mirror llvm / 4c3715c
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8 David Goodwin 10 years ago
11 changed file(s) with 44 addition(s) and 23 deletion(s). Raw diff Collapse all Expand all
3232 protected: // Can only create subclasses...
3333 TargetSubtarget();
3434 public:
35 // AntiDepBreakMode - Type of anti-dependence breaking that should
36 // be performed before post-RA scheduling.
37 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
38
3539 virtual ~TargetSubtarget();
3640
3741 /// getSpecialAddressLatency - For targets where it is beneficial to
4246
4347 // enablePostRAScheduler - If the target can benefit from post-regalloc
4448 // scheduling and the specified optimization level meets the requirement
45 // return true to enable post-register-allocation scheduling.
46 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
49 // return true to enable post-register-allocation scheduling.
50 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
51 AntiDepBreakMode& mode) const {
52 mode = ANTIDEP_NONE;
4753 return false;
4854 }
4955
127127 /// AA - AliasAnalysis for making memory reference queries.
128128 AliasAnalysis *AA;
129129
130 /// AntiDepMode - Anti-dependence breaking mode
131 TargetSubtarget::AntiDepBreakMode AntiDepMode;
132
130133 /// Classes - For live regs that are only used in one register class in a
131134 /// live range, the register class. If the register is not live, the
132135 /// corresponding value is null. If the register is live but used in
155158 const MachineLoopInfo &MLI,
156159 const MachineDominatorTree &MDT,
157160 ScheduleHazardRecognizer *HR,
158 AliasAnalysis *aa)
161 AliasAnalysis *aa,
162 TargetSubtarget::AntiDepBreakMode adm)
159163 : ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
160164 AllocatableSet(TRI->getAllocatableSet(MF)),
161 HazardRec(HR), AA(aa) {}
165 HazardRec(HR), AA(aa), AntiDepMode(adm) {}
162166
163167 ~SchedulePostRATDList() {
164168 delete HazardRec;
233237 AA = &getAnalysis();
234238
235239 // Check for explicit enable/disable of post-ra scheduling.
240 TargetSubtarget::AntiDepBreakMode AntiDepMode = TargetSubtarget::ANTIDEP_NONE;
236241 if (EnablePostRAScheduler.getPosition() > 0) {
237242 if (!EnablePostRAScheduler)
238243 return false;
239244 } else {
240245 // Check that post-RA scheduling is enabled for this target.
241246 const TargetSubtarget &ST = Fn.getTarget().getSubtarget();
242 if (!ST.enablePostRAScheduler(OptLevel))
247 if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode))
243248 return false;
249 }
250
251 // Check for antidep breaking override...
252 if (EnableAntiDepBreaking.getPosition() > 0) {
253 AntiDepMode = (EnableAntiDepBreaking) ?
254 TargetSubtarget::ANTIDEP_CRITICAL : TargetSubtarget::ANTIDEP_NONE;
244255 }
245256
246257 DEBUG(errs() << "PostRAScheduler\n");
252263 (ScheduleHazardRecognizer *)new ExactHazardRecognizer(InstrItins) :
253264 (ScheduleHazardRecognizer *)new SimpleHazardRecognizer();
254265
255 SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR, AA);
266 SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR, AA, AntiDepMode);
256267
257268 // Loop over all of the basic blocks
258269 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
392403 // Build the scheduling graph.
393404 BuildSchedGraph(AA);
394405
395 if (EnableAntiDepBreaking) {
406 if (AntiDepMode != TargetSubtarget::ANTIDEP_NONE) {
396407 if (BreakAntiDependencies()) {
397408 // We made changes. Update the dependency graph.
398409 // Theoretically we could update the graph in place:
127127
128128 /// enablePostRAScheduler - True at 'More' optimization except
129129 /// for Thumb1.
130 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
130 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
131 TargetSubtarget::AntiDepBreakMode& mode) const {
132 mode = TargetSubtarget::ANTIDEP_NONE;
131133 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
132134 }
133135
217217
218218 /// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
219219 /// at 'More' optimization level.
220 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
220 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
221 TargetSubtarget::AntiDepBreakMode& mode) const {
222 mode = TargetSubtarget::ANTIDEP_NONE;
221223 return OptLevel >= CodeGenOpt::Default;
222224 }
223225 };
1010 %tmp14 = fadd float %tmp12, %tmp7
1111 ret float %tmp14
1212
13 ; CHECK: mulss LCPI1_0(%rip)
14 ; CHECK-NEXT: mulss LCPI1_1(%rip)
15 ; CHECK-NEXT: addss
1316 ; CHECK: mulss LCPI1_3(%rip)
14 ; CHECK-NEXT: mulss LCPI1_0(%rip)
15 ; CHECK-NEXT: mulss LCPI1_1(%rip)
1617 ; CHECK-NEXT: mulss LCPI1_2(%rip)
17 ; CHECK-NEXT: addss
1818 ; CHECK-NEXT: addss
1919 ; CHECK-NEXT: addss
2020 ; CHECK-NEXT: ret
99
1010 ; CHECK: t1:
1111 ; CHECK: movl 8(%esp), %eax
12 ; CHECK-NEXT: movl 4(%esp), %ecx
1312 ; CHECK-NEXT: movapd (%eax), %xmm0
13 ; CHECK-NEXT: movl 4(%esp), %eax
1414 ; CHECK-NEXT: movlpd 12(%esp), %xmm0
15 ; CHECK-NEXT: movapd %xmm0, (%ecx)
15 ; CHECK-NEXT: movapd %xmm0, (%eax)
1616 ; CHECK-NEXT: ret
1717 }
1818
2525
2626 ; CHECK: t2:
2727 ; CHECK: movl 8(%esp), %eax
28 ; CHECK-NEXT: movl 4(%esp), %ecx
2928 ; CHECK-NEXT: movapd (%eax), %xmm0
29 ; CHECK-NEXT: movl 4(%esp), %eax
3030 ; CHECK-NEXT: movhpd 12(%esp), %xmm0
31 ; CHECK-NEXT: movapd %xmm0, (%ecx)
31 ; CHECK-NEXT: movapd %xmm0, (%eax)
3232 ; CHECK-NEXT: ret
3333 }
167167 ret void
168168 ; X64: t10:
169169 ; X64: pextrw $4, %xmm0, %eax
170 ; X64: pextrw $6, %xmm0, %edx
171170 ; X64: movlhps %xmm1, %xmm1
172171 ; X64: pshuflw $8, %xmm1, %xmm1
173172 ; X64: pinsrw $2, %eax, %xmm1
174 ; X64: pinsrw $3, %edx, %xmm1
173 ; X64: pextrw $6, %xmm0, %eax
174 ; X64: pinsrw $3, %eax, %xmm1
175175 }
176176
177177
6262 ; CHECK: shift3b:
6363 ; CHECK: movzwl
6464 ; CHECK: movd
65 ; CHECK-NEXT: psllw
65 ; CHECK: psllw
6666 %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
6767 %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
6868 %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
6262 ; CHECK: shift3b:
6363 ; CHECK: movzwl
6464 ; CHECK: movd
65 ; CHECK-NEXT: psrlw
65 ; CHECK: psrlw
6666 %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
6767 %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
6868 %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
5151 ; CHECK: shift3b:
5252 ; CHECK: movzwl
5353 ; CHECK: movd
54 ; CHECK-NEXT: psraw
54 ; CHECK: psraw
5555 %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
5656 %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
5757 %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
55 entry:
66 ; CHECK: shift5a:
77 ; CHECK: movd
8 ; CHECK-NEXT: pslld
8 ; CHECK: pslld
99 %amt = load i32* %pamt
1010 %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
1111 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
1919 entry:
2020 ; CHECK: shift5b:
2121 ; CHECK: movd
22 ; CHECK-NEXT: psrad
22 ; CHECK: psrad
2323 %amt = load i32* %pamt
2424 %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
2525 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer