llvm.org GIT mirror llvm / 4bdc127
[ARM] Use new assembler diags for ARM This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314779 91177308-0d34-0410-b5e6-96231b3b80d8 Oliver Stannard 2 years ago
43 changed file(s) with 2467 addition(s) and 2136 deletion(s). Raw diff Collapse all Expand all
10211021 bit isMCAsmWriter = 1;
10221022 }
10231023
1024 def ARMAsmParser : AsmParser {
1025 bit ReportMultipleNearMisses = 1;
1026 }
1027
10241028 def ARMAsmParserVariant : AsmParserVariant {
10251029 int Variant = 0;
10261030 string Name = "ARM";
10311035 // Pull in Instruction Info.
10321036 let InstructionSet = ARMInstrInfo;
10331037 let AssemblyWriters = [ARMAsmWriter];
1038 let AssemblyParsers = [ARMAsmParser];
10341039 let AssemblyParserVariants = [ARMAsmParserVariant];
10351040 }
1616 #include "llvm/ADT/APInt.h"
1717 #include "llvm/ADT/None.h"
1818 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallSet.h"
1920 #include "llvm/ADT/SmallVector.h"
2021 #include "llvm/ADT/StringMap.h"
2122 #include "llvm/ADT/StringRef.h"
8384 static cl::opt AddBuildAttributes("arm-add-build-attributes",
8485 cl::init(false));
8586
87 cl::opt
88 DevDiags("arm-asm-parser-dev-diags", cl::init(false),
89 cl::desc("Use extended diagnostics, which include implementation "
90 "details useful for development"));
91
8692 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
8793
8894 class UnwindContext {
607613 uint64_t &ErrorInfo,
608614 bool MatchingInlineAsm) override;
609615 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
610 uint64_t &ErrorInfo, bool MatchingInlineAsm,
611 bool &EmitInITBlock, MCStreamer &Out);
616 SmallVectorImpl &NearMisses,
617 bool MatchingInlineAsm, bool &EmitInITBlock,
618 MCStreamer &Out);
619
620 struct NearMissMessage {
621 SMLoc Loc;
622 SmallString<128> Message;
623 };
624
625 const char *getOperandMatchFailDiag(ARMMatchResultTy Error);
626 void FilterNearMisses(SmallVectorImpl &NearMissesIn,
627 SmallVectorImpl &NearMissesOut,
628 SMLoc IDLoc, OperandVector &Operands);
629 void ReportNearMisses(SmallVectorImpl &NearMisses, SMLoc IDLoc,
630 OperandVector &Operands);
631
612632 void onLabelParsed(MCSymbol *Symbol) override;
613633 };
614634
89088928 }
89098929
89108930 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
8911 uint64_t &ErrorInfo,
8931 SmallVectorImpl &NearMisses,
89128932 bool MatchingInlineAsm,
89138933 bool &EmitInITBlock,
89148934 MCStreamer &Out) {
89158935 // If we can't use an implicit IT block here, just match as normal.
89168936 if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb())
8917 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
8937 return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
89188938
89198939 // Try to match the instruction in an extension of the current IT block (if
89208940 // there is one).
89218941 if (inImplicitITBlock()) {
89228942 extendImplicitITBlock(ITState.Cond);
8923 if (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm) ==
8943 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
89248944 Match_Success) {
89258945 // The match succeded, but we still have to check that the instruction is
89268946 // valid in this implicit IT block.
89468966 // Finish the current IT block, and try to match outside any IT block.
89478967 flushPendingInstructions(Out);
89488968 unsigned PlainMatchResult =
8949 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
8969 MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
89508970 if (PlainMatchResult == Match_Success) {
89518971 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
89528972 if (MCID.isPredicable()) {
89738993 // condition, so we create an IT block with a dummy condition, and fix it up
89748994 // once we know the actual condition.
89758995 startImplicitITBlock();
8976 if (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm) ==
8996 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
89778997 Match_Success) {
89788998 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
89798999 if (MCID.isPredicable()) {
90039023 unsigned MatchResult;
90049024 bool PendConditionalInstruction = false;
90059025
9006 MatchResult = MatchInstruction(Operands, Inst, ErrorInfo, MatchingInlineAsm,
9026 SmallVector NearMisses;
9027 MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm,
90079028 PendConditionalInstruction, Out);
90089029
90099030 SMLoc ErrorLoc;
90609081 Out.EmitInstruction(Inst, getSTI());
90619082 }
90629083 return false;
9063 case Match_MissingFeature: {
9064 assert(ErrorInfo && "Unknown missing feature!");
9065 // Special case the error message for the very common case where only
9066 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
9067 std::string Msg = "instruction requires:";
9068 uint64_t Mask = 1;
9069 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
9070 if (ErrorInfo & Mask) {
9071 Msg += " ";
9072 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
9073 }
9074 Mask <<= 1;
9075 }
9076 return Error(IDLoc, Msg);
9077 }
9078 case Match_InvalidOperand: {
9079 SMLoc ErrorLoc = IDLoc;
9080 if (ErrorInfo != ~0ULL) {
9081 if (ErrorInfo >= Operands.size())
9082 return Error(IDLoc, "too few operands for instruction");
9083
9084 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
9085 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
9086 }
9087
9088 return Error(ErrorLoc, "invalid operand for instruction");
9089 }
9084 case Match_NearMisses:
9085 ReportNearMisses(NearMisses, IDLoc, Operands);
9086 return true;
90909087 case Match_MnemonicFail: {
90919088 uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
90929089 std::string Suggestion = ARMMnemonicSpellCheck(
90949091 return Error(IDLoc, "invalid instruction" + Suggestion,
90959092 ((ARMOperand &)*Operands[0]).getLocRange());
90969093 }
9097 case Match_RequiresNotITBlock:
9098 return Error(IDLoc, "flag setting instruction only valid outside IT block");
9099 case Match_RequiresITBlock:
9100 return Error(IDLoc, "instruction only valid inside IT block");
9101 case Match_RequiresV6:
9102 return Error(IDLoc, "instruction variant requires ARMv6 or later");
9103 case Match_RequiresThumb2:
9104 return Error(IDLoc, "instruction variant requires Thumb2");
9105 case Match_RequiresV8:
9106 return Error(IDLoc, "instruction variant requires ARMv8 or later");
9107 case Match_RequiresFlagSetting:
9108 return Error(IDLoc, "no flag-preserving variant of this instruction available");
9109 case Match_ImmRange0_1:
9110 return Error(ErrorLoc, "immediate operand must be in the range [0,1]");
9111 case Match_ImmRange0_3:
9112 return Error(ErrorLoc, "immediate operand must be in the range [0,3]");
9113 case Match_ImmRange0_7:
9114 return Error(ErrorLoc, "immediate operand must be in the range [0,7]");
9115 case Match_ImmRange0_15:
9116 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
9117 case Match_ImmRange0_31:
9118 return Error(ErrorLoc, "immediate operand must be in the range [0,31]");
9119 case Match_ImmRange0_32:
9120 return Error(ErrorLoc, "immediate operand must be in the range [0,32]");
9121 case Match_ImmRange0_63:
9122 return Error(ErrorLoc, "immediate operand must be in the range [0,63]");
9123 case Match_ImmRange0_239:
9124 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
9125 case Match_ImmRange0_255:
9126 return Error(ErrorLoc, "immediate operand must be in the range [0,255]");
9127 case Match_ImmRange0_4095:
9128 return Error(ErrorLoc, "immediate operand must be in the range [0,4095]");
9129 case Match_ImmRange0_65535:
9130 return Error(ErrorLoc, "immediate operand must be in the range [0,65535]");
9131 case Match_ImmRange1_7:
9132 return Error(ErrorLoc, "immediate operand must be in the range [1,7]");
9133 case Match_ImmRange1_8:
9134 return Error(ErrorLoc, "immediate operand must be in the range [1,8]");
9135 case Match_ImmRange1_15:
9136 return Error(ErrorLoc, "immediate operand must be in the range [1,15]");
9137 case Match_ImmRange1_16:
9138 return Error(ErrorLoc, "immediate operand must be in the range [1,16]");
9139 case Match_ImmRange1_31:
9140 return Error(ErrorLoc, "immediate operand must be in the range [1,31]");
9141 case Match_ImmRange1_32:
9142 return Error(ErrorLoc, "immediate operand must be in the range [1,32]");
9143 case Match_ImmRange1_64:
9144 return Error(ErrorLoc, "immediate operand must be in the range [1,64]");
9145 case Match_ImmRange8_8:
9146 return Error(ErrorLoc, "immediate operand must be 8.");
9147 case Match_ImmRange16_16:
9148 return Error(ErrorLoc, "immediate operand must be 16.");
9149 case Match_ImmRange32_32:
9150 return Error(ErrorLoc, "immediate operand must be 32.");
9151 case Match_ImmRange256_65535:
9152 return Error(ErrorLoc, "immediate operand must be in the range [255,65535]");
9153 case Match_ImmRange0_16777215:
9154 return Error(ErrorLoc, "immediate operand must be in the range [0,0xffffff]");
9155 case Match_AlignedMemoryRequiresNone:
9156 case Match_DupAlignedMemoryRequiresNone:
9157 case Match_AlignedMemoryRequires16:
9158 case Match_DupAlignedMemoryRequires16:
9159 case Match_AlignedMemoryRequires32:
9160 case Match_DupAlignedMemoryRequires32:
9161 case Match_AlignedMemoryRequires64:
9162 case Match_DupAlignedMemoryRequires64:
9163 case Match_AlignedMemoryRequires64or128:
9164 case Match_DupAlignedMemoryRequires64or128:
9165 case Match_AlignedMemoryRequires64or128or256:
9166 {
9167 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
9168 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
9169 switch (MatchResult) {
9170 default:
9171 llvm_unreachable("Missing Match_Aligned type");
9172 case Match_AlignedMemoryRequiresNone:
9173 case Match_DupAlignedMemoryRequiresNone:
9174 return Error(ErrorLoc, "alignment must be omitted");
9175 case Match_AlignedMemoryRequires16:
9176 case Match_DupAlignedMemoryRequires16:
9177 return Error(ErrorLoc, "alignment must be 16 or omitted");
9178 case Match_AlignedMemoryRequires32:
9179 case Match_DupAlignedMemoryRequires32:
9180 return Error(ErrorLoc, "alignment must be 32 or omitted");
9181 case Match_AlignedMemoryRequires64:
9182 case Match_DupAlignedMemoryRequires64:
9183 return Error(ErrorLoc, "alignment must be 64 or omitted");
9184 case Match_AlignedMemoryRequires64or128:
9185 case Match_DupAlignedMemoryRequires64or128:
9186 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
9187 case Match_AlignedMemoryRequires64or128or256:
9188 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
9189 }
9190 }
9191 case Match_InvalidComplexRotationEven:
9192 return Error(IDLoc, "complex rotation must be 0, 90, 180 or 270");
9193 case Match_InvalidComplexRotationOdd:
9194 return Error(IDLoc, "complex rotation must be 90 or 270");
91959094 }
91969095
91979096 llvm_unreachable("Implement any new match types added!");
1020210101 #define GET_MATCHER_IMPLEMENTATION
1020310102 #include "ARMGenAsmMatcher.inc"
1020410103
10104 const char *ARMAsmParser::getOperandMatchFailDiag(ARMMatchResultTy Error) {
10105 switch (Error) {
10106 case Match_AlignedMemoryRequiresNone:
10107 case Match_DupAlignedMemoryRequiresNone:
10108 return "alignment must be omitted";
10109 case Match_AlignedMemoryRequires16:
10110 case Match_DupAlignedMemoryRequires16:
10111 return "alignment must be 16 or omitted";
10112 case Match_AlignedMemoryRequires32:
10113 case Match_DupAlignedMemoryRequires32:
10114 return "alignment must be 32 or omitted";
10115 case Match_AlignedMemoryRequires64:
10116 case Match_DupAlignedMemoryRequires64:
10117 return "alignment must be 64 or omitted";
10118 case Match_AlignedMemoryRequires64or128:
10119 case Match_DupAlignedMemoryRequires64or128:
10120 return "alignment must be 64, 128 or omitted";
10121 case Match_AlignedMemoryRequires64or128or256:
10122 return "alignment must be 64, 128, 256 or omitted";
10123 case Match_ImmRange0_1:
10124 return "immediate operand must be in the range [0,1]";
10125 case Match_ImmRange0_3:
10126 return "immediate operand must be in the range [0,3]";
10127 case Match_ImmRange0_7:
10128 return "immediate operand must be in the range [0,7]";
10129 case Match_ImmRange0_15:
10130 return "immediate operand must be in the range [0,15]";
10131 case Match_ImmRange0_31:
10132 return "immediate operand must be in the range [0,31]";
10133 case Match_ImmRange0_32:
10134 return "immediate operand must be in the range [0,32]";
10135 case Match_ImmRange0_63:
10136 return "immediate operand must be in the range [0,63]";
10137 case Match_ImmRange0_239:
10138 return "immediate operand must be in the range [0,239]";
10139 case Match_ImmRange0_255:
10140 return "immediate operand must be in the range [0,255]";
10141 case Match_ImmRange0_4095:
10142 return "immediate operand must be in the range [0,4095]";
10143 case Match_ImmRange0_65535:
10144 return "immediate operand must be in the range [0,65535]";
10145 case Match_ImmRange1_7:
10146 return "immediate operand must be in the range [1,7]";
10147 case Match_ImmRange1_8:
10148 return "immediate operand must be in the range [1,8]";
10149 case Match_ImmRange1_15:
10150 return "immediate operand must be in the range [1,15]";
10151 case Match_ImmRange1_16:
10152 return "immediate operand must be in the range [1,16]";
10153 case Match_ImmRange1_31:
10154 return "immediate operand must be in the range [1,31]";
10155 case Match_ImmRange1_32:
10156 return "immediate operand must be in the range [1,32]";
10157 case Match_ImmRange1_64:
10158 return "immediate operand must be in the range [1,64]";
10159 case Match_ImmRange8_8:
10160 return "immediate operand must be 8.";
10161 case Match_ImmRange16_16:
10162 return "immediate operand must be 16.";
10163 case Match_ImmRange32_32:
10164 return "immediate operand must be 32.";
10165 case Match_ImmRange256_65535:
10166 return "immediate operand must be in the range [255,65535]";
10167 case Match_ImmRange0_16777215:
10168 return "immediate operand must be in the range [0,0xffffff]";
10169 case Match_InvalidComplexRotationEven:
10170 return "complex rotation must be 0, 90, 180 or 270";
10171 case Match_InvalidComplexRotationOdd:
10172 return "complex rotation must be 90 or 270";
10173 default:
10174 return nullptr;
10175 }
10176 }
10177
10178 // Process the list of near-misses, throwing away ones we don't want to report
10179 // to the user, and converting the rest to a source location and string that
10180 // should be reported.
10181 void
10182 ARMAsmParser::FilterNearMisses(SmallVectorImpl &NearMissesIn,
10183 SmallVectorImpl &NearMissesOut,
10184 SMLoc IDLoc, OperandVector &Operands) {
10185 // TODO: If operand didn't match, sub in a dummy one and run target
10186 // predicate, so that we can avoid reporting near-misses that are invalid?
10187 // TODO: Many operand types dont have SuperClasses set, so we report
10188 // redundant ones.
10189 // TODO: Some operands are superclasses of registers (e.g.
10190 // MCK_RegShiftedImm), we don't have any way to represent that currently.
10191 // TODO: This is not all ARM-specific, can some of it be factored out?
10192
10193 // Record some information about near-misses that we have already seen, so
10194 // that we can avoid reporting redundant ones. For example, if there are
10195 // variants of an instruction that take 8- and 16-bit immediates, we want
10196 // to only report the widest one.
10197 std::multimap OperandMissesSeen;
10198 SmallSet FeatureMissesSeen;
10199
10200 // Process the near-misses in reverse order, so that we see more general ones
10201 // first, and so can avoid emitting more specific ones.
10202 for (NearMissInfo &I : reverse(NearMissesIn)) {
10203 switch (I.getKind()) {
10204 case NearMissInfo::NearMissOperand: {
10205 SMLoc OperandLoc =
10206 ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc();
10207 const char *OperandDiag =
10208 getOperandMatchFailDiag((ARMMatchResultTy)I.getOperandError());
10209
10210 // If we have already emitted a message for a superclass, don't also report
10211 // the sub-class. We consider all operand classes that we don't have a
10212 // specialised diagnostic for to be equal for the propose of this check,
10213 // so that we don't report the generic error multiple times on the same
10214 // operand.
10215 unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U;
10216 auto PrevReports = OperandMissesSeen.equal_range(I.getOperandIndex());
10217 if (std::any_of(PrevReports.first, PrevReports.second,
10218 [DupCheckMatchClass](
10219 const std::pair Pair) {
10220 if (DupCheckMatchClass == ~0U)
10221 return Pair.second == ~0U;
10222 else
10223 return isSubclass((MatchClassKind)DupCheckMatchClass,
10224 (MatchClassKind)Pair.second);
10225 }))
10226 break;
10227 OperandMissesSeen.insert(
10228 std::make_pair(I.getOperandIndex(), DupCheckMatchClass));
10229
10230 NearMissMessage Message;
10231 Message.Loc = OperandLoc;
10232 raw_svector_ostream OS(Message.Message);
10233 if (OperandDiag) {
10234 OS << OperandDiag;
10235 } else if (I.getOperandClass() == InvalidMatchClass) {
10236 OS << "too many operands for instruction";
10237 } else {
10238 OS << "invalid operand for instruction";
10239 if (DevDiags) {
10240 OS << " class" << I.getOperandClass() << ", error "
10241 << I.getOperandError() << ", opcode "
10242 << MII.getName(I.getOpcode());
10243 }
10244 }
10245 NearMissesOut.emplace_back(Message);
10246 break;
10247 }
10248 case NearMissInfo::NearMissFeature: {
10249 uint64_t MissingFeatures = I.getFeatures();
10250 // Don't report the same set of features twice.
10251 if (FeatureMissesSeen.count(MissingFeatures))
10252 break;
10253 FeatureMissesSeen.insert(MissingFeatures);
10254
10255 // Special case: don't report a feature set which includes arm-mode for
10256 // targets that don't have ARM mode.
10257 if ((MissingFeatures & Feature_IsARM) && !hasARM())
10258 break;
10259 // Don't report any near-misses that both require switching instruction
10260 // set, and adding other subtarget features.
10261 if (isThumb() && (MissingFeatures & Feature_IsARM) &&
10262 (MissingFeatures & ~Feature_IsARM))
10263 break;
10264 if (!isThumb() && (MissingFeatures & Feature_IsThumb) &&
10265 (MissingFeatures & ~Feature_IsThumb))
10266 break;
10267 if (!isThumb() && (MissingFeatures & Feature_IsThumb2) &&
10268 (MissingFeatures & ~(Feature_IsThumb2 | Feature_IsThumb)))
10269 break;
10270
10271 NearMissMessage Message;
10272 Message.Loc = IDLoc;
10273 raw_svector_ostream OS(Message.Message);
10274
10275 OS << "instruction requires:";
10276 uint64_t Mask = 1;
10277 for (unsigned MaskPos = 0; MaskPos < (sizeof(MissingFeatures) * 8 - 1);
10278 ++MaskPos) {
10279 if (MissingFeatures & Mask) {
10280 OS << " " << getSubtargetFeatureName(MissingFeatures & Mask);
10281 }
10282 Mask <<= 1;
10283 }
10284 NearMissesOut.emplace_back(Message);
10285
10286 break;
10287 }
10288 case NearMissInfo::NearMissPredicate: {
10289 NearMissMessage Message;
10290 Message.Loc = IDLoc;
10291 switch (I.getPredicateError()) {
10292 case Match_RequiresNotITBlock:
10293 Message.Message = "flag setting instruction only valid outside IT block";
10294 break;
10295 case Match_RequiresITBlock:
10296 Message.Message = "instruction only valid inside IT block";
10297 break;
10298 case Match_RequiresV6:
10299 Message.Message = "instruction variant requires ARMv6 or later";
10300 break;
10301 case Match_RequiresThumb2:
10302 Message.Message = "instruction variant requires Thumb2";
10303 break;
10304 case Match_RequiresV8:
10305 Message.Message = "instruction variant requires ARMv8 or later";
10306 break;
10307 case Match_RequiresFlagSetting:
10308 Message.Message = "no flag-preserving variant of this instruction available";
10309 break;
10310 case Match_InvalidOperand:
10311 Message.Message = "invalid operand for instruction";
10312 break;
10313 default:
10314 llvm_unreachable("Unhandled target predicate error");
10315 break;
10316 }
10317 NearMissesOut.emplace_back(Message);
10318 break;
10319 }
10320 case NearMissInfo::NearMissTooFewOperands: {
10321 SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc();
10322 NearMissesOut.emplace_back(
10323 NearMissMessage{ EndLoc, StringRef("too few operands for instruction") });
10324 break;
10325 }
10326 case NearMissInfo::NoNearMiss:
10327 // This should never leave the matcher.
10328 llvm_unreachable("not a near-miss");
10329 break;
10330 }
10331 }
10332 }
10333
10334 void ARMAsmParser::ReportNearMisses(SmallVectorImpl &NearMisses,
10335 SMLoc IDLoc, OperandVector &Operands) {
10336 SmallVector Messages;
10337 FilterNearMisses(NearMisses, Messages, IDLoc, Operands);
10338
10339 if (Messages.size() == 0) {
10340 // No near-misses were found, so the best we can do is "invalid
10341 // instruction".
10342 Error(IDLoc, "invalid instruction");
10343 } else if (Messages.size() == 1) {
10344 // One near miss was found, report it as the sole error.
10345 Error(Messages[0].Loc, Messages[0].Message);
10346 } else {
10347 // More than one near miss, so report a generic "invalid instruction"
10348 // error, followed by notes for each of the near-misses.
10349 Error(IDLoc, "invalid instruction, any one of the following would fix this:");
10350 for (auto &M : Messages) {
10351 Note(M.Loc, M.Message);
10352 }
10353 }
10354 }
10355
1020510356 // FIXME: This structure should be moved inside ARMTargetParser
1020610357 // when we start to table-generate them, and we can use the ARM
1020710358 // flags below, that were generated by table-gen.
77 bl #2
88 beq #2
99
10 @ CHECK: error: instruction requires: thumb
10 @ CHECK: error: invalid instruction, any one of the following would fix this:
1111 @ CHECK: b #2
12 @ CHECK: error: instruction requires: thumb
12 @ CHECK: note: instruction requires: thumb
13 @ CHECK: note: invalid operand for instruction
14 @ CHECK: error: invalid instruction, any one of the following would fix this:
1315 @ CHECK: bl #2
14 @ CHECK: error: instruction requires: thumb
16 @ CHECK: note: instruction requires: thumb
17 @ CHECK: note: invalid operand for instruction
18 @ CHECK: error: invalid instruction, any one of the following would fix this:
1519 @ CHECK: beq #2
20 @ CHECK: note: instruction requires: thumb
21 @ CHECK: note: invalid operand for instruction
2626 //CHECK-ERROR: error: invalid operand for instruction
2727 //CHECK-ERROR: vqrdmlsh.f64 d3, d5, d5
2828 //CHECK-ERROR: ^
29 //CHECK-V8: error: invalid operand for instruction
29 //CHECK-V8: error: invalid instruction
3030 //CHECK-V8: vqrdmlah.i8 q0, q1, q2
31 //CHECK-V8: ^
32 //CHECK-V8: error: invalid operand for instruction
31 //CHECK-V8: ^
32 //CHECK-V8: error: invalid instruction
3333 //CHECK-V8: vqrdmlah.u16 d0, d1, d2
34 //CHECK-V8: ^
35 //CHECK-V8: error: invalid operand for instruction
34 //CHECK-V8: ^
35 //CHECK-V8: error: invalid instruction
3636 //CHECK-V8: vqrdmlsh.f32 q3, q4, q5
37 //CHECK-V8: ^
38 //CHECK-V8: error: invalid operand for instruction
37 //CHECK-V8: ^
38 //CHECK-V8: error: invalid instruction
3939 //CHECK-V8: vqrdmlsh.f64 d3, d5, d5
40 //CHECK-V8: ^
40 //CHECK-V8: ^
4141
4242 vqrdmlah.s16 d0, d1, d2
4343 //CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x12,0x0b,0x11,0xf3]
9797 //CHECK-V8: ^
9898
9999
100 vqrdmlah.i8 q0, q1, d9[7]
100 vqrdmlah.i8 q0, q1, d9[0]
101 vqrdmlah.s32 q0, q1, d9[7]
101102 vqrdmlah.u16 d0, d1, d2[3]
102103 vqrdmlsh.f32 q3, q4, d5[1]
103104 vqrdmlsh.f64 d3, d5, d5[0]
104105
105106 //CHECK-ERROR: error: invalid operand for instruction
106 //CHECK-ERROR: vqrdmlah.i8 q0, q1, d9[7]
107 //CHECK-ERROR: ^
107 //CHECK-ERROR: vqrdmlah.i8 q0, q1, d9[0]
108 //CHECK-ERROR: ^
109 //CHECK-ERROR: error: invalid operand for instruction
110 //CHECK-ERROR: vqrdmlah.s32 q0, q1, d9[7]
111 //CHECK-ERROR: ^
108112 //CHECK-ERROR: error: invalid operand for instruction
109113 //CHECK-ERROR: vqrdmlah.u16 d0, d1, d2[3]
110114 //CHECK-ERROR: ^
175179 setpan #0
176180 //CHECK-V81aTHUMB: setpan #0 @ encoding: [0x10,0xb6]
177181 //CHECK-V81aARM: setpan #0 @ encoding: [0x00,0x00,0x10,0xf1]
178 //CHECK-V8: error: instruction requires: armv8.1a
182 //CHECK-V8: instruction requires: armv8.1a
179183 //CHECK-V8: setpan #0
180184 //CHECK-V8: ^
181185
182186 setpan #1
183187 //CHECK-V81aTHUMB: setpan #1 @ encoding: [0x18,0xb6]
184188 //CHECK-V81aARM: setpan #1 @ encoding: [0x00,0x02,0x10,0xf1]
185 //CHECK-V8: error: instruction requires: armv8.1a
189 //CHECK-V8: instruction requires: armv8.1a
186190 //CHECK-V8: setpan #1
187191 //CHECK-V8: ^
188192 setpan
5555 sevl
5656
5757 @ CHECK-V8: sevl @ encoding: [0x05,0xf0,0x20,0xe3]
58 @ CHECK-V7: error: instruction requires: armv8
58 @ CHECK-V7: instruction requires: armv8
3030 @ CHECK-V8: sbc.w r6, r3, sp, asr #16 @ encoding: [0x63,0xeb,0x2d,0x46]
3131 @ CHECK-V8: and.w r6, r3, sp, asr #16 @ encoding: [0x03,0xea,0x2d,0x46]
3232 @ CHECK-V8: and sp, r0, #0 @ encoding: [0x00,0xf0,0x00,0x0d]
33 @ CHECK-V7: error: instruction variant requires ARMv8 or later
34 @ CHECK-V7: error: instruction variant requires ARMv8 or later
33 @ CHECK-V7: error: invalid instruction, any one of the following would fix this:
34 @ CHECk-V7: note: instruction variant requires ARMv8 or later
35 @ CHECk-V7: note: invalid operand for instruction
36 @ CHECK-V7: error: invalid instruction, any one of the following would fix this:
37 @ CHECk-V7: note: instruction variant requires ARMv8 or later
38 @ CHECk-V7: note: invalid operand for instruction
3539 @ CHECK-V7: error: invalid operand for instruction
3640
3741 @ DCPS{1,2,3} (in ARMv8 only)
1212 @ CHECK: cps #0 @ encoding: [0xaf,0xf3,0x00,0x81]
1313
1414 @ UNDEF-DAG: cpsie f @ encoding: [0x61,0xb6]
15 @ UNDEF-DAG: error: instruction requires:
15 @ UNDEF-DAG: instruction requires:
1616 @ UNDEF-DAG: error: instruction 'cps' requires effect for M-class
9292 @ Out of range 16-bit immediate on BKPT
9393 bkpt #65536
9494
95 @ CHECK-ERRORS: error: immediate operand must be in the range [0,65535]
95 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
96 @ CHECK-ERRORS: note: immediate operand must be in the range [0,65535]
97 @ CHECK-ERRORS: note: too many operands for instruction
9698 @ CHECK-ERRORS: bkpt #65536
9799 @ CHECK-ERRORS: ^
98100
99101 @ Out of range immediates for v8 HLT instruction.
100102 hlt #65536
101103 hlt #-1
102 @CHECK-ERRORS: error: immediate operand must be in the range [0,65535]
104 @CHECK-ERRORS-V7: error: invalid instruction
105 @CHECK-ERRORS-V8: error: immediate operand must be in the range [0,65535]
103106 @CHECK-ERRORS: hlt #65536
104 @CHECK-ERRORS: ^
105 @CHECK-ERRORS: error: immediate operand must be in the range [0,65535]
107 @CHECK-ERRORS: ^
108 @CHECK-ERRORS-V7: error: invalid instruction
109 @CHECK-ERRORS-V8: error: immediate operand must be in the range [0,65535]
106110 @CHECK-ERRORS: hlt #-1
107111 @CHECK-ERRORS: ^
108112
128132 @ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,7]
129133 @ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,7]
130134 @ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,7]
131 @ CHECK-ERRORS-V8: error: invalid operand for instruction
132 @ CHECK-ERRORS-V8: error: invalid operand for instruction
133 @ CHECK-ERRORS-V8: error: invalid operand for instruction
134 @ CHECK-ERRORS-V8: error: invalid operand for instruction
135 @ CHECK-ERRORS-V8: error: invalid instruction
136 @ CHECK-ERRORS-V8: error: invalid instruction
137 @ CHECK-ERRORS-V8: error: invalid instruction
138 @ CHECK-ERRORS-V8: error: invalid instruction
135139
136140 @ Out of range immediates for DBG
137141 dbg #-1
138142 dbg #16
139143
140 @ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
141 @ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
144 @ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15]
145 @ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15]
146 @ CHECK-ERRORS-V8: error: immediate operand must be in the range [0,15]
147 @ CHECK-ERRORS-V8: error: immediate operand must be in the range [0,15]
142148 @ Double-check that we're synced up with the right diagnostics.
143149 @ CHECK-ERRORS: dbg #16
144150 @ CHECK-ERRORS: ^
150156 mcr2 p7, #1, r5, c1, c1, #8
151157 mcrr p7, #16, r5, r4, c1
152158 mcrr2 p7, #16, r5, r4, c1
153 @ CHECK-ERRORS: error: immediate operand must be in the range [0,7]
154 @ CHECK-ERRORS: error: immediate operand must be in the range [0,7]
155 @ CHECK-ERRORS: error: immediate operand must be in the range [0,7]
156 @ CHECK-ERRORS: error: immediate operand must be in the range [0,7]
157 @ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
158 @ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15]
159 @ CHECK-ERRORS-V8: error: invalid operand for instruction
159 @ CHECK-ERRORS: immediate operand must be in the range [0,7]
160 @ CHECK-ERRORS: immediate operand must be in the range [0,7]
161 @ CHECK-ERRORS-V7: immediate operand must be in the range [0,7]
162 @ CHECK-ERRORS-V7: immediate operand must be in the range [0,7]
163 @ CHECK-ERRORS-V8: invalid instruction
164 @ CHECK-ERRORS-V8: too many operands for instruction
165 @ CHECK-ERRORS: immediate operand must be in the range [0,15]
166 @ CHECK-ERRORS-V7: immediate operand must be in the range [0,15]
167 @ CHECK-ERRORS-V8: invalid instruction
160168
161169 @ p10 and p11 are reserved for NEON
162170 mcr p10, #2, r5, c1, c1, #4
173181 @ Invalid 's' bit usage for MOVW
174182 movs r6, #0xffff
175183 movwseq r9, #0xffff
176 @ CHECK-ERRORS: error: immediate operand must be in the range [0,255]
184 @ CHECK-ERRORS: error: invalid operand for instruction
177185 @ CHECK-ERRORS: error: instruction 'movw' can not set flags, but 's' suffix specified
178186
179187 @ Out of range immediate for MOVT
189197 mrc2 p14, #0, r1, c1, c2, #9
190198 mrrc p7, #16, r5, r4, c1
191199 mrrc2 p7, #17, r5, r4, c1
192 @ CHECK-ERRORS: error: immediate operand must be in the range [0,7]
193 @ CHECK-ERRORS: error: immediate operand must be in the range [0,7]
194 @ CHECK-ERRORS: error: immediate operand must be in the range [0,7]
195 @ CHECK-ERRORS: error: immediate operand must be in the range [0,7]
196 @ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
197 @ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15]
198 @ CHECK-ERRORS-V8: error: invalid operand for instruction
200 @ CHECK-ERRORS: immediate operand must be in the range [0,7]
201 @ CHECK-ERRORS: immediate operand must be in the range [0,7]
202 @ CHECK-ERRORS-V7: immediate operand must be in the range [0,7]
203 @ CHECK-ERRORS-V8: invalid instruction
204 @ CHECK-ERRORS-V7: immediate operand must be in the range [0,7]
205 @ CHECK-ERRORS-V8: too many operands for instruction
206 @ CHECK-ERRORS: immediate operand must be in the range [0,15]
207 @ CHECK-ERRORS-V7: immediate operand must be in the range [0,15]
208 @ CHECK-ERRORS-V8: invalid instruction
199209
200210 @ Shifter operand validation for PKH instructions.
201211 pkhbt r2, r2, r3, lsl #-1
417427
418428 @ Bad CPS instruction format.
419429 cps f,#1
420 @ CHECK-ERRORS: error: immediate operand must be in the range [0,31]
430 @ CHECK-ERRORS: error: invalid operand for instruction
421431 @ CHECK-ERRORS: cps f,#1
422432 @ CHECK-ERRORS: ^
423433
1616 .type fp,%function
1717 fp:
1818 vmrs r0, mvfr2
19 @ CHECK-V7: error: instruction requires: FPARMv8
19 @ CHECK-V7: instruction requires: FPARMv8
2020
2121 vselgt.f32 s0, s0, s0
22 @ CHECK-V7: error: instruction requires: FPARMv8
22 @ CHECK-V7: instruction requires: FPARMv8
2323 vselge.f32 s0, s0, s0
24 @ CHECK-V7: error: instruction requires: FPARMv8
24 @ CHECK-V7: instruction requires: FPARMv8
2525 vseleq.f32 s0, s0, s0
26 @ CHECK-V7: error: instruction requires: FPARMv8
26 @ CHECK-V7: instruction requires: FPARMv8
2727 vselvs.f32 s0, s0, s0
28 @ CHECK-V7: error: instruction requires: FPARMv8
28 @ CHECK-V7: instruction requires: FPARMv8
2929 vmaxnm.f32 s0, s0, s0
30 @ CHECK-V7: error: instruction requires: FPARMv8
30 @ CHECK-V7: instruction requires: FPARMv8
3131 vminnm.f32 s0, s0, s0
32 @ CHECK-V7: error: instruction requires: FPARMv8
32 @ CHECK-V7: instruction requires: FPARMv8
3333
3434 vselgt.f64 d0, d0, d0
35 @ CHECK-V7: error: instruction requires: FPARMv8
35 @ CHECK-V7: instruction requires: FPARMv8
3636 vselge.f64 d0, d0, d0
37 @ CHECK-V7: error: instruction requires: FPARMv8
37 @ CHECK-V7: instruction requires: FPARMv8
3838 vseleq.f64 d0, d0, d0
39 @ CHECK-V7: error: instruction requires: FPARMv8
39 @ CHECK-V7: instruction requires: FPARMv8
4040 vselvs.f64 d0, d0, d0
41 @ CHECK-V7: error: instruction requires: FPARMv8
41 @ CHECK-V7: instruction requires: FPARMv8
4242 vmaxnm.f64 d0, d0, d0
43 @ CHECK-V7: error: instruction requires: FPARMv8
43 @ CHECK-V7: instruction requires: FPARMv8
4444 vminnm.f64 d0, d0, d0
45 @ CHECK-V7: error: instruction requires: FPARMv8
45 @ CHECK-V7: instruction requires: FPARMv8
4646
4747 vcvtb.f64.f16 d0, s0
48 @ CHECK-V7: error: instruction requires: FPARMv8
48 @ CHECK-V7: instruction requires: FPARMv8
4949 vcvtb.f16.f64 s0, d0
50 @ CHECK-V7: error: instruction requires: FPARMv8
50 @ CHECK-V7: instruction requires: FPARMv8
5151 vcvtt.f64.f16 d0, s0
52 @ CHECK-V7: error: instruction requires: FPARMv8
52 @ CHECK-V7: instruction requires: FPARMv8
5353 vcvtt.f16.f64 s0, d0
54 @ CHECK-V7: error: instruction requires: FPARMv8
54 @ CHECK-V7: instruction requires: FPARMv8
5555
5656 vcvta.s32.f32 s0, s0
57 @ CHECK-V7: error: instruction requires: FPARMv8
57 @ CHECK-V7: instruction requires: FPARMv8
5858 vcvta.u32.f32 s0, s0
59 @ CHECK-V7: error: instruction requires: FPARMv8
59 @ CHECK-V7: instruction requires: FPARMv8
6060 vcvta.s32.f64 s0, d0
61 @ CHECK-V7: error: instruction requires: FPARMv8
61 @ CHECK-V7: instruction requires: FPARMv8
6262 vcvta.u32.f64 s0, d0
63 @ CHECK-V7: error: instruction requires: FPARMv8
63 @ CHECK-V7: instruction requires: FPARMv8
6464 vcvtn.s32.f32 s0, s0
65 @ CHECK-V7: error: instruction requires: FPARMv8
65 @ CHECK-V7: instruction requires: FPARMv8
6666 vcvtn.u32.f32 s0, s0
67 @ CHECK-V7: error: instruction requires: FPARMv8
67 @ CHECK-V7: instruction requires: FPARMv8
6868 vcvtn.s32.f64 s0, d0
69 @ CHECK-V7: error: instruction requires: FPARMv8
69 @ CHECK-V7: instruction requires: FPARMv8
7070 vcvtn.u32.f64 s0, d0
71 @ CHECK-V7: error: instruction requires: FPARMv8
71 @ CHECK-V7: instruction requires: FPARMv8
7272 vcvtp.s32.f32 s0, s0
73 @ CHECK-V7: error: instruction requires: FPARMv8
73 @ CHECK-V7: instruction requires: FPARMv8
7474 vcvtp.u32.f32 s0, s0
75 @ CHECK-V7: error: instruction requires: FPARMv8
75 @ CHECK-V7: instruction requires: FPARMv8
7676 vcvtp.s32.f64 s0, d0
77 @ CHECK-V7: error: instruction requires: FPARMv8
77 @ CHECK-V7: instruction requires: FPARMv8
7878 vcvtp.u32.f64 s0, d0
79 @ CHECK-V7: error: instruction requires: FPARMv8
79 @ CHECK-V7: instruction requires: FPARMv8
8080 vcvtm.s32.f32 s0, s0
81 @ CHECK-V7: error: instruction requires: FPARMv8
81 @ CHECK-V7: instruction requires: FPARMv8
8282 vcvtm.u32.f32 s0, s0
83 @ CHECK-V7: error: instruction requires: FPARMv8
83 @ CHECK-V7: instruction requires: FPARMv8
8484 vcvtm.s32.f64 s0, d0
85 @ CHECK-V7: error: instruction requires: FPARMv8
85 @ CHECK-V7: instruction requires: FPARMv8
8686 vcvtm.u32.f64 s0, d0
87 @ CHECK-V7: error: instruction requires: FPARMv8
87 @ CHECK-V7: instruction requires: FPARMv8
8888
8989 vrintz.f32 s0, s1
90 @ CHECK-V7: error: instruction requires: FPARMv8
90 @ CHECK-V7: instruction requires: FPARMv8
9191 vrintz.f64 d0, d1
92 @ CHECK-V7: error: instruction requires: FPARMv8
92 @ CHECK-V7: instruction requires: FPARMv8
9393 vrintz.f32.f32 s0, s0
94 @ CHECK-V7: error: instruction requires: FPARMv8
94 @ CHECK-V7: instruction requires: FPARMv8
9595 vrintz.f64.f64 d0, d0
96 @ CHECK-V7: error: instruction requires: FPARMv8
96 @ CHECK-V7: instruction requires: FPARMv8
9797 vrintr.f32 s0, s1
98 @ CHECK-V7: error: instruction requires: FPARMv8
98 @ CHECK-V7: instruction requires: FPARMv8
9999 vrintr.f64 d0, d1
100 @ CHECK-V7: error: instruction requires: FPARMv8
100 @ CHECK-V7: instruction requires: FPARMv8
101101 vrintr.f32.f32 s0, s0
102 @ CHECK-V7: error: instruction requires: FPARMv8
102 @ CHECK-V7: instruction requires: FPARMv8
103103 vrintr.f64.f64 d0, d0
104 @ CHECK-V7: error: instruction requires: FPARMv8
104 @ CHECK-V7: instruction requires: FPARMv8
105105 vrintx.f32 s0, s1
106 @ CHECK-V7: error: instruction requires: FPARMv8
106 @ CHECK-V7: instruction requires: FPARMv8
107107 vrintx.f64 d0, d1
108 @ CHECK-V7: error: instruction requires: FPARMv8
108 @ CHECK-V7: instruction requires: FPARMv8
109109 vrintx.f32.f32 s0, s0
110 @ CHECK-V7: error: instruction requires: FPARMv8
110 @ CHECK-V7: instruction requires: FPARMv8
111111 vrintx.f64.f64 d0, d0
112 @ CHECK-V7: error: instruction requires: FPARMv8
112 @ CHECK-V7: instruction requires: FPARMv8
113113
114114 vrinta.f32 s0, s0
115 @ CHECK-V7: error: instruction requires: FPARMv8
115 @ CHECK-V7: instruction requires: FPARMv8
116116 vrinta.f64 d0, d0
117 @ CHECK-V7: error: instruction requires: FPARMv8
117 @ CHECK-V7: instruction requires: FPARMv8
118118 vrinta.f32.f32 s0, s0
119 @ CHECK-V7: error: instruction requires: FPARMv8
119 @ CHECK-V7: instruction requires: FPARMv8
120120 vrinta.f64.f64 d0, d0
121 @ CHECK-V7: error: instruction requires: FPARMv8
121 @ CHECK-V7: instruction requires: FPARMv8
122122 vrintn.f32 s0, s0
123 @ CHECK-V7: error: instruction requires: FPARMv8
123 @ CHECK-V7: instruction requires: FPARMv8
124124 vrintn.f64 d0, d0
125 @ CHECK-V7: error: instruction requires: FPARMv8
125 @ CHECK-V7: instruction requires: FPARMv8
126126 vrintn.f32.f32 s0, s0
127 @ CHECK-V7: error: instruction requires: FPARMv8
127 @ CHECK-V7: instruction requires: FPARMv8
128128 vrintn.f64.f64 d0, d0
129 @ CHECK-V7: error: instruction requires: FPARMv8
129 @ CHECK-V7: instruction requires: FPARMv8
130130 vrintp.f32 s0, s0
131 @ CHECK-V7: error: instruction requires: FPARMv8
131 @ CHECK-V7: instruction requires: FPARMv8
132132 vrintp.f64 d0, d0
133 @ CHECK-V7: error: instruction requires: FPARMv8
133 @ CHECK-V7: instruction requires: FPARMv8
134134 vrintp.f32.f32 s0, s0
135 @ CHECK-V7: error: instruction requires: FPARMv8
135 @ CHECK-V7: instruction requires: FPARMv8
136136 vrintp.f64.f64 d0, d0
137 @ CHECK-V7: error: instruction requires: FPARMv8
137 @ CHECK-V7: instruction requires: FPARMv8
138138 vrintm.f32 s0, s0
139 @ CHECK-V7: error: instruction requires: FPARMv8
139 @ CHECK-V7: instruction requires: FPARMv8
140140 vrintm.f64 d0, d0
141 @ CHECK-V7: error: instruction requires: FPARMv8
141 @ CHECK-V7: instruction requires: FPARMv8
142142 vrintm.f32.f32 s0, s0
143 @ CHECK-V7: error: instruction requires: FPARMv8
143 @ CHECK-V7: instruction requires: FPARMv8
144144 vrintm.f64.f64 d0, d0
145 @ CHECK-V7: error: instruction requires: FPARMv8
145 @ CHECK-V7: instruction requires: FPARMv8
146146
147147 .arch_extension nofp
148148 @ CHECK-V7: error: architectural extension 'fp' is not allowed for the current base architecture
152152 .type nofp,%function
153153 nofp:
154154 vmrs r0, mvfr2
155 @ CHECK: error: instruction requires: FPARMv8
155 @ CHECK: instruction requires: FPARMv8
156156
157157 vselgt.f32 s0, s0, s0
158 @ CHECK: error: instruction requires: FPARMv8
158 @ CHECK: instruction requires: FPARMv8
159159 vselge.f32 s0, s0, s0
160 @ CHECK: error: instruction requires: FPARMv8
160 @ CHECK: instruction requires: FPARMv8
161161 vseleq.f32 s0, s0, s0
162 @ CHECK: error: instruction requires: FPARMv8
162 @ CHECK: instruction requires: FPARMv8
163163 vselvs.f32 s0, s0, s0
164 @ CHECK: error: instruction requires: FPARMv8
164 @ CHECK: instruction requires: FPARMv8
165165 vmaxnm.f32 s0, s0, s0
166 @ CHECK: error: instruction requires: FPARMv8
166 @ CHECK: instruction requires: FPARMv8
167167 vminnm.f32 s0, s0, s0
168 @ CHECK: error: instruction requires: FPARMv8
168 @ CHECK: instruction requires: FPARMv8
169169
170170 vselgt.f64 d0, d0, d0
171 @ CHECK: error: instruction requires: FPARMv8
171 @ CHECK: instruction requires: FPARMv8
172172 vselge.f64 d0, d0, d0
173 @ CHECK: error: instruction requires: FPARMv8
173 @ CHECK: instruction requires: FPARMv8
174174 vseleq.f64 d0, d0, d0
175 @ CHECK: error: instruction requires: FPARMv8
175 @ CHECK: instruction requires: FPARMv8
176176 vselvs.f64 d0, d0, d0
177 @ CHECK: error: instruction requires: FPARMv8
177 @ CHECK: instruction requires: FPARMv8
178178 vmaxnm.f64 d0, d0, d0
179 @ CHECK: error: instruction requires: FPARMv8
179 @ CHECK: instruction requires: FPARMv8
180180 vminnm.f64 d0, d0, d0
181 @ CHECK: error: instruction requires: FPARMv8
181 @ CHECK: instruction requires: FPARMv8
182182
183183 vcvtb.f64.f16 d0, s0
184 @ CHECK: error: instruction requires: FPARMv8
184 @ CHECK: instruction requires: FPARMv8
185185 vcvtb.f16.f64 s0, d0
186 @ CHECK: error: instruction requires: FPARMv8
186 @ CHECK: instruction requires: FPARMv8
187187 vcvtt.f64.f16 d0, s0
188 @ CHECK: error: instruction requires: FPARMv8
188 @ CHECK: instruction requires: FPARMv8
189189 vcvtt.f16.f64 s0, d0
190 @ CHECK: error: instruction requires: FPARMv8
190 @ CHECK: instruction requires: FPARMv8
191191
192192 vcvta.s32.f32 s0, s0
193 @ CHECK: error: instruction requires: FPARMv8
193 @ CHECK: instruction requires: FPARMv8
194194 vcvta.u32.f32 s0, s0
195 @ CHECK: error: instruction requires: FPARMv8
195 @ CHECK: instruction requires: FPARMv8
196196 vcvta.s32.f64 s0, d0
197 @ CHECK: error: instruction requires: FPARMv8
197 @ CHECK: instruction requires: FPARMv8
198198 vcvta.u32.f64 s0, d0
199 @ CHECK: error: instruction requires: FPARMv8
199 @ CHECK: instruction requires: FPARMv8
200200 vcvtn.s32.f32 s0, s0
201 @ CHECK: error: instruction requires: FPARMv8
201 @ CHECK: instruction requires: FPARMv8
202202 vcvtn.u32.f32 s0, s0
203 @ CHECK: error: instruction requires: FPARMv8
203 @ CHECK: instruction requires: FPARMv8
204204 vcvtn.s32.f64 s0, d0
205 @ CHECK: error: instruction requires: FPARMv8
205 @ CHECK: instruction requires: FPARMv8
206206 vcvtn.u32.f64 s0, d0
207 @ CHECK: error: instruction requires: FPARMv8
207 @ CHECK: instruction requires: FPARMv8
208208 vcvtp.s32.f32 s0, s0
209 @ CHECK: error: instruction requires: FPARMv8
209 @ CHECK: instruction requires: FPARMv8
210210 vcvtp.u32.f32 s0, s0
211 @ CHECK: error: instruction requires: FPARMv8
211 @ CHECK: instruction requires: FPARMv8
212212 vcvtp.s32.f64 s0, d0
213 @ CHECK: error: instruction requires: FPARMv8
213 @ CHECK: instruction requires: FPARMv8
214214 vcvtp.u32.f64 s0, d0
215 @ CHECK: error: instruction requires: FPARMv8
215 @ CHECK: instruction requires: FPARMv8
216216 vcvtm.s32.f32 s0, s0
217 @ CHECK: error: instruction requires: FPARMv8
217 @ CHECK: instruction requires: FPARMv8
218218 vcvtm.u32.f32 s0, s0
219 @ CHECK: error: instruction requires: FPARMv8
219 @ CHECK: instruction requires: FPARMv8
220220 vcvtm.s32.f64 s0, d0
221 @ CHECK: error: instruction requires: FPARMv8
221 @ CHECK: instruction requires: FPARMv8
222222 vcvtm.u32.f64 s0, d0
223 @ CHECK: error: instruction requires: FPARMv8
223 @ CHECK: instruction requires: FPARMv8
224224
225225 vrintz.f32 s0, s1
226 @ CHECK: error: instruction requires: FPARMv8
226 @ CHECK: instruction requires: FPARMv8
227227 vrintz.f64 d0, d1
228 @ CHECK: error: instruction requires: FPARMv8
228 @ CHECK: instruction requires: FPARMv8
229229 vrintz.f32.f32 s0, s0
230 @ CHECK: error: instruction requires: FPARMv8
230 @ CHECK: instruction requires: FPARMv8
231231 vrintz.f64.f64 d0, d0
232 @ CHECK: error: instruction requires: FPARMv8
232 @ CHECK: instruction requires: FPARMv8
233233 vrintr.f32 s0, s1
234 @ CHECK: error: instruction requires: FPARMv8
234 @ CHECK: instruction requires: FPARMv8
235235 vrintr.f64 d0, d1
236 @ CHECK: error: instruction requires: FPARMv8
236 @ CHECK: instruction requires: FPARMv8
237237 vrintr.f32.f32 s0, s0
238 @ CHECK: error: instruction requires: FPARMv8
238 @ CHECK: instruction requires: FPARMv8
239239 vrintr.f64.f64 d0, d0
240 @ CHECK: error: instruction requires: FPARMv8
240 @ CHECK: instruction requires: FPARMv8
241241 vrintx.f32 s0, s1
242 @ CHECK: error: instruction requires: FPARMv8
242 @ CHECK: instruction requires: FPARMv8
243243 vrintx.f64 d0, d1
244 @ CHECK: error: instruction requires: FPARMv8
244 @ CHECK: instruction requires: FPARMv8
245245 vrintx.f32.f32 s0, s0
246 @ CHECK: error: instruction requires: FPARMv8
246 @ CHECK: instruction requires: FPARMv8
247247 vrintx.f64.f64 d0, d0
248 @ CHECK: error: instruction requires: FPARMv8
248 @ CHECK: instruction requires: FPARMv8
249249
250250 vrinta.f32 s0, s0
251 @ CHECK: error: instruction requires: FPARMv8
251 @ CHECK: instruction requires: FPARMv8
252252 vrinta.f64 d0, d0
253 @ CHECK: error: instruction requires: FPARMv8
253 @ CHECK: instruction requires: FPARMv8
254254 vrinta.f32.f32 s0, s0
255 @ CHECK: error: instruction requires: FPARMv8
255 @ CHECK: instruction requires: FPARMv8
256256 vrinta.f64.f64 d0, d0
257 @ CHECK: error: instruction requires: FPARMv8
257 @ CHECK: instruction requires: FPARMv8
258258 vrintn.f32 s0, s0
259 @ CHECK: error: instruction requires: FPARMv8
259 @ CHECK: instruction requires: FPARMv8
260260 vrintn.f64 d0, d0
261 @ CHECK: error: instruction requires: FPARMv8
261 @ CHECK: instruction requires: FPARMv8
262262 vrintn.f32.f32 s0, s0
263 @ CHECK: error: instruction requires: FPARMv8
263 @ CHECK: instruction requires: FPARMv8
264264 vrintn.f64.f64 d0, d0
265 @ CHECK: error: instruction requires: FPARMv8
265 @ CHECK: instruction requires: FPARMv8
266266 vrintp.f32 s0, s0
267 @ CHECK: error: instruction requires: FPARMv8
267 @ CHECK: instruction requires: FPARMv8
268268 vrintp.f64 d0, d0
269 @ CHECK: error: instruction requires: FPARMv8
269 @ CHECK: instruction requires: FPARMv8
270270 vrintp.f32.f32 s0, s0
271 @ CHECK: error: instruction requires: FPARMv8
271 @ CHECK: instruction requires: FPARMv8
272272 vrintp.f64.f64 d0, d0
273 @ CHECK: error: instruction requires: FPARMv8
273 @ CHECK: instruction requires: FPARMv8
274274 vrintm.f32 s0, s0
275 @ CHECK: error: instruction requires: FPARMv8
275 @ CHECK: instruction requires: FPARMv8
276276 vrintm.f64 d0, d0
277 @ CHECK: error: instruction requires: FPARMv8
277 @ CHECK: instruction requires: FPARMv8
278278 vrintm.f32.f32 s0, s0
279 @ CHECK: error: instruction requires: FPARMv8
279 @ CHECK: instruction requires: FPARMv8
280280 vrintm.f64.f64 d0, d0
281 @ CHECK: error: instruction requires: FPARMv8
282
281 @ CHECK: instruction requires: FPARMv8
282
2424 idiv:
2525 udiv r0, r1, r2
2626 @ CHECK-ARMv6: error: instruction requires: divide in ARM
27 @ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode
27 @ CHECK-THUMBv6: error: instruction requires: divide in THUMB armv8m.base
2828 sdiv r0, r1, r2
2929 @ CHECK-ARMv6: error: instruction requires: divide in ARM
30 @ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode
30 @ CHECK-THUMBv6: error: instruction requires: divide in THUMB armv8m.base
3131
3232 .arch_extension noidiv
3333 @ CHECK-V6: error: architectural extension 'idiv' is not allowed for the current base architecture
4141 noidiv:
4242 udiv r0, r1, r2
4343 @ CHECK-ARMv6: error: instruction requires: divide in ARM
44 @ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode
44 @ CHECK-THUMBv6: error: instruction requires: divide in THUMB armv8m.base
4545 @ CHECK-ARMv7: error: instruction requires: divide in ARM
4646 @ CHECK-THUMBv7: error: instruction requires: divide in THUMB
4747 sdiv r0, r1, r2
4848 @ CHECK-ARMv6: error: instruction requires: divide in ARM
49 @ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode
49 @ CHECK-THUMBv6: error: instruction requires: divide in THUMB armv8m.base
5050 @ CHECK-ARMv7: error: instruction requires: divide in ARM
5151 @ CHECK-THUMBv7: error: instruction requires: divide in THUMB
5252
11
22 @ Test for floating point constants that are out of the 8-bit encoded value range
33 vmov.f32 s2, #32.0
4 @ CHECK: error: invalid operand for instruction
4 @ CHECK: invalid operand for instruction
55
66 vmov.f64 d2, #32.0
7 @ CHECK: error: invalid operand for instruction
7 @ CHECK: invalid operand for instruction
88
99 @ Test that vmov.f instructions do not accept an 8-bit encoded float as an operand
1010 vmov.f32 s1, #0x70
2121 @ CHECK: error: invalid floating point immediate
2222
2323 vmov.i64 d0, 0x8000000000000000
24 @ CHECK: error: invalid operand for instruction
24 @ CHECK: invalid operand for instruction
11 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+thumb-mode -show-encoding < %s 2>&1 | FileCheck %s
22
33 vadd.f16 s0, s1, s0
4 @ CHECK: error: instruction requires:
4 @ CHECK: instruction requires: full half-float
55
66 vsub.f16 s0, s1, s0
7 @ CHECK: error: instruction requires:
7 @ CHECK: instruction requires: full half-float
88
99 vdiv.f16 s0, s1, s0
10 @ CHECK: error: instruction requires:
10 @ CHECK: instruction requires: full half-float
1111
1212 vmul.f16 s0, s1, s0
13 @ CHECK: error: instruction requires:
13 @ CHECK: instruction requires: full half-float
1414
1515 vnmul.f16 s0, s1, s0
16 @ CHECK: error: instruction requires:
16 @ CHECK: instruction requires: full half-float
1717
1818 vmla.f16 s1, s2, s0
19 @ CHECK: error: instruction requires:
19 @ CHECK: instruction requires: full half-float
2020
2121 vmls.f16 s1, s2, s0
22 @ CHECK: error: instruction requires:
22 @ CHECK: instruction requires: full half-float
2323
2424 vnmla.f16 s1, s2, s0
25 @ CHECK: error: instruction requires:
25 @ CHECK: instruction requires: full half-float
2626
2727 vnmls.f16 s1, s2, s0
28 @ CHECK: error: instruction requires:
28 @ CHECK: instruction requires: full half-float
2929
3030 vcmp.f16 s0, s1
31 @ CHECK: error: instruction requires:
31 @ CHECK: instruction requires: full half-float
3232
3333 vcmp.f16 s2, #0
34 @ CHECK: error: instruction requires:
34 @ CHECK: instruction requires: full half-float
3535
3636 vcmpe.f16 s1, s0
37 @ CHECK: error: instruction requires:
37 @ CHECK: instruction requires: full half-float
3838
3939 vcmpe.f16 s0, #0
40 @ CHECK: error: instruction requires:
40 @ CHECK: instruction requires: full half-float
4141
4242 vabs.f16 s0, s0
43 @ CHECK: error: instruction requires:
43 @ CHECK: instruction requires: full half-float
4444
4545 vneg.f16 s0, s0
46 @ CHECK: error: instruction requires:
46 @ CHECK: instruction requires: full half-float
4747
4848 vsqrt.f16 s0, s0
49 @ CHECK: error: instruction requires:
49 @ CHECK: instruction requires: full half-float
5050
5151 vcvt.f16.s32 s0, s0
5252 vcvt.f16.u32 s0, s0
5353 vcvt.s32.f16 s0, s0
5454 vcvt.u32.f16 s0, s0
55 @ CHECK: error: instruction requires:
56 @ CHECK: error: instruction requires:
57 @ CHECK: error: instruction requires:
58 @ CHECK: error: instruction requires:
55 @ CHECK: instruction requires: full half-float
56 @ CHECK: instruction requires: full half-float
57 @ CHECK: instruction requires: full half-float
58 @ CHECK: instruction requires: full half-float
5959
6060 vcvtr.s32.f16 s0, s1
6161 vcvtr.u32.f16 s0, s1
62 @ CHECK: error: instruction requires:
63 @ CHECK: error: instruction requires:
62 @ CHECK: instruction requires: full half-float
63 @ CHECK: instruction requires: full half-float
6464
6565 vcvt.f16.u32 s0, s0, #20
6666 vcvt.f16.u16 s0, s0, #1
7070 vcvt.u16.f16 s28, s28, #1
7171 vcvt.s32.f16 s1, s1, #20
7272 vcvt.s16.f16 s17, s17, #1
73 @ CHECK: error: instruction requires:
74 @ CHECK: error: instruction requires:
75 @ CHECK: error: instruction requires:
76 @ CHECK: error: instruction requires:
77 @ CHECK: error: instruction requires:
78 @ CHECK: error: instruction requires:
79 @ CHECK: error: instruction requires:
80 @ CHECK: error: instruction requires:
73 @ CHECK: instruction requires: full half-float
74 @ CHECK: instruction requires: full half-float
75 @ CHECK: instruction requires: full half-float
76 @ CHECK: instruction requires: full half-float
77 @ CHECK: instruction requires: full half-float
78 @ CHECK: instruction requires: full half-float
79 @ CHECK: instruction requires: full half-float
80 @ CHECK: instruction requires: full half-float
8181
8282 vcvta.s32.f16 s2, s3
83 @ CHECK: error: instruction requires:
83 @ CHECK: instruction requires: full half-float
8484
8585 vcvtn.s32.f16 s6, s23
86 @ CHECK: error: instruction requires:
86 @ CHECK: instruction requires: full half-float
8787
8888 vcvtp.s32.f16 s0, s4
89 @ CHECK: error: instruction requires:
89 @ CHECK: instruction requires: full half-float
9090
9191 vcvtm.s32.f16 s17, s8
92 @ CHECK: error: instruction requires:
92 @ CHECK: instruction requires: full half-float
9393
9494 vcvta.u32.f16 s2, s3
95 @ CHECK: error: instruction requires:
95 @ CHECK: instruction requires: full half-float
9696
9797 vcvtn.u32.f16 s6, s23
98 @ CHECK: error: instruction requires:
98 @ CHECK: instruction requires: full half-float
9999
100100 vcvtp.u32.f16 s0, s4
101 @ CHECK: error: instruction requires:
101 @ CHECK: instruction requires: full half-float
102102
103103 vcvtm.u32.f16 s17, s8
104 @ CHECK: error: instruction requires:
104 @ CHECK: instruction requires: full half-float
105105
106106 vselge.f16 s4, s1, s23
107 @ CHECK: error: instruction requires:
107 @ CHECK: instruction requires: full half-float
108108
109109 vselgt.f16 s0, s1, s0
110 @ CHECK: error: instruction requires:
110 @ CHECK: instruction requires: full half-float
111111
112112 vseleq.f16 s30, s28, s23
113 @ CHECK: error: instruction requires:
113 @ CHECK: instruction requires: full half-float
114114
115115 vselvs.f16 s21, s16, s14
116 @ CHECK: error: instruction requires:
116 @ CHECK: instruction requires: full half-float
117117
118118 vmaxnm.f16 s5, s12, s0
119 @ CHECK: error: instruction requires:
119 @ CHECK: instruction requires: full half-float
120120
121121 vminnm.f16 s0, s0, s12
122 @ CHECK: error: instruction requires:
122 @ CHECK: instruction requires: full half-float
123123
124124 vrintz.f16 s3, s24
125 @ CHECK: error: instruction requires:
125 @ CHECK: instruction requires: full half-float
126126
127127 vrintr.f16 s0, s9
128 @ CHECK: error: instruction requires:
128 @ CHECK: instruction requires: full half-float
129129
130130 vrintx.f16 s10, s14
131 @ CHECK: error: instruction requires:
131 @ CHECK: instruction requires: full half-float
132132
133133 vrinta.f16 s12, s1
134 @ CHECK: error: instruction requires:
134 @ CHECK: instruction requires: full half-float
135135
136136 vrintn.f16 s12, s1
137 @ CHECK: error: instruction requires:
137 @ CHECK: instruction requires: full half-float
138138
139139 vrintp.f16 s12, s1
140 @ CHECK: error: instruction requires:
140 @ CHECK: instruction requires: full half-float
141141
142142 vrintm.f16 s12, s1
143 @ CHECK: error: instruction requires:
143 @ CHECK: instruction requires: full half-float
144144
145145 vfma.f16 s2, s7, s4
146 @ CHECK: error: instruction requires:
146 @ CHECK: instruction requires: full half-float
147147
148148 vfms.f16 s2, s7, s4
149 @ CHECK: error: instruction requires:
149 @ CHECK: instruction requires: full half-float
150150
151151 vfnma.f16 s2, s7, s4
152 @ CHECK: error: instruction requires:
152 @ CHECK: instruction requires: full half-float
153153
154154 vfnms.f16 s2, s7, s4
155 @ CHECK: error: instruction requires:
155 @ CHECK: instruction requires: full half-float
156156
157157 vmovx.f16 s2, s5
158158 vins.f16 s2, s5
159 @ CHECK: error: instruction requires:
160 @ CHECK: error: instruction requires:
159 @ CHECK: instruction requires: full half-float
160 @ CHECK: instruction requires: full half-float
161161
162162
163163 vldr.16 s1, [pc, #6]
164164 vldr.16 s2, [pc, #510]
165165 vldr.16 s3, [pc, #-510]
166166 vldr.16 s4, [r4, #-18]
167 @ CHECK: error: instruction requires:
168 @ CHECK: error: instruction requires:
169 @ CHECK: error: instruction requires:
170 @ CHECK: error: instruction requires:
167 @ CHECK: instruction requires: full half-float
168 @ CHECK: instruction requires: full half-float
169 @ CHECK: instruction requires: full half-float
170 @ CHECK: instruction requires: full half-float
171171
172172
173173 vstr.16 s1, [pc, #6]
174174 vstr.16 s2, [pc, #510]
175175 vstr.16 s3, [pc, #-510]
176176 vstr.16 s4, [r4, #-18]
177 @ CHECK: error: instruction requires:
178 @ CHECK: error: instruction requires:
179 @ CHECK: error: instruction requires:
180 @ CHECK: error: instruction requires:
177 @ CHECK: instruction requires: full half-float
178 @ CHECK: instruction requires: full half-float
179 @ CHECK: instruction requires: full half-float
180 @ CHECK: instruction requires: full half-float
181181
182182 vmov.f16 s0, #1.0
183 @ CHECK: error: instruction requires:
183 @ CHECK: instruction requires: full half-float
184184
185185 vmov.f16 s1, r2
186186 vmov.f16 r3, s4
187 @ CHECK: error: instruction requires:
188 @ CHECK: error: instruction requires:
187 @ CHECK: instruction requires: full half-float
188 @ CHECK: instruction requires: full half-float
44
55 vadd.f16 d0, d1, d2
66 vadd.f16 q0, q1, q2
7 @ CHECK: error: instruction requires:
8 @ CHECK: error: instruction requires:
7 @ CHECK: instruction requires: {{full half-float|NEON}}
8 @ CHECK: instruction requires: {{full half-float|NEON}}
99
1010 vsub.f16 d0, d1, d2
1111 vsub.f16 q0, q1, q2
12 @ CHECK: error: instruction requires:
13 @ CHECK: error: instruction requires:
12 @ CHECK: instruction requires: {{full half-float|NEON}}
13 @ CHECK: instruction requires: {{full half-float|NEON}}
1414
1515 vmul.f16 d0, d1, d2
1616 vmul.f16 q0, q1, q2
17 @ CHECK: error: instruction requires:
18 @ CHECK: error: instruction requires:
17 @ CHECK: instruction requires: {{full half-float|NEON}}
18 @ CHECK: instruction requires: {{full half-float|NEON}}
1919
2020 vmul.f16 d1, d2, d3[2]
2121 vmul.f16 q4, q5, d6[3]
22 @ CHECK: error: instruction requires:
23 @ CHECK: error: instruction requires:
22 @ CHECK: instruction requires: {{full half-float|NEON}}
23 @ CHECK: instruction requires: {{full half-float|NEON}}
2424
2525 vmla.f16 d0, d1, d2
2626 vmla.f16 q0, q1, q2
27 @ CHECK: error: instruction requires:
28 @ CHECK: error: instruction requires:
27 @ CHECK: instruction requires: {{full half-float|NEON}}
28 @ CHECK: instruction requires: {{full half-float|NEON}}
2929
3030 vmla.f16 d5, d6, d7[2]
3131 vmla.f16 q5, q6, d7[3]
32 @ CHECK: error: instruction requires:
33 @ CHECK: error: instruction requires:
32 @ CHECK: instruction requires: {{full half-float|NEON}}
33 @ CHECK: instruction requires: {{full half-float|NEON}}
3434
3535 vmls.f16 d0, d1, d2
3636 vmls.f16 q0, q1, q2
37 @ CHECK: error: instruction requires:
38 @ CHECK: error: instruction requires:
37 @ CHECK: instruction requires: {{full half-float|NEON}}
38 @ CHECK: instruction requires: {{full half-float|NEON}}
3939
4040 vmls.f16 d5, d6, d7[2]
4141 vmls.f16 q5, q6, d7[3]
42 @ CHECK: error: instruction requires:
43 @ CHECK: error: instruction requires:
42 @ CHECK: instruction requires: {{full half-float|NEON}}
43 @ CHECK: instruction requires: {{full half-float|NEON}}
4444
4545 vfma.f16 d0, d1, d2
4646 vfma.f16 q0, q1, q2
47 @ CHECK: error: instruction requires:
48 @ CHECK: error: instruction requires:
47 @ CHECK: instruction requires: {{full half-float|NEON}}
48 @ CHECK: instruction requires: {{full half-float|NEON}}
4949
5050 vfms.f16 d0, d1, d2
5151 vfms.f16 q0, q1, q2
52 @ CHECK: error: instruction requires:
53 @ CHECK: error: instruction requires:
52 @ CHECK: instruction requires: {{full half-float|NEON}}
53 @ CHECK: instruction requires: {{full half-float|NEON}}
5454
5555 vceq.f16 d2, d3, d4
5656 vceq.f16 q2, q3, q4
57 @ CHECK: error: instruction requires:
58 @ CHECK: error: instruction requires:
57 @ CHECK: instruction requires: {{full half-float|NEON}}
58 @ CHECK: instruction requires: {{full half-float|NEON}}
5959
6060 vceq.f16 d2, d3, #0
6161 vceq.f16 q2, q3, #0
62 @ CHECK: error: instruction requires:
63 @ CHECK: error: instruction requires:
62 @ CHECK: instruction requires: {{full half-float|NEON}}
63 @ CHECK: instruction requires: {{full half-float|NEON}}
6464
6565 vcge.f16 d2, d3, d4
6666 vcge.f16 q2, q3, q4
67 @ CHECK: error: instruction requires:
68 @ CHECK: error: instruction requires:
67 @ CHECK: instruction requires: {{full half-float|NEON}}
68 @ CHECK: instruction requires: {{full half-float|NEON}}
6969
7070 vcge.f16 d2, d3, #0
7171 vcge.f16 q2, q3, #0
72 @ CHECK: error: instruction requires:
73 @ CHECK: error: instruction requires:
72 @ CHECK: instruction requires: {{full half-float|NEON}}
73 @ CHECK: instruction requires: {{full half-float|NEON}}
7474
7575 vcgt.f16 d2, d3, d4
7676 vcgt.f16 q2, q3, q4
77 @ CHECK: error: instruction requires:
78 @ CHECK: error: instruction requires:
77 @ CHECK: instruction requires: {{full half-float|NEON}}
78 @ CHECK: instruction requires: {{full half-float|NEON}}
7979
8080 vcgt.f16 d2, d3, #0
8181 vcgt.f16 q2, q3, #0
82 @ CHECK: error: instruction requires:
83 @ CHECK: error: instruction requires:
82 @ CHECK: instruction requires: {{full half-float|NEON}}
83 @ CHECK: instruction requires: {{full half-float|NEON}}
8484
8585 vcle.f16 d2, d3, d4
8686 vcle.f16 q2, q3, q4
87 @ CHECK: error: instruction requires:
88 @ CHECK: error: instruction requires:
87 @ CHECK: instruction requires: {{full half-float|NEON}}
88 @ CHECK: instruction requires: {{full half-float|NEON}}
8989
9090 vcle.f16 d2, d3, #0
9191 vcle.f16 q2, q3, #0
92 @ CHECK: error: instruction requires:
93 @ CHECK: error: instruction requires:
92 @ CHECK: instruction requires: {{full half-float|NEON}}
93 @ CHECK: instruction requires: {{full half-float|NEON}}
9494
9595 vclt.f16 d2, d3, d4
9696 vclt.f16 q2, q3, q4
97 @ CHECK: error: instruction requires:
98 @ CHECK: error: instruction requires:
97 @ CHECK: instruction requires: {{full half-float|NEON}}
98 @ CHECK: instruction requires: {{full half-float|NEON}}
9999
100100 vclt.f16 d2, d3, #0
101101 vclt.f16 q2, q3, #0
102 @ CHECK: error: instruction requires:
103 @ CHECK: error: instruction requires:
102 @ CHECK: instruction requires: {{full half-float|NEON}}
103 @ CHECK: instruction requires: {{full half-float|NEON}}
104104
105105 vacge.f16 d0, d1, d2
106106 vacge.f16 q0, q1, q2
107 @ CHECK: error: instruction requires:
108 @ CHECK: error: instruction requires:
107 @ CHECK: instruction requires: {{full half-float|NEON}}
108 @ CHECK: instruction requires: {{full half-float|NEON}}
109109
110110 vacgt.f16 d0, d1, d2
111111 vacgt.f16 q0, q1, q2
112 @ CHECK: error: instruction requires:
113 @ CHECK: error: instruction requires:
112 @ CHECK: instruction requires: {{full half-float|NEON}}
113 @ CHECK: instruction requires: {{full half-float|NEON}}
114114
115115 vacle.f16 d0, d1, d2
116116 vacle.f16 q0, q1, q2
117 @ CHECK: error: instruction requires:
118 @ CHECK: error: instruction requires:
117 @ CHECK: instruction requires: {{full half-float|NEON}}
118 @ CHECK: instruction requires: {{full half-float|NEON}}
119119
120120 vaclt.f16 d0, d1, d2
121121 vaclt.f16 q0, q1, q2
122 @ CHECK: error: instruction requires:
123 @ CHECK: error: instruction requires:
122 @ CHECK: instruction requires: {{full half-float|NEON}}
123 @ CHECK: instruction requires: {{full half-float|NEON}}
124124
125125 vabd.f16 d0, d1, d2
126126 vabd.f16 q0, q1, q2
127 @ CHECK: error: instruction requires:
128 @ CHECK: error: instruction requires:
127 @ CHECK: instruction requires: {{full half-float|NEON}}
128 @ CHECK: instruction requires: {{full half-float|NEON}}
129129
130130 vabs.f16 d0, d1
131131 vabs.f16 q0, q1
132 @ CHECK: error: instruction requires:
133 @ CHECK: error: instruction requires:
132 @ CHECK: instruction requires: {{full half-float|NEON}}
133 @ CHECK: instruction requires: {{full half-float|NEON}}
134134
135135 vmax.f16 d0, d1, d2
136136 vmax.f16 q0, q1, q2
137 @ CHECK: error: instruction requires:
138 @ CHECK: error: instruction requires:
137 @ CHECK: instruction requires: {{full half-float|NEON}}
138 @ CHECK: instruction requires: {{full half-float|NEON}}
139139
140140 vmin.f16 d0, d1, d2
141141 vmin.f16 q0, q1, q2
142 @ CHECK: error: instruction requires:
143 @ CHECK: error: instruction requires:
142 @ CHECK: instruction requires: {{full half-float|NEON}}
143 @ CHECK: instruction requires: {{full half-float|NEON}}
144144
145145 vmaxnm.f16 d0, d1, d2
146146 vmaxnm.f16 q0, q1, q2
147 @ CHECK: error: instruction requires:
148 @ CHECK: error: instruction requires:
147 @ CHECK: instruction requires: {{full half-float|NEON}}
148 @ CHECK: instruction requires: {{full half-float|NEON}}
149149
150150 vminnm.f16 d0, d1, d2
151151 vminnm.f16 q0, q1, q2
152 @ CHECK: error: instruction requires:
153 @ CHECK: error: instruction requires:
152 @ CHECK: instruction requires: {{full half-float|NEON}}
153 @ CHECK: instruction requires: {{full half-float|NEON}}
154154
155155 vpadd.f16 d0, d1, d2
156 @ CHECK: error: instruction requires:
156 @ CHECK: instruction requires: {{full half-float|NEON}}
157157
158158 vpmax.f16 d0, d1, d2
159 @ CHECK: error: instruction requires:
159 @ CHECK: instruction requires: {{full half-float|NEON}}
160160
161161 vpmin.f16 d0, d1, d2
162 @ CHECK: error: instruction requires:
162 @ CHECK: instruction requires: {{full half-float|NEON}}
163163
164164 vrecpe.f16 d0, d1
165165 vrecpe.f16 q0, q1
166 @ CHECK: error: instruction requires:
167 @ CHECK: error: instruction requires:
166 @ CHECK: instruction requires: {{full half-float|NEON}}
167 @ CHECK: instruction requires: {{full half-float|NEON}}
168168
169169 vrecps.f16 d0, d1, d2
170170 vrecps.f16 q0, q1, q2
171 @ CHECK: error: instruction requires:
172 @ CHECK: error: instruction requires:
171 @ CHECK: instruction requires: {{full half-float|NEON}}
172 @ CHECK: instruction requires: {{full half-float|NEON}}
173173
174174 vrsqrte.f16 d0, d1
175175 vrsqrte.f16 q0, q1
176 @ CHECK: error: instruction requires:
177 @ CHECK: error: instruction requires:
176 @ CHECK: instruction requires: {{full half-float|NEON}}
177 @ CHECK: instruction requires: {{full half-float|NEON}}
178178
179179 vrsqrts.f16 d0, d1, d2
180180 vrsqrts.f16 q0, q1, q2
181 @ CHECK: error: instruction requires:
182 @ CHECK: error: instruction requires:
181 @ CHECK: instruction requires: {{full half-float|NEON}}
182 @ CHECK: instruction requires: {{full half-float|NEON}}
183183
184184 vneg.f16 d0, d1
185185 vneg.f16 q0, q1
186 @ CHECK: error: instruction requires:
187 @ CHECK: error: instruction requires:
186 @ CHECK: instruction requires: {{full half-float|NEON}}
187 @ CHECK: instruction requires: {{full half-float|NEON}}
188188
189189 vcvt.s16.f16 d0, d1
190190 vcvt.u16.f16 d0, d1
194194 vcvt.u16.f16 q0, q1
195195 vcvt.f16.s16 q0, q1
196196 vcvt.f16.u16 q0, q1
197 @ CHECK: error: instruction requires:
198 @ CHECK: error: instruction requires:
199 @ CHECK: error: instruction requires:
200 @ CHECK: error: instruction requires:
201 @ CHECK: error: instruction requires:
202 @ CHECK: error: instruction requires:
203 @ CHECK: error: instruction requires:
204 @ CHECK: error: instruction requires:
197 @ CHECK: instruction requires: {{full half-float|NEON}}
198 @ CHECK: instruction requires: {{full half-float|NEON}}
199 @ CHECK: instruction requires: {{full half-float|NEON}}
200 @ CHECK: instruction requires: {{full half-float|NEON}}
201 @ CHECK: instruction requires: {{full half-float|NEON}}
202 @ CHECK: instruction requires: {{full half-float|NEON}}
203 @ CHECK: instruction requires: {{full half-float|NEON}}
204 @ CHECK: instruction requires: {{full half-float|NEON}}
205205
206206 vcvta.s16.f16 d0, d1
207207 vcvta.s16.f16 q0, q1
208208 vcvta.u16.f16 d0, d1
209209 vcvta.u16.f16 q0, q1
210 @ CHECK: error: instruction requires:
211 @ CHECK: error: instruction requires:
212 @ CHECK: error: instruction requires:
213 @ CHECK: error: instruction requires:
210 @ CHECK: instruction requires: {{full half-float|NEON}}
211 @ CHECK: instruction requires: {{full half-float|NEON}}
212 @ CHECK: instruction requires: {{full half-float|NEON}}
213 @ CHECK: instruction requires: {{full half-float|NEON}}
214214
215215 vcvtm.s16.f16 d0, d1
216216 vcvtm.s16.f16 q0, q1
217217 vcvtm.u16.f16 d0, d1
218218 vcvtm.u16.f16 q0, q1
219 @ CHECK: error: instruction requires:
220 @ CHECK: error: instruction requires:
221 @ CHECK: error: instruction requires:
222 @ CHECK: error: instruction requires:
219 @ CHECK: instruction requires: {{full half-float|NEON}}
220 @ CHECK: instruction requires: {{full half-float|NEON}}
221 @ CHECK: instruction requires: {{full half-float|NEON}}
222 @ CHECK: instruction requires: {{full half-float|NEON}}
223223
224224 vcvtn.s16.f16 d0, d1
225225 vcvtn.s16.f16 q0, q1
226226 vcvtn.u16.f16 d0, d1
227227 vcvtn.u16.f16 q0, q1
228 @ CHECK: error: instruction requires:
229 @ CHECK: error: instruction requires:
230 @ CHECK: error: instruction requires:
231 @ CHECK: error: instruction requires:
228 @ CHECK: instruction requires: {{full half-float|NEON}}
229 @ CHECK: instruction requires: {{full half-float|NEON}}
230 @ CHECK: instruction requires: {{full half-float|NEON}}
231 @ CHECK: instruction requires: {{full half-float|NEON}}
232232
233233 vcvtp.s16.f16 d0, d1
234234 vcvtp.s16.f16 q0, q1
235235 vcvtp.u16.f16 d0, d1
236236 vcvtp.u16.f16 q0, q1
237 @ CHECK: error: instruction requires:
238 @ CHECK: error: instruction requires:
239 @ CHECK: error: instruction requires:
240 @ CHECK: error: instruction requires:
237 @ CHECK: instruction requires: {{full half-float|NEON}}
238 @ CHECK: instruction requires: {{full half-float|NEON}}
239 @ CHECK: instruction requires: {{full half-float|NEON}}
240 @ CHECK: instruction requires: {{full half-float|NEON}}
241241
242242
243243 vcvt.s16.f16 d0, d1, #1
248248 vcvt.u16.f16 q0, q1, #6
249249 vcvt.f16.s16 q0, q1, #7
250250 vcvt.f16.u16 q0, q1, #8
251 @ CHECK: error: instruction requires:
252 @ CHECK: error: instruction requires:
253 @ CHECK: error: instruction requires:
254 @ CHECK: error: instruction requires:
255 @ CHECK: error: instruction requires:
256 @ CHECK: error: instruction requires:
257 @ CHECK: error: instruction requires:
258 @ CHECK: error: instruction requires:
251 @ CHECK: instruction requires: {{full half-float|NEON}}
252 @ CHECK: instruction requires: {{full half-float|NEON}}
253 @ CHECK: instruction requires: {{full half-float|NEON}}
254 @ CHECK: instruction requires: {{full half-float|NEON}}
255 @ CHECK: instruction requires: {{full half-float|NEON}}
256 @ CHECK: instruction requires: {{full half-float|NEON}}
257 @ CHECK: instruction requires: {{full half-float|NEON}}
258 @ CHECK: instruction requires: {{full half-float|NEON}}
259259
260260 vrinta.f16.f16 d0, d1
261261 vrinta.f16.f16 q0, q1
262 @ CHECK: error: instruction requires:
263 @ CHECK: error: instruction requires:
262 @ CHECK: instruction requires: {{full half-float|NEON}}
263 @ CHECK: instruction requires: {{full half-float|NEON}}
264264
265265 vrintm.f16.f16 d0, d1
266266 vrintm.f16.f16 q0, q1
267 @ CHECK: error: instruction requires:
268 @ CHECK: error: instruction requires:
267 @ CHECK: instruction requires: {{full half-float|NEON}}
268 @ CHECK: instruction requires: {{full half-float|NEON}}
269269
270270 vrintn.f16.f16 d0, d1
271271 vrintn.f16.f16 q0, q1
272 @ CHECK: error: instruction requires:
273 @ CHECK: error: instruction requires:
272 @ CHECK: instruction requires: {{full half-float|NEON}}
273 @ CHECK: instruction requires: {{full half-float|NEON}}
274274
275275 vrintp.f16.f16 d0, d1
276276 vrintp.f16.f16 q0, q1
277 @ CHECK: error: instruction requires:
278 @ CHECK: error: instruction requires:
277 @ CHECK: instruction requires: {{full half-float|NEON}}
278 @ CHECK: instruction requires: {{full half-float|NEON}}
279279
280280 vrintx.f16.f16 d0, d1
281281 vrintx.f16.f16 q0, q1
282 @ CHECK: error: instruction requires:
283 @ CHECK: error: instruction requires:
282 @ CHECK: instruction requires: {{full half-float|NEON}}
283 @ CHECK: instruction requires: {{full half-float|NEON}}
284284
285285 vrintz.f16.f16 d0, d1
286286 vrintz.f16.f16 q0, q1
287 @ CHECK: error: instruction requires:
288 @ CHECK: error: instruction requires:
287 @ CHECK: instruction requires: {{full half-float|NEON}}
288 @ CHECK: instruction requires: {{full half-float|NEON}}
3434 @ V8: error: invalid instruction
3535
3636 vseleq.f32 s0, d2, d1
37 @ V8: error: invalid operand for instruction
37 @ V8: error: invalid instruction
3838 vselgt.f64 s3, s2, s1
3939 @ V8: error: invalid operand for instruction
4040 vselgt.f32 s0, q3, q1
41 @ V8: error: invalid operand for instruction
41 @ V8: error: invalid instruction
4242 vselgt.f64 q0, s3, q1
43 @ V8: error: invalid operand for instruction
43 @ V8: error: invalid instruction
4444
4545 vmaxnm.f32 s0, d2, d1
46 @ V8: error: invalid operand for instruction
46 @ V8: error: invalid instruction
4747 vminnm.f64 s3, s2, s1
4848 @ V8: error: invalid operand for instruction
4949 vmaxnm.f32 s0, q3, q1
50 @ V8: error: invalid operand for instruction
50 @ V8: error: invalid instruction
5151 vmaxnm.f64 q0, s3, q1
52 @ V8: error: invalid operand for instruction
52 @ V8: error: invalid instruction
5353 vmaxnmgt.f64 q0, s3, q1
5454 @ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified
5555
5656 vcvta.s32.f64 d3, s2
57 @ V8: error: invalid operand for instruction
57 @ V8: error: invalid instruction
5858 vcvtp.s32.f32 d3, s2
5959 @ V8: error: invalid operand for instruction
6060 vcvtn.u32.f64 d3, s2
61 @ V8: error: invalid operand for instruction
61 @ V8: error: invalid instruction
6262 vcvtm.u32.f32 d3, s2
6363 @ V8: error: invalid operand for instruction
6464 vcvtnge.u32.f64 d3, s2
6565 @ V8: error: instruction 'vcvtn' is not predicable, but condition code specified
6666
6767 vcvtbgt.f64.f16 q0, d3
68 @ V8: error: invalid operand for instruction
68 @ V8: error: invalid instruction
6969 vcvttlt.f64.f16 s0, s3
70 @ V8: error: invalid operand for instruction
70 @ V8: note: invalid operand for instruction
7171 vcvttvs.f16.f64 s0, s3
72 @ V8: error: invalid operand for instruction
72 @ V8: note: invalid operand for instruction
7373 vcvtthi.f16.f64 q0, d3
7474 @ V8: error: invalid operand for instruction
7575
7676 vrintrlo.f32.f32 d3, q0
77 @ V8: error: invalid operand for instruction
77 @ V8: error: invalid instruction
7878 vrintxcs.f32.f32 d3, d0
7979 @ V8: error: instruction requires: NEON
8080
8181 vrinta.f64.f64 s3, q0
82 @ V8: error: invalid operand for instruction
82 @ V8: error: invalid instruction
8383 vrintn.f32.f32 d3, d0
8484 @ V8: error: instruction requires: NEON
8585 vrintp.f32 q3, q0
22 hint #240
33 hint #1000
44
5 @ CHECK: error: immediate operand must be in the range [0,239]
6 @ CHECK: error: immediate operand must be in the range [0,239]
5 @ FIXME: set the subclasses of the operand classes so that we only get one error for each.
76
7 @ CHECK: error: invalid instruction, any one of the following would fix this:
8 @ CHECK: note: immediate operand must be in the range [0,239]
9 @ CHECK: note: immediate operand must be in the range [0,15]
10
11 @ CHECK: error: invalid instruction, any one of the following would fix this:
12 @ CHECK: note: immediate operand must be in the range [0,239]
13 @ CHECK: note: immediate operand must be in the range [0,15]
14
88
99 sdiv r1, r2, r3
1010 udiv r3, r4, r5
11 @ ARM-A15: error: instruction requires: divide in ARM
11 @ ARM-A15: note: instruction requires: divide in ARM
12 @ ARM-A15: note: instruction requires: thumb
1213 @ ARM-A15: sdiv r1, r2, r3
13 @ ARM-A15: error: instruction requires: divide in ARM
14 @ ARM-A15: note: instruction requires: divide in ARM
15 @ ARM-A15: note: instruction requires: thumb
1416 @ ARM-A15: udiv r3, r4, r5
15 @ THUMB-A15: error: instruction requires: arm-mode
17 @ THUMB-A15: note: instruction requires: arm-mode
18 @ THUMB-A15: note: instruction requires: divide in THUMB
1619 @ THUMB-A15: sdiv r1, r2, r3
17 @ THUMB-A15: error: instruction requires: arm-mode
20 @ THUMB-A15: note: instruction requires: arm-mode
21 @ THUMB-A15: note: instruction requires: divide in THUMB
1822 @ THUMB-A15: udiv r3, r4, r5
1923
2024 @ ARM: error: instruction requires: divide in ARM
0 @ RUN: not llvm-mc -triple armv8 -mattr=-fp-armv8 -show-encoding < %s 2>&1 | FileCheck %s
11
22 vmaxnm.f32 s4, d5, q1
3 @ CHECK: error: invalid operand for instruction
3 @ CHECK: error: invalid instruction
44 vmaxnm.f64.f64 s4, d5, q1
5 @ CHECK: error: invalid operand for instruction
5 @ CHECK: error: invalid instruction
66 vmaxnmge.f64.f64 s4, d5, q1
77 @ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified
88
1111 vcvtp.u32.f32 s1, d2
1212 @ CHECK: error: invalid operand for instruction
1313 vcvtp.f32.u32 d1, q2
14 @ CHECK: error: invalid operand for instruction
14 @ CHECK: error: invalid instruction
1515 vcvtplo.f32.u32 s1, s2
1616 @ CHECK: error: instruction 'vcvtp' is not predicable, but condition code specified
1717
1818 vrinta.f64.f64 s3, d12
19 @ CHECK: error: invalid operand for instruction
19 @ CHECK: error: invalid instruction
2020 vrintn.f32 d3, q12
21 @ CHECK: error: invalid operand for instruction
21 @ CHECK: error: invalid instruction, any one of the following would fix this:
22 @ CHECK: note: invalid operand for instruction
23 @ CHECK: note: invalid operand for instruction
2224 vrintz.f32 d3, q12
23 @ CHECK: error: invalid operand for instruction
25 @ CHECK: error: invalid instruction, any one of the following would fix this:
26 @ CHECK: note: invalid operand for instruction
27 @ CHECK: note: invalid operand for instruction
2428 vrintmge.f32.f32 d3, d4
2529 @ CHECK: error: instruction 'vrintm' is not predicable, but condition code specified
2630
4549 @ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified
4650
4751 sha1c.32 s0, d1, q2
48 @ CHECK: error: invalid operand for instruction
52 @ CHECK: error: invalid instruction
4953 sha1m.32 q0, s1, q2
5054 @ CHECK: error: invalid operand for instruction
5155 sha1p.32 s0, q1, q2
5761 sha256h2.32 q0, q1, s2
5862 @ CHECK: error: invalid operand for instruction
5963 sha256su1.32 s0, d1, q2
60 @ CHECK: error: invalid operand for instruction
64 @ CHECK: error: invalid instruction
6165 sha256su1lt.32 q0, d1, q2
6266 @ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified
6367
6468 vmull.p64 q0, s1, s3
65 @ CHECK: error: invalid operand for instruction
69 @ CHECK: error: invalid instruction
6670 vmull.p64 s1, d2, d3
6771 @ CHECK: error: invalid operand for instruction
6872 vmullge.p64 q0, d16, d17
22
33 msr apsr_c, r0
44 @ CHECK: invalid operand for instruction
5 msr cpsr_w
5 msr cpsr_w, r0
66 @ CHECK: invalid operand for instruction
7 msr cpsr_cc
7 msr cpsr_cc, r0
88 @ CHECK: invalid operand for instruction
9 msr xpsr_c
9 msr xpsr_c, r0
1010 @ CHECK: invalid operand for instruction
1111 @ CHECK-DARWIN-ARM: ldr pc, Ltmp0
1212 @ CHECK-T2: ldr.w pc, .Ltmp[[TMP0:[0-9]+]]
1313 @ CHECK-DARWIN-T2: ldr.w pc, Ltmp0
14 @ CHECK-NONE: error: instruction requires: thumb2
14 @ CHECK-NONE: instruction requires: thumb2
1515 ldr sp, = 0x8
1616 @ CHECK-ARM: ldr sp, .Ltmp[[TMP1:[0-9]+]]
1717 @ CHECK-DARWIN-ARM: ldr sp, Ltmp1
1818 @ CHECK-T2: ldr.w sp, .Ltmp[[TMP1:[0-9]+]]
1919 @ CHECK-DARWIN-T2: ldr.w sp, Ltmp1
20 @ CHECK-NONE: error: instruction requires: thumb2
20 @ CHECK-NONE: instruction requires: thumb2
0 @ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
11 .text
2 @ CHECK: error: instruction requires: thumb2
2 @ CHECK: error: invalid instruction, any one of the following would fix this:
33 @ CHECK: ldrd r0, [r0, #512]
4 @ CHECK: note: invalid operand for instruction
5 @ CHECK: note: instruction requires: thumb2
46 ldrd r0, [r0, #512]
57
6 @ CHECK: error: instruction requires: thumb2
8 @ CHECK: error: invalid instruction, any one of the following would fix this:
79 @ CHECK: strd r0, [r0, #512]
10 @ CHECK: note: invalid operand for instruction
11 @ CHECK: note: instruction requires: thumb2
812 strd r0, [r0, #512]
1212 lsls r0, pc, #0
1313 lsls pc, pc, #0
1414
15 // CHECK-NONARM: error: instruction requires: arm-mode
15 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
1616 // CHECK-NONARM-NEXT: lsl pc, r0, #0
17 // CHECK-NONARM: error: instruction requires: arm-mode
17 // CHECK-NONARM: instruction requires: arm-mode
18 // CHECK-NONARM: invalid operand for instruction
19
20 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
1821 // CHECK-NONARM-NEXT: lsl r0, pc, #0
22 // CHECK-NONARM: instruction requires: arm-mode
23 // CHECK-NONARM: invalid operand for instruction
24
1925 // CHECK-NONARM: error: instruction requires: arm-mode
2026 // CHECK-NONARM-NEXT: lsl pc, pc, #0
21 // CHECK-NONARM: error: instruction requires: arm-mode
27
28 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
2229 // CHECK-NONARM-NEXT: lsls pc, r0, #0
23 // CHECK-NONARM: error: instruction requires: arm-mode
30 // CHECK-NONARM: instruction requires: arm-mode
31 // CHECK-NONARM: invalid operand for instruction
32
33 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
2434 // CHECK-NONARM-NEXT: lsls r0, pc, #0
35 // CHECK-NONARM: instruction requires: arm-mode
36 // CHECK-NONARM: invalid operand for instruction
37
2538 // CHECK-NONARM: error: instruction requires: arm-mode
2639 // CHECK-NONARM-NEXT: lsls pc, pc, #0
2740
3952 movs r0, pc, lsl #0
4053 movs pc, pc, lsl #0
4154
42 // FIXME: Really the error we should be giving is "requires: arm-mode"
43 // CHECK-NONARM: error: invalid operand for instruction
55 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
4456 // CHECK-NONARM-NEXT: mov pc, r0, lsl #0
45 // CHECK-NONARM: error: invalid operand for instruction
57 // CHECK-NONARM: invalid operand for instruction
58 // CHECK-NONARM: invalid operand for instruction
59 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
4660 // CHECK-NONARM-NEXT: mov r0, pc, lsl #0
47 // CHECK-NONARM: error: invalid operand for instruction
61 // CHECK-NONARM: invalid operand for instruction
62 // CHECK-NONARM: invalid operand for instruction
63 // CHECK-NONARM: immediate operand must be in the range [255,65535]
64 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
4865 // CHECK-NONARM-NEXT: mov pc, pc, lsl #0
66 // CHECK-NONARM: invalid operand for instruction
67 // CHECK-NONARM: invalid operand for instruction
4968 // CHECK-NONARM: error: invalid operand for instruction
5069 // CHECK-NONARM-NEXT: movs pc, r0, lsl #0
51 // CHECK-NONARM: error: invalid operand for instruction
70 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
5271 // CHECK-NONARM-NEXT: movs r0, pc, lsl #0
72 // CHECK-NONARM: invalid operand for instruction
73 // CHECK-NONARM: invalid operand for instruction
5374 // CHECK-NONARM: error: invalid operand for instruction
5475 // CHECK-NONARM-NEXT: movs pc, pc, lsl #0
5576
6788 lsls r0, sp, #0
6889 lsls sp, r0, #0
6990
70 // CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
91 // CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
7192 // CHECK-THUMBV7-NEXT: lsl sp, sp, #0
72 // CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
93 // CHECK-THUMBV7: instruction requires: arm-mode
94 // CHECK-THUMBV7: instruction variant requires ARMv8 or later
95 // CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
7396 // CHECK-THUMBV7-NEXT: lsls sp, sp, #0
74 // CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
97 // CHECK-THUMBV7: instruction requires: arm-mode
98 // CHECK-THUMBV7: instruction variant requires ARMv8 or later
99 // CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
75100 // CHECK-THUMBV7-NEXT: lsls r0, sp, #0
76 // CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
101 // CHECK-THUMBV7: instruction requires: arm-mode
102 // CHECK-THUMBV7: instruction variant requires ARMv8 or later
103 // CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
77104 // CHECK-THUMBV7-NEXT: lsls sp, r0, #0
105 // CHECK-THUMBV7: instruction requires: arm-mode
106 // CHECK-THUMBV7: instruction variant requires ARMv8 or later
78107
79108 // CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]
80109 // CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]
87116 movs sp, r0, lsl #0
88117
89118 // FIXME: We should consistently have the "requires ARMv8" error here
90 // CHECK-THUMBV7: error: invalid operand for instruction
119 // CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
120 // CHECK-THUMBV7: invalid operand for instruction
91121 // CHECK-THUMBV7-NEXT: mov sp, sp, lsl #0
92 // CHECK-THUMBV7: error: invalid operand for instruction
122 // CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
123 // CHECK-THUMBV7: invalid operand for instruction
93124 // CHECK-THUMBV7-NEXT: movs sp, sp, lsl #0
94 // CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
125 // CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
126 // CHECK-THUMBV7: instruction variant requires ARMv8 or later
95127 // CHECK-THUMBV7-NEXT: movs r0, sp, lsl #0
96 // CHECK-THUMBV7: error: invalid operand for instruction
128 // CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
129 // CHECK-THUMBV7: invalid operand for instruction
97130 // CHECK-THUMBV7-NEXT: movs sp, r0, lsl #0
98131
99132 // CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]
99 # CHECK: error: invalid operand for instruction
1010
1111 ADD.W r0, r0, #0xFF01FF01
12 # CHECK: error: immediate operand must be in the range [0,7]
12 # CHECK: invalid operand for instruction
1313
1414 ORR r0, r1, #0xFFFFFF00
15 # CHECK: error: instruction requires: thumb2
15 # CHECK: error: invalid instruction, any one of the following would fix this:
16 # CHECK: note: invalid operand for instruction
17 # CHECK: note: instruction requires: thumb2
1618 ORN r0, r1, #0xFFFFFF00
1719 # CHECK: error: instruction requires: thumb2
22 .thumb
33
44 ADDs r1, r0, #0xFFFFFFF5
5 # CHECK: error: instruction requires: arm-mode
5 # CHECK: error: invalid instruction, any one of the following would fix this:
6 # CHECK-DAG: note: instruction requires: thumb2
7 # CHECK-DAG: note: invalid operand for instruction
8 # CHECK-DAG: note: immediate operand must be in the range [0,7]
69
710 ADDs r0, #0xFFFFFEFF
8 # CHECK: error: immediate operand must be in the range [0,255]
11 # CHECK: error: invalid instruction, any one of the following would fix this:
12 # CHECK-DAG: note: invalid operand for instruction
13 # CHECK-DAG: note: immediate operand must be in the range [0,255]
914
1015 SUBs r1, r0, #0xFFFFFFF5
11 # CHECK: error: instruction requires: arm-mode
16 # CHECK: error: invalid instruction, any one of the following would fix this:
17 # CHECK-DAG: note: invalid operand for instruction
18 # CHECK-DAG: note: immediate operand must be in the range [0,7]
1219
1320 SUBs r0, #0xFFFFFEFF
14 # CHECK: error: immediate operand must be in the range [0,255]
21 # CHECK: error: invalid instruction, any one of the following would fix this:
22 # CHECK-DAG: note: invalid operand for instruction
23 # CHECK-DAG: note: immediate operand must be in the range [0,255]
1524
1625 ORRs r0, r1, #0xFFFFFF00
17 # CHECK: error: instruction requires: thumb2
26 # CHECK: error: invalid instruction, any one of the following would fix this:
27 # CHECK-DAG: note: instruction requires: thumb2
28 # CHECK-DAG: note: too many operands for instruction
29
1830 ORNs r0, r1, #0xFFFFFF00
1931 # CHECK: error: instruction requires: thumb2
44
55 ADDs r1, r0, #0xFFFFFFF9
66 # CHECK: subs r1, r0, #7
7 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
7 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
88 ADDs r0, #0xFFFFFF01
99 # CHECK: subs r0, #255
10 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
10 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
1111
1212 SUBs r0, #0xFFFFFF01
1313 # CHECK: adds r0, #255
14 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
14 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
1515
1616 SUBs r1, r0, #0xFFFFFFF9
1717 # CHECK: adds r1, r0, #7
18 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
18 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
44
55 ADC r0, r1, #0xFFFFFF00
66 # CHECK: sbc r0, r1, #255
7 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
7 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
88 # CHECK-DISABLED: ADC
99 ADC r0, r1, #0xFFFFFE03
1010 # CHECK: sbc r0, r1, #508
11 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
11 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
1212 # CHECK-DISABLED: ADC
1313 ADD r0, r1, #0xFFFFFF01
1414 # CHECK: sub r0, r1, #255
15 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
15 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
1616 # CHECK-DISABLED: ADD
1717 AND r0, r1, #0xFFFFFF00
1818 # CHECK: bic r0, r1, #255
19 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
19 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
2020 # CHECK-DISABLED: AND
2121 BIC r0, r1, #0xFFFFFF00
2222 # CHECK: and r0, r1, #255
23 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
23 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
2424 # CHECK-DISABLED: BIC
2525 CMP r0, #0xFFFFFF01
2626 # CHECK: cmn r0, #255
27 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
27 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
2828 # CHECK-DISABLED: CMP
2929 CMN r0, #0xFFFFFF01
3030 # CHECK: cmp r0, #255
31 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
31 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
3232 # CHECK-DISABLED: CMN
3333 MOV r0, #0xFFFFFF00
3434 # CHECK: mvn r0, #255
35 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
35 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
3636 # CHECK-DISABLED: MOV
3737 MVN r0, #0xFFFFFF00
3838 # CHECK: mov r0, #255
39 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
39 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
4040 # CHECK-DISABLED: MVN
4141 SBC r0, r1, #0xFFFFFF00
4242 # CHECK: adc r0, r1, #255
43 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
43 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
4444 # CHECK-DISABLED: SBC
4545 SUB r0, r1, #0xFFFFFF01
4646 # CHECK: add r0, r1, #255
47 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
47 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
4848 # CHECK-DISABLED: SUB
4949
5050 .thumb
5151
5252 ADC r0, r1, #0xFFFFFF00
5353 # CHECK: sbc r0, r1, #255
54 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
54 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
5555 # CHECK-DISABLED: ADC
5656 ADC r0, r1, #0xFFFF00FF
5757 # CHECK: sbc r0, r1, #65280
58 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
58 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
5959 # CHECK-DISABLED: ADC
6060 ADC r0, r1, #0xFFFEFFFE
6161 # CHECK: sbc r0, r1, #65537 @ encoding: [0x61,0xf1,0x01,0x10]
62 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
62 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
6363 # CHECK-DISABLED: ADC
6464 ADC r0, r1, #0xFEFFFEFF
6565 # CHECK: sbc r0, r1, #16777472 @ encoding: [0x61,0xf1,0x01,0x20]
66 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
66 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
6767 # CHECK-DISABLED: ADC
6868 ADD.W r0, r0, #0xFFFFFF01
6969 # CHECK: sub.w r0, r0, #255
70 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
70 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
7171 # CHECK-DISABLED: ADD.W
7272 ADD.W r0, r0, #0xFF01FF02
7373 # CHECK: sub.w r0, r0, #16646398 @ encoding: [0xa0,0xf1,0xfe,0x10]
74 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
74 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
7575 # CHECK-DISABLED: ADD.W
7676 ADDW r0, r1, #0xFFFFFF01
7777 # CHECK: subw r0, r1, #255 @ encoding: [0xa1,0xf2,0xff,0x00]
78 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
78 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
7979 # CHECK-DISABLED: ADDW
8080 ADD.W r0, r1, #0xFFFFFF01
8181 # CHECK: sub.w r0, r1, #255 @ encoding: [0xa1,0xf1,0xff,0x00]
82 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
82 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
8383 # CHECK-DISABLED: ADD.W
8484 AND r0, r1, #0xFFFFFF00
85 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
85 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
8686 # CHECK-DISABLED: AND
8787 # CHECK: bic r0, r1, #255
8888 AND r0, r1, #0xFEFFFEFF
8989 # CHECK: bic r0, r1, #16777472 @ encoding: [0x21,0xf0,0x01,0x20]
90 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
90 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
9191 # CHECK-DISABLED: AND
9292 BIC r0, r1, #0xFFFFFF00
9393 # CHECK: and r0, r1, #255
94 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
94 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
9595 # CHECK-DISABLED: BIC
9696 BIC r0, r1, #0xFEFFFEFF
9797 # CHECK: and r0, r1, #16777472 @ encoding: [0x01,0xf0,0x01,0x20]
98 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
98 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
9999 # CHECK-DISABLED: BIC
100100 ORR r0, r1, #0xFFFFFF00
101 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
101 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
102102 # CHECK-DISABLED: ORR
103103 # CHECK: orn r0, r1, #255
104104 ORR r0, r1, #0xFEFFFEFF
105105 # CHECK: orn r0, r1, #16777472 @ encoding: [0x61,0xf0,0x01,0x20]
106 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
106 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
107107 # CHECK-DISABLED: ORR
108108 ORN r0, r1, #0xFFFFFF00
109109 # CHECK: orr r0, r1, #255
110 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
110 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
111111 # CHECK-DISABLED: ORN
112112 ORN r0, r1, #0xFEFFFEFF
113113 # CHECK: orr r0, r1, #16777472 @ encoding: [0x41,0xf0,0x01,0x20]
114 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
114 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
115115 # CHECK-DISABLED: ORN
116116 CMP r0, #0xFFFFFF01
117117 # CHECK: cmn.w r0, #255
118 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
118 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
119119 # CHECK-DISABLED: CMP
120120 CMN r0, #0xFFFFFF01
121121 # CHECK: cmp.w r0, #255
122 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
122 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
123123 # CHECK-DISABLED: CMN
124124 MOV r0, #0xFFFFFF00
125125 # CHECK: mvn r0, #255
126 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
126 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
127127 # CHECK-DISABLED: MOV
128128 MVN r0, #0xFFFFFF00
129129 # CHECK: mov.w r0, #255
130 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
130 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
131131 # CHECK-DISABLED: MVN
132132 SBC r0, r1, #0xFFFFFF00
133133 # CHECK: adc r0, r1, #255
134 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
134 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
135135 # CHECK-DISABLED: SBC
136136 SUBW r0, r1, #0xFFFFFF01
137137 # CHECK: addw r0, r1, #255
138 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
138 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
139139 # CHECK-DISABLED: SUBW
140140 SUB.W r0, r1, #0xFFFFFF01
141141 # CHECK: add.w r0, r1, #255
142 # CHECK-DISABLED: error: instruction requires: NegativeImmediates
142 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
143143 # CHECK-DISABLED: SUB.W
0 // RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.3a,+neon,+fullfp16 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=THUMB --check-prefix=FP16-THUMB
1 // RUN: FileCheck --check-prefix=STDERR <%t %s
1 // RUN: FileCheck --check-prefix=STDERR --check-prefix=NEON-STDERR <%t %s
22 // RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.3a,+neon,+fullfp16 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=ARM --check-prefix=FP16-ARM
3 // RUN: FileCheck --check-prefix=STDERR <%t %s
3 // RUN: FileCheck --check-prefix=STDERR --check-prefix=NEON-STDERR <%t %s
44
55 // RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.3a,+neon,-fullfp16 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=THUMB
6 // RUN: FileCheck --check-prefix=STDERR --check-prefix=NO-FP16-STDERR <%t %s
6 // RUN: FileCheck --check-prefix=STDERR --check-prefix=NO-FP16-STDERR --check-prefix=NEON-STDERR <%t %s
77 // RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.3a,+neon,-fullfp16 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=ARM
8 // RUN: FileCheck --check-prefix=STDERR --check-prefix=NO-FP16-STDERR <%t %s
8 // RUN: FileCheck --check-prefix=STDERR --check-prefix=NO-FP16-STDERR --check-prefix=NEON-STDERR <%t %s
99
1010 // RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.3a,-neon,+fullfp16 -show-encoding < %s 2>%t
1111 // RUN: FileCheck --check-prefix=STDERR --check-prefix=NO-NEON-STDERR <%t %s
2121 vcmla.f16 d0, d1, d2, #0
2222 // FP16-ARM: vcmla.f16 d0, d1, d2, #0 @ encoding: [0x02,0x08,0x21,0xfc]
2323 // FP16-THUMB: vcmla.f16 d0, d1, d2, #0 @ encoding: [0x21,0xfc,0x02,0x08]
24 // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float
24 // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float
2525 // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a
2626 // NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
2727 vcmla.f16 q0, q1, q2, #0
2828 // FP16-ARM: vcmla.f16 q0, q1, q2, #0 @ encoding: [0x44,0x08,0x22,0xfc]
2929 // FP16-THUMB: vcmla.f16 q0, q1, q2, #0 @ encoding: [0x22,0xfc,0x44,0x08]
30 // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float
30 // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float
3131 // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a
3232 // NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
3333 vcmla.f32 d0, d1, d2, #0
6060
6161 // Invalid rotations
6262 vcmla.f32 d0, d1, d2, #-90
63 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
63 // NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
64 // NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction
6465 vcmla.f32 d0, d1, d2, #1
65 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
66 // NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
67 // NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction
6668 vcmla.f32 d0, d1, d2, #360
67 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
69 // NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
70 // NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction
6871
6972 /* ==== VCADD vector ==== */
7073
7275 vcadd.f16 d0, d1, d2, #90
7376 // FP16-ARM: vcadd.f16 d0, d1, d2, #90 @ encoding: [0x02,0x08,0x81,0xfc]
7477 // FP16-THUMB: vcadd.f16 d0, d1, d2, #90 @ encoding: [0x81,0xfc,0x02,0x08]
75 // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float
78 // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float
7679 // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a
7780 // NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
7881 vcadd.f16 q0, q1, q2, #90
7982 // FP16-ARM: vcadd.f16 q0, q1, q2, #90 @ encoding: [0x44,0x08,0x82,0xfc]
8083 // FP16-THUMB: vcadd.f16 q0, q1, q2, #90 @ encoding: [0x82,0xfc,0x44,0x08]
81 // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float
84 // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float
8285 // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a
8386 // NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
8487 vcadd.f32 d0, d1, d2, #90
101104
102105 // Invalid rotations
103106 vcadd.f32 d0, d1, d2, #0
104 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
107 // NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
108 // NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction
105109 vcadd.f32 d0, d1, d2, #180
106 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
110 // NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
111 // NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction
107112 vcadd.f32 d0, d1, d2, #-90
108 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
113 // NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
114 // NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction
109115 vcadd.f32 d0, d1, d2, #1
110 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
116 // NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
117 // NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction
111118 vcadd.f32 d0, d1, d2, #360
112 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
119 // NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
120 // NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction
113121
114122
115123 /* ==== VCMLA indexed ==== */
118126 vcmla.f16 d0, d1, d2[0], #0
119127 // FP16-ARM: vcmla.f16 d0, d1, d2[0], #0 @ encoding: [0x02,0x08,0x01,0xfe]
120128 // FP16-THUMB: vcmla.f16 d0, d1, d2[0], #0 @ encoding: [0x01,0xfe,0x02,0x08]
121 // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float
129 // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float
122130 // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a
123131 // NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
124132 vcmla.f16 q0, q1, d2[0], #0
125133 // FP16-ARM: vcmla.f16 q0, q1, d2[0], #0 @ encoding: [0x42,0x08,0x02,0xfe]
126134 // FP16-THUMB: vcmla.f16 q0, q1, d2[0], #0 @ encoding: [0x02,0xfe,0x42,0x08]
127 // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float
135 // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float
128136 // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a
129137 // NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
130138 vcmla.f32 d0, d1, d2[0], #0
157165
158166 // Invalid rotations
159167 vcmla.f32 d0, d1, d2[0], #-90
160 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
168 // NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
169 // NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction
161170 vcmla.f32 d0, d1, d2[0], #1
162 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
171 // NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
172 // NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction
163173 vcmla.f32 d0, d1, d2[0], #360
164 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
174 // NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
175 // NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction
165176
166177 // Valid indices
167178 vcmla.f16 d0, d1, d2[1], #0
171182 // NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
172183
173184 // Invalid indices
174 // FIXME: These error messages are emitted because the index operand is not
175 // valid as a rotation, so they are a bit unintuitive. Can we do better?
185 // The text of these errors vary depending on whether fullfp16 is present.
176186 vcmla.f16 d0, d1, d2[2], #0
177 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
187 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error:
178188 vcmla.f32 d0, d1, d2[1], #0
179 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
189 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error:
99 vld1.8 {d0}, [r4:256]
1010
1111 @ CHECK: vld1.8 {d0}, [r4] @ encoding: [0x24,0xf9,0x0f,0x07]
12 @ CHECK-ERRORS: error: alignment must be 64 or omitted
12 @ CHECK-ERRORS: alignment must be 64 or omitted
1313 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16]
1414 @ CHECK-ERRORS: ^
15 @ CHECK-ERRORS: error: alignment must be 64 or omitted
15 @ CHECK-ERRORS: alignment must be 64 or omitted
1616 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32]
1717 @ CHECK-ERRORS: ^
1818 @ CHECK: vld1.8 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x07]
19 @ CHECK-ERRORS: error: alignment must be 64 or omitted
19 @ CHECK-ERRORS: alignment must be 64 or omitted
2020 @ CHECK-ERRORS: vld1.8 {d0}, [r4:128]
2121 @ CHECK-ERRORS: ^
22 @ CHECK-ERRORS: error: alignment must be 64 or omitted
22 @ CHECK-ERRORS: alignment must be 64 or omitted
2323 @ CHECK-ERRORS: vld1.8 {d0}, [r4:256]
2424 @ CHECK-ERRORS: ^
2525
3131 vld1.8 {d0}, [r4:256]!
3232
3333 @ CHECK: vld1.8 {d0}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x07]
34 @ CHECK-ERRORS: error: alignment must be 64 or omitted
34 @ CHECK-ERRORS: alignment must be 64 or omitted
3535 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16]!
3636 @ CHECK-ERRORS: ^
37 @ CHECK-ERRORS: error: alignment must be 64 or omitted
37 @ CHECK-ERRORS: alignment must be 64 or omitted
3838 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32]!
3939 @ CHECK-ERRORS: ^
4040 @ CHECK: vld1.8 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x07]
41 @ CHECK-ERRORS: error: alignment must be 64 or omitted
41 @ CHECK-ERRORS: alignment must be 64 or omitted
4242 @ CHECK-ERRORS: vld1.8 {d0}, [r4:128]!
4343 @ CHECK-ERRORS: ^
44 @ CHECK-ERRORS: error: alignment must be 64 or omitted
44 @ CHECK-ERRORS: alignment must be 64 or omitted
4545 @ CHECK-ERRORS: vld1.8 {d0}, [r4:256]!
4646 @ CHECK-ERRORS: ^
4747
5353 vld1.8 {d0}, [r4:256], r6
5454
5555 @ CHECK: vld1.8 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x07]
56 @ CHECK-ERRORS: error: alignment must be 64 or omitted
56 @ CHECK-ERRORS: alignment must be 64 or omitted
5757 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16], r6
5858 @ CHECK-ERRORS: ^
59 @ CHECK-ERRORS: error: alignment must be 64 or omitted
59 @ CHECK-ERRORS: alignment must be 64 or omitted
6060 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32], r6
6161 @ CHECK-ERRORS: ^
6262 @ CHECK: vld1.8 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x07]
63 @ CHECK-ERRORS: error: alignment must be 64 or omitted
63 @ CHECK-ERRORS: alignment must be 64 or omitted
6464 @ CHECK-ERRORS: vld1.8 {d0}, [r4:128], r6
6565 @ CHECK-ERRORS: ^
66 @ CHECK-ERRORS: error: alignment must be 64 or omitted
66 @ CHECK-ERRORS: alignment must be 64 or omitted
6767 @ CHECK-ERRORS: vld1.8 {d0}, [r4:256], r6
6868 @ CHECK-ERRORS: ^
6969
7575 vld1.8 {d0, d1}, [r4:256]
7676
7777 @ CHECK: vld1.8 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x0f,0x0a]
78 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
78 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
7979 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16]
8080 @ CHECK-ERRORS: ^
81 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
81 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
8282 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32]
8383 @ CHECK-ERRORS: ^
8484 @ CHECK: vld1.8 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x0a]
8585 @ CHECK: vld1.8 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x0a]
86 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
86 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
8787 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256]
8888 @ CHECK-ERRORS: ^
8989
9595 vld1.8 {d0, d1}, [r4:256]!
9696
9797 @ CHECK: vld1.8 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x0a]
98 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
98 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
9999 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16]!
100100 @ CHECK-ERRORS: ^
101 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
101 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
102102 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32]!
103103 @ CHECK-ERRORS: ^
104104 @ CHECK: vld1.8 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x0a]
105105 @ CHECK: vld1.8 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x0a]
106 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
106 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
107107 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256]!
108108 @ CHECK-ERRORS: ^
109109
115115 vld1.8 {d0, d1}, [r4:256], r6
116116
117117 @ CHECK: vld1.8 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x0a]
118 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
118 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
119119 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16], r6
120120 @ CHECK-ERRORS: ^
121 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
121 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
122122 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32], r6
123123 @ CHECK-ERRORS: ^
124124 @ CHECK: vld1.8 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x0a]
125125 @ CHECK: vld1.8 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x0a]
126 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
126 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
127127 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256], r6
128128 @ CHECK-ERRORS: ^
129129
135135 vld1.8 {d0, d1, d2}, [r4:256]
136136
137137 @ CHECK: vld1.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x06]
138 @ CHECK-ERRORS: error: alignment must be 64 or omitted
138 @ CHECK-ERRORS: alignment must be 64 or omitted
139139 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16]
140140 @ CHECK-ERRORS: ^
141 @ CHECK-ERRORS: error: alignment must be 64 or omitted
141 @ CHECK-ERRORS: alignment must be 64 or omitted
142142 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32]
143143 @ CHECK-ERRORS: ^
144144 @ CHECK: vld1.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x06]
145 @ CHECK-ERRORS: error: alignment must be 64 or omitted
145 @ CHECK-ERRORS: alignment must be 64 or omitted
146146 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128]
147147 @ CHECK-ERRORS: ^
148 @ CHECK-ERRORS: error: alignment must be 64 or omitted
148 @ CHECK-ERRORS: alignment must be 64 or omitted
149149 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256]
150150 @ CHECK-ERRORS: ^
151151
157157 vld1.8 {d0, d1, d2}, [r4:256]!
158158
159159 @ CHECK: vld1.8 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x06]
160 @ CHECK-ERRORS: error: alignment must be 64 or omitted
160 @ CHECK-ERRORS: alignment must be 64 or omitted
161161 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16]!
162162 @ CHECK-ERRORS: ^
163 @ CHECK-ERRORS: error: alignment must be 64 or omitted
163 @ CHECK-ERRORS: alignment must be 64 or omitted
164164 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32]!
165165 @ CHECK-ERRORS: ^
166166 @ CHECK: vld1.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x06]
167 @ CHECK-ERRORS: error: alignment must be 64 or omitted
167 @ CHECK-ERRORS: alignment must be 64 or omitted
168168 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128]!
169169 @ CHECK-ERRORS: ^
170 @ CHECK-ERRORS: error: alignment must be 64 or omitted
170 @ CHECK-ERRORS: alignment must be 64 or omitted
171171 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256]!
172172 @ CHECK-ERRORS: ^
173173
179179 vld1.8 {d0, d1, d2}, [r4:256], r6
180180
181181 @ CHECK: vld1.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x06]
182 @ CHECK-ERRORS: error: alignment must be 64 or omitted
182 @ CHECK-ERRORS: alignment must be 64 or omitted
183183 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16], r6
184184 @ CHECK-ERRORS: ^
185 @ CHECK-ERRORS: error: alignment must be 64 or omitted
185 @ CHECK-ERRORS: alignment must be 64 or omitted
186186 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32], r6
187187 @ CHECK-ERRORS: ^
188188 @ CHECK: vld1.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x06]
189 @ CHECK-ERRORS: error: alignment must be 64 or omitted
189 @ CHECK-ERRORS: alignment must be 64 or omitted
190190 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128], r6
191191 @ CHECK-ERRORS: ^
192 @ CHECK-ERRORS: error: alignment must be 64 or omitted
192 @ CHECK-ERRORS: alignment must be 64 or omitted
193193 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256], r6
194194 @ CHECK-ERRORS: ^
195195
201201 vld1.8 {d0, d1, d2, d3}, [r4:256]
202202
203203 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x0f,0x02]
204 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
204 @ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted
205205 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16]
206206 @ CHECK-ERRORS: ^
207 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
207 @ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted
208208 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32]
209209 @ CHECK-ERRORS: ^
210210 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x02]
219219 vld1.8 {d0, d1, d2, d3}, [r4:256]!
220220
221221 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x02]
222 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
222 @ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted
223223 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16]!
224224 @ CHECK-ERRORS: ^
225 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
225 @ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted
226226 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32]!
227227 @ CHECK-ERRORS: ^
228228 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x02]
237237 vld1.8 {d0, d1, d2, d3}, [r4:256], r6
238238
239239 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x02]
240 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
240 @ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted
241241 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16], r6
242242 @ CHECK-ERRORS: ^
243 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
243 @ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted
244244 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32], r6
245245 @ CHECK-ERRORS: ^
246246 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x02]
255255 vld1.8 {d0[2]}, [r4:256]
256256
257257 @ CHECK: vld1.8 {d0[2]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x00]
258 @ CHECK-ERRORS: error: alignment must be omitted
258 @ CHECK-ERRORS: alignment must be omitted
259259 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16]
260260 @ CHECK-ERRORS: ^
261 @ CHECK-ERRORS: error: alignment must be omitted
261 @ CHECK-ERRORS: alignment must be omitted
262262 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32]
263263 @ CHECK-ERRORS: ^
264 @ CHECK-ERRORS: error: alignment must be omitted
264 @ CHECK-ERRORS: alignment must be omitted
265265 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64]
266266 @ CHECK-ERRORS: ^
267 @ CHECK-ERRORS: error: alignment must be omitted
267 @ CHECK-ERRORS: alignment must be omitted
268268 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128]
269269 @ CHECK-ERRORS: ^
270 @ CHECK-ERRORS: error: alignment must be omitted
270 @ CHECK-ERRORS: alignment must be omitted
271271 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256]
272272 @ CHECK-ERRORS: ^
273273
279279 vld1.8 {d0[2]}, [r4:256]!
280280
281281 @ CHECK: vld1.8 {d0[2]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x00]
282 @ CHECK-ERRORS: error: alignment must be omitted
282 @ CHECK-ERRORS: alignment must be omitted
283283 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16]!
284284 @ CHECK-ERRORS: ^
285 @ CHECK-ERRORS: error: alignment must be omitted
285 @ CHECK-ERRORS: alignment must be omitted
286286 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32]!
287287 @ CHECK-ERRORS: ^
288 @ CHECK-ERRORS: error: alignment must be omitted
288 @ CHECK-ERRORS: alignment must be omitted
289289 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64]!
290290 @ CHECK-ERRORS: ^
291 @ CHECK-ERRORS: error: alignment must be omitted
291 @ CHECK-ERRORS: alignment must be omitted
292292 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128]!
293293 @ CHECK-ERRORS: ^
294 @ CHECK-ERRORS: error: alignment must be omitted
294 @ CHECK-ERRORS: alignment must be omitted
295295 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256]!
296296 @ CHECK-ERRORS: ^
297297
303303 vld1.8 {d0[2]}, [r4:256], r6
304304
305305 @ CHECK: vld1.8 {d0[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x00]
306 @ CHECK-ERRORS: error: alignment must be omitted
306 @ CHECK-ERRORS: alignment must be omitted
307307 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16], r6
308308 @ CHECK-ERRORS: ^
309 @ CHECK-ERRORS: error: alignment must be omitted
309 @ CHECK-ERRORS: alignment must be omitted
310310 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32], r6
311311 @ CHECK-ERRORS: ^
312 @ CHECK-ERRORS: error: alignment must be omitted
312 @ CHECK-ERRORS: alignment must be omitted
313313 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64], r6
314314 @ CHECK-ERRORS: ^
315 @ CHECK-ERRORS: error: alignment must be omitted
315 @ CHECK-ERRORS: alignment must be omitted
316316 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128], r6
317317 @ CHECK-ERRORS: ^
318 @ CHECK-ERRORS: error: alignment must be omitted
318 @ CHECK-ERRORS: alignment must be omitted
319319 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256], r6
320320 @ CHECK-ERRORS: ^
321321
327327 vld1.8 {d0[]}, [r4:256]
328328
329329 @ CHECK: vld1.8 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0c]
330 @ CHECK-ERRORS: error: alignment must be omitted
330 @ CHECK-ERRORS: alignment must be omitted
331331 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16]
332332 @ CHECK-ERRORS: ^
333 @ CHECK-ERRORS: error: alignment must be omitted
333 @ CHECK-ERRORS: alignment must be omitted
334334 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32]
335335 @ CHECK-ERRORS: ^
336 @ CHECK-ERRORS: error: alignment must be omitted
336 @ CHECK-ERRORS: alignment must be omitted
337337 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64]
338338 @ CHECK-ERRORS: ^
339 @ CHECK-ERRORS: error: alignment must be omitted
339 @ CHECK-ERRORS: alignment must be omitted
340340 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128]
341341 @ CHECK-ERRORS: ^
342 @ CHECK-ERRORS: error: alignment must be omitted
342 @ CHECK-ERRORS: alignment must be omitted
343343 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256]
344344 @ CHECK-ERRORS: ^
345345
351351 vld1.8 {d0[]}, [r4:256]!
352352
353353 @ CHECK: vld1.8 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0c]
354 @ CHECK-ERRORS: error: alignment must be omitted
354 @ CHECK-ERRORS: alignment must be omitted
355355 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16]!
356356 @ CHECK-ERRORS: ^
357 @ CHECK-ERRORS: error: alignment must be omitted
357 @ CHECK-ERRORS: alignment must be omitted
358358 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32]!
359359 @ CHECK-ERRORS: ^
360 @ CHECK-ERRORS: error: alignment must be omitted
360 @ CHECK-ERRORS: alignment must be omitted
361361 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64]!
362362 @ CHECK-ERRORS: ^
363 @ CHECK-ERRORS: error: alignment must be omitted
363 @ CHECK-ERRORS: alignment must be omitted
364364 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128]!
365365 @ CHECK-ERRORS: ^
366 @ CHECK-ERRORS: error: alignment must be omitted
366 @ CHECK-ERRORS: alignment must be omitted
367367 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256]!
368368 @ CHECK-ERRORS: ^
369369
375375 vld1.8 {d0[]}, [r4:256], r6
376376
377377 @ CHECK: vld1.8 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0c]
378 @ CHECK-ERRORS: error: alignment must be omitted
378 @ CHECK-ERRORS: alignment must be omitted
379379 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16], r6
380380 @ CHECK-ERRORS: ^
381 @ CHECK-ERRORS: error: alignment must be omitted
381 @ CHECK-ERRORS: alignment must be omitted
382382 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32], r6
383383 @ CHECK-ERRORS: ^
384 @ CHECK-ERRORS: error: alignment must be omitted
384 @ CHECK-ERRORS: alignment must be omitted
385385 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64], r6
386386 @ CHECK-ERRORS: ^
387 @ CHECK-ERRORS: error: alignment must be omitted
387 @ CHECK-ERRORS: alignment must be omitted
388388 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128], r6
389389 @ CHECK-ERRORS: ^
390 @ CHECK-ERRORS: error: alignment must be omitted
390 @ CHECK-ERRORS: alignment must be omitted
391391 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256], r6
392392 @ CHECK-ERRORS: ^
393393
399399 vld1.8 {d0[], d1[]}, [r4:256]
400400
401401 @ CHECK: vld1.8 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0c]
402 @ CHECK-ERRORS: error: alignment must be omitted
402 @ CHECK-ERRORS: alignment must be omitted
403403 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16]
404404 @ CHECK-ERRORS: ^
405 @ CHECK-ERRORS: error: alignment must be omitted
405 @ CHECK-ERRORS: alignment must be omitted
406406 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32]
407407 @ CHECK-ERRORS: ^
408 @ CHECK-ERRORS: error: alignment must be omitted
408 @ CHECK-ERRORS: alignment must be omitted
409409 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64]
410410 @ CHECK-ERRORS: ^
411 @ CHECK-ERRORS: error: alignment must be omitted
411 @ CHECK-ERRORS: alignment must be omitted
412412 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128]
413413 @ CHECK-ERRORS: ^
414 @ CHECK-ERRORS: error: alignment must be omitted
414 @ CHECK-ERRORS: alignment must be omitted
415415 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256]
416416 @ CHECK-ERRORS: ^
417417
423423 vld1.8 {d0[], d1[]}, [r4:256]!
424424
425425 @ CHECK: vld1.8 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0c]
426 @ CHECK-ERRORS: error: alignment must be omitted
426 @ CHECK-ERRORS: alignment must be omitted
427427 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16]!
428428 @ CHECK-ERRORS: ^
429 @ CHECK-ERRORS: error: alignment must be omitted
429 @ CHECK-ERRORS: alignment must be omitted
430430 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32]!
431431 @ CHECK-ERRORS: ^
432 @ CHECK-ERRORS: error: alignment must be omitted
432 @ CHECK-ERRORS: alignment must be omitted
433433 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64]!
434434 @ CHECK-ERRORS: ^
435 @ CHECK-ERRORS: error: alignment must be omitted
435 @ CHECK-ERRORS: alignment must be omitted
436436 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128]!
437437 @ CHECK-ERRORS: ^
438 @ CHECK-ERRORS: error: alignment must be omitted
438 @ CHECK-ERRORS: alignment must be omitted
439439 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256]!
440440 @ CHECK-ERRORS: ^
441441
447447 vld1.8 {d0[], d1[]}, [r4:256], r6
448448
449449 @ CHECK: vld1.8 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0c]
450 @ CHECK-ERRORS: error: alignment must be omitted
450 @ CHECK-ERRORS: alignment must be omitted
451451 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16], r6
452452 @ CHECK-ERRORS: ^
453 @ CHECK-ERRORS: error: alignment must be omitted
453 @ CHECK-ERRORS: alignment must be omitted
454454 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32], r6
455455 @ CHECK-ERRORS: ^
456 @ CHECK-ERRORS: error: alignment must be omitted
456 @ CHECK-ERRORS: alignment must be omitted
457457 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64], r6
458458 @ CHECK-ERRORS: ^
459 @ CHECK-ERRORS: error: alignment must be omitted
459 @ CHECK-ERRORS: alignment must be omitted
460460 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128], r6
461461 @ CHECK-ERRORS: ^
462 @ CHECK-ERRORS: error: alignment must be omitted
462 @ CHECK-ERRORS: alignment must be omitted
463463 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256], r6
464464 @ CHECK-ERRORS: ^
465465
471471 vld1.16 {d0}, [r4:256]
472472
473473 @ CHECK: vld1.16 {d0}, [r4] @ encoding: [0x24,0xf9,0x4f,0x07]
474 @ CHECK-ERRORS: error: alignment must be 64 or omitted
474 @ CHECK-ERRORS: alignment must be 64 or omitted
475475 @ CHECK-ERRORS: vld1.16 {d0}, [r4:16]
476476 @ CHECK-ERRORS: ^
477 @ CHECK-ERRORS: error: alignment must be 64 or omitted
477 @ CHECK-ERRORS: alignment must be 64 or omitted
478478 @ CHECK-ERRORS: vld1.16 {d0}, [r4:32]
479479 @ CHECK-ERRORS: ^
480480 @ CHECK: vld1.16 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x07]
481 @ CHECK-ERRORS: error: alignment must be 64 or omitted
481 @ CHECK-ERRORS: alignment must be 64 or omitted
482482 @ CHECK-ERRORS: vld1.16 {d0}, [r4:128]
483483 @ CHECK-ERRORS: ^
484 @ CHECK-ERRORS: error: alignment must be 64 or omitted
484 @ CHECK-ERRORS: alignment must be 64 or omitted
485485 @ CHECK-ERRORS: vld1.16 {d0}, [r4:256]
486486 @ CHECK-ERRORS: ^
487487
493493 vld1.16 {d0}, [r4:256]!
494494
495495 @ CHECK: vld1.16 {d0}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x07]
496 @ CHECK-ERRORS: error: alignment must be 64 or omitted
496 @ CHECK-ERRORS: alignment must be 64 or omitted
497497 @ CHECK-ERRORS: vld1.16 {d0}, [r4:16]!
498498 @ CHECK-ERRORS: ^
499 @ CHECK-ERRORS: error: alignment must be 64 or omitted
499 @ CHECK-ERRORS: alignment must be 64 or omitted
500500 @ CHECK-ERRORS: vld1.16 {d0}, [r4:32]!
501501 @ CHECK-ERRORS: ^
502502 @ CHECK: vld1.16 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x07]
503 @ CHECK-ERRORS: error: alignment must be 64 or omitted
503 @ CHECK-ERRORS: alignment must be 64 or omitted
504504 @ CHECK-ERRORS: vld1.16 {d0}, [r4:128]!
505505 @ CHECK-ERRORS: ^
506 @ CHECK-ERRORS: error: alignment must be 64 or omitted
506 @ CHECK-ERRORS: alignment must be 64 or omitted
507507 @ CHECK-ERRORS: vld1.16 {d0}, [r4:256]!
508508 @ CHECK-ERRORS: ^
509509
515515 vld1.16 {d0}, [r4:256], r6
516516
517517 @ CHECK: vld1.16 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x07]
518 @ CHECK-ERRORS: error: alignment must be 64 or omitted
518 @ CHECK-ERRORS: alignment must be 64 or omitted
519519 @ CHECK-ERRORS: vld1.16 {d0}, [r4:16], r6
520520 @ CHECK-ERRORS: ^
521 @ CHECK-ERRORS: error: alignment must be 64 or omitted
521 @ CHECK-ERRORS: alignment must be 64 or omitted
522522 @ CHECK-ERRORS: vld1.16 {d0}, [r4:32], r6
523523 @ CHECK-ERRORS: ^
524524 @ CHECK: vld1.16 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x07]
525 @ CHECK-ERRORS: error: alignment must be 64 or omitted
525 @ CHECK-ERRORS: alignment must be 64 or omitted
526526 @ CHECK-ERRORS: vld1.16 {d0}, [r4:128], r6
527527 @ CHECK-ERRORS: ^
528 @ CHECK-ERRORS: error: alignment must be 64 or omitted
528 @ CHECK-ERRORS: alignment must be 64 or omitted
529529 @ CHECK-ERRORS: vld1.16 {d0}, [r4:256], r6
530530 @ CHECK-ERRORS: ^
531531
537537 vld1.16 {d0, d1}, [r4:256]
538538
539539 @ CHECK: vld1.16 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x4f,0x0a]
540 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
540 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
541541 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16]
542542 @ CHECK-ERRORS: ^
543 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
543 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
544544 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32]
545545 @ CHECK-ERRORS: ^
546546 @ CHECK: vld1.16 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x0a]
547547 @ CHECK: vld1.16 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x0a]
548 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
548 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
549549 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256]
550550 @ CHECK-ERRORS: ^
551551
557557 vld1.16 {d0, d1}, [r4:256]!
558558
559559 @ CHECK: vld1.16 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x0a]
560 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
560 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
561561 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16]!
562562 @ CHECK-ERRORS: ^
563 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
563 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
564564 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32]!
565565 @ CHECK-ERRORS: ^
566566 @ CHECK: vld1.16 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x0a]
567567 @ CHECK: vld1.16 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x0a]
568 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
568 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
569569 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256]!
570570 @ CHECK-ERRORS: ^
571571
577577 vld1.16 {d0, d1}, [r4:256], r6
578578
579579 @ CHECK: vld1.16 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x0a]
580 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
580 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
581581 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16], r6
582582 @ CHECK-ERRORS: ^
583 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
583 @ CHECK-ERRORS: alignment must be 64, 128 or omitted
584584 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32], r6
585585 @ CHECK-ERRORS: ^
586586 @ CHECK: vld1.16 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x0a]