llvm.org GIT mirror llvm / 4bd2f44
[GlobalISel][AArch64] Adding -disable-gisel-legality-check CL option Currently it's impossible to test InstructionSelect pass with MIR which is considered illegal by the Legalizer in Assert builds. In early stages of porting an existing backend from SelectionDAG ISel to GlobalISel, however, we would have very basic CallLowering, Legalizer, and RegBankSelect implementations, but rather functional Instruction Select with quite a few patterns selectable due to the semi-automatic porting process borrowing them from SelectionDAG ISel. As we are trying to define legality as a property of being selectable by the instruction selector, it would be nice to be able to easily check what the selector can do in its current state w/o the legality check provided by the Legalizer getting in the way. It also seems beneficial to have a regression testing set up that would not allow the selector to silently regress in its support of the MIR not supported yet by the previous passes in the GlobalISel pipeline. This commit adds -disable-gisel-legality-check command line option to llc that disables those legality checks in RegBankSelect and InstructionSelect passes. It also adds quite a few MIR test cases for AArch64's Instruction Selector. Every one of them would fail on the legality check at the moment, but will select just fine if the check is disabled. Every test MachineFunction is intended to exercise a specific selection rule and that rule only, encoded in the MachineFunction's name by the rule's number, ID, and index of its GIM_Try opcode in TableGen'erated MatchTable (-optimize-match-table=false). Reviewers: ab, dsanders, qcolombet, rovka Reviewed By: bogner Subscribers: kristof.beyls, volkan, aditya_nandakumar, aemerson, rengolin, t.p.northover, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D42886 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326396 91177308-0d34-0410-b5e6-96231b3b80d8 Roman Tereshin 2 years ago
5 changed file(s) with 4590 addition(s) and 28 deletion(s). Raw diff Collapse all Expand all
1919 #include "llvm/ADT/Optional.h"
2020 #include "llvm/ADT/STLExtras.h"
2121 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/MachineFunction.h"
2223 #include "llvm/CodeGen/TargetOpcodes.h"
2324 #include "llvm/Support/raw_ostream.h"
2425 #include "llvm/Support/LowLevelTypeImpl.h"
2930 #include
3031
3132 namespace llvm {
33
34 extern cl::opt DisableGISelLegalityCheck;
3235
3336 class MachineInstr;
3437 class MachineIRBuilder;
905908 LegalizeRuleSet RulesForOpcode[LastOp - FirstOp + 1];
906909 };
907910
911 #ifndef NDEBUG
912 /// Checks that MIR is fully legal, returns an illegal instruction if it's not,
913 /// nullptr otherwise
914 const MachineInstr *machineFunctionIsIllegal(const MachineFunction &MF);
915 #endif
916
908917 } // end namespace llvm.
909918
910919 #endif // LLVM_CODEGEN_GLOBALISEL_LEGALIZERINFO_H
8080 #ifndef NDEBUG
8181 // Check that our input is fully legal: we require the function to have the
8282 // Legalized property, so it should be.
83 // FIXME: This should be in the MachineVerifier, but it can't use the
84 // LegalizerInfo as it's currently in the separate GlobalISel library.
85 // The RegBankSelected property is already checked in the verifier. Note
86 // that it has the same layering problem, but we only use inline methods so
87 // end up not needing to link against the GlobalISel library.
88 if (const LegalizerInfo *MLI = MF.getSubtarget().getLegalizerInfo())
89 for (MachineBasicBlock &MBB : MF)
90 for (MachineInstr &MI : MBB)
91 if (isPreISelGenericOpcode(MI.getOpcode()) && !MLI->isLegal(MI, MRI)) {
92 reportGISelFailure(MF, TPC, MORE, "gisel-select",
93 "instruction is not legal", MI);
94 return false;
95 }
96
83 // FIXME: This should be in the MachineVerifier, as the RegBankSelected
84 // property check already is.
85 if (!DisableGISelLegalityCheck)
86 if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
87 reportGISelFailure(MF, TPC, MORE, "gisel-select",
88 "instruction is not legal", *MI);
89 return false;
90 }
9791 #endif
9892 // FIXME: We could introduce new blocks and will need to fix the outer loop.
9993 // Until then, keep track of the number of blocks to assert that we don't.
3434 using namespace LegalizeActions;
3535
3636 #define DEBUG_TYPE "legalizer-info"
37
38 cl::opt llvm::DisableGISelLegalityCheck(
39 "disable-gisel-legality-check",
40 cl::desc("Don't verify that MIR is fully legal between GlobalISel passes"),
41 cl::Hidden);
3742
3843 raw_ostream &LegalityQuery::print(raw_ostream &OS) const {
3944 OS << Opcode << ", {";
494499 LLT::vector(NumElementsAndAction.first,
495500 IntermediateType.getScalarSizeInBits())};
496501 }
502
503 #ifndef NDEBUG
504 // FIXME: This should be in the MachineVerifier, but it can't use the
505 // LegalizerInfo as it's currently in the separate GlobalISel library.
506 // Note that RegBankSelected property already checked in the verifier
507 // has the same layering problem, but we only use inline methods so
508 // end up not needing to link against the GlobalISel library.
509 const MachineInstr *llvm::machineFunctionIsIllegal(const MachineFunction &MF) {
510 if (const LegalizerInfo *MLI = MF.getSubtarget().getLegalizerInfo()) {
511 const MachineRegisterInfo &MRI = MF.getRegInfo();
512 for (const MachineBasicBlock &MBB : MF)
513 for (const MachineInstr &MI : MBB)
514 if (isPreISelGenericOpcode(MI.getOpcode()) && !MLI->isLegal(MI, MRI))
515 return &MI;
516 }
517 return nullptr;
518 }
519 #endif
609609 #ifndef NDEBUG
610610 // Check that our input is fully legal: we require the function to have the
611611 // Legalized property, so it should be.
612 // FIXME: This should be in the MachineVerifier, but it can't use the
613 // LegalizerInfo as it's currently in the separate GlobalISel library.
614 const MachineRegisterInfo &MRI = MF.getRegInfo();
615 if (const LegalizerInfo *MLI = MF.getSubtarget().getLegalizerInfo()) {
616 for (MachineBasicBlock &MBB : MF) {
617 for (MachineInstr &MI : MBB) {
618 if (isPreISelGenericOpcode(MI.getOpcode()) && !MLI->isLegal(MI, MRI)) {
619 reportGISelFailure(MF, *TPC, *MORE, "gisel-regbankselect",
620 "instruction is not legal", MI);
621 return false;
622 }
623 }
624 }
625 }
612 // FIXME: This should be in the MachineVerifier.
613 if (!DisableGISelLegalityCheck)
614 if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
615 reportGISelFailure(MF, *TPC, *MORE, "gisel-regbankselect",
616 "instruction is not legal", *MI);
617 return false;
618 }
626619 #endif
627620
628621 // Walk the function and assign register banks to all operands.
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple aarch64-apple-ios -run-pass instruction-select %s \
2 # RUN: -disable-gisel-legality-check -verify-machineinstrs -simplify-mir \
3 # RUN: -o - | FileCheck %s
4 ---
5 name: test_rule14_id188_at_idx1067
6 alignment: 2
7 legalized: true
8 regBankSelected: true
9 tracksRegLiveness: true
10 registers:
11 - { id: 0, class: fpr }
12 - { id: 1, class: fpr }
13 liveins:
14 - { reg: '$d0', virtual-reg: '%1' }
15 body: |
16 bb.0.entry:
17 liveins: $d0
18
19 ; CHECK-LABEL: name: test_rule14_id188_at_idx1067
20 ; CHECK: liveins: $d0
21 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
22 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
23 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
24 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
25 %1:fpr(p0) = COPY $d0
26 %0:fpr(s128) = G_LOAD %1(p0) :: (load 16)
27 $noreg = PATCHABLE_RET %0(s128)
28
29 ...
30 ---
31 name: test_rule21_id2237_at_idx1449
32 alignment: 2
33 legalized: true
34 regBankSelected: true
35 tracksRegLiveness: true
36 registers:
37 - { id: 0, class: fpr }
38 - { id: 1, class: fpr }
39 liveins:
40 - { reg: '$d0', virtual-reg: '%0' }
41 - { reg: '$d1', virtual-reg: '%1' }
42 body: |
43 bb.0.entry:
44 liveins: $d0, $d1
45
46 ; CHECK-LABEL: name: test_rule21_id2237_at_idx1449
47 ; CHECK: liveins: $d0, $d1
48 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
49 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
50 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
51 ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8)
52 ; CHECK: $noreg = PATCHABLE_RET
53 %1:fpr(p0) = COPY $d1
54 %0:fpr(<8 x s8>) = COPY $d0
55 G_STORE %0(<8 x s8>), %1(p0) :: (store 8)
56 $noreg = PATCHABLE_RET
57
58 ...
59 ---
60 name: test_rule22_id2238_at_idx1505
61 alignment: 2
62 legalized: true
63 regBankSelected: true
64 tracksRegLiveness: true
65 registers:
66 - { id: 0, class: fpr }
67 - { id: 1, class: fpr }
68 liveins:
69 - { reg: '$d0', virtual-reg: '%0' }
70 - { reg: '$d1', virtual-reg: '%1' }
71 body: |
72 bb.0.entry:
73 liveins: $d0, $d1
74
75 ; CHECK-LABEL: name: test_rule22_id2238_at_idx1505
76 ; CHECK: liveins: $d0, $d1
77 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
78 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
79 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
80 ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8)
81 ; CHECK: $noreg = PATCHABLE_RET
82 %1:fpr(p0) = COPY $d1
83 %0:fpr(<4 x s16>) = COPY $d0
84 G_STORE %0(<4 x s16>), %1(p0) :: (store 8)
85 $noreg = PATCHABLE_RET
86
87 ...
88 ---
89 name: test_rule27_id2243_at_idx1781
90 alignment: 2
91 legalized: true
92 regBankSelected: true
93 tracksRegLiveness: true
94 registers:
95 - { id: 0, class: fpr }
96 - { id: 1, class: fpr }
97 liveins:
98 - { reg: '$q0', virtual-reg: '%0' }
99 - { reg: '$d0', virtual-reg: '%1' }
100 body: |
101 bb.0.entry:
102 liveins: $q0, $d0
103
104 ; CHECK-LABEL: name: test_rule27_id2243_at_idx1781
105 ; CHECK: liveins: $q0, $d0
106 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
107 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
108 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
109 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
110 ; CHECK: $noreg = PATCHABLE_RET
111 %1:fpr(p0) = COPY $d0
112 %0:fpr(<4 x s32>) = COPY $q0
113 G_STORE %0(<4 x s32>), %1(p0) :: (store 16)
114 $noreg = PATCHABLE_RET
115
116 ...
117 ---
118 name: test_rule28_id2244_at_idx1837
119 alignment: 2
120 legalized: true
121 regBankSelected: true
122 tracksRegLiveness: true
123 registers:
124 - { id: 0, class: fpr }
125 - { id: 1, class: fpr }
126 liveins:
127 - { reg: '$q0', virtual-reg: '%0' }
128 - { reg: '$d0', virtual-reg: '%1' }
129 body: |
130 bb.0.entry:
131 liveins: $q0, $d0
132
133 ; CHECK-LABEL: name: test_rule28_id2244_at_idx1837
134 ; CHECK: liveins: $q0, $d0
135 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
136 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
137 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
138 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
139 ; CHECK: $noreg = PATCHABLE_RET
140 %1:fpr(p0) = COPY $d0
141 %0:fpr(<2 x s64>) = COPY $q0
142 G_STORE %0(<2 x s64>), %1(p0) :: (store 16)
143 $noreg = PATCHABLE_RET
144
145 ...
146 ---
147 name: test_rule29_id2245_at_idx1893
148 alignment: 2
149 legalized: true
150 regBankSelected: true
151 tracksRegLiveness: true
152 registers:
153 - { id: 0, class: fpr }
154 - { id: 1, class: fpr }
155 liveins:
156 - { reg: '$q0', virtual-reg: '%0' }
157 - { reg: '$d0', virtual-reg: '%1' }
158 body: |
159 bb.0.entry:
160 liveins: $q0, $d0
161
162 ; CHECK-LABEL: name: test_rule29_id2245_at_idx1893
163 ; CHECK: liveins: $q0, $d0
164 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
165 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
166 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
167 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
168 ; CHECK: $noreg = PATCHABLE_RET
169 %1:fpr(p0) = COPY $d0
170 %0:fpr(<16 x s8>) = COPY $q0
171 G_STORE %0(<16 x s8>), %1(p0) :: (store 16)
172 $noreg = PATCHABLE_RET
173
174 ...
175 ---
176 name: test_rule30_id2246_at_idx1949
177 alignment: 2
178 legalized: true
179 regBankSelected: true
180 tracksRegLiveness: true
181 registers:
182 - { id: 0, class: fpr }
183 - { id: 1, class: fpr }
184 liveins:
185 - { reg: '$q0', virtual-reg: '%0' }
186 - { reg: '$d0', virtual-reg: '%1' }
187 body: |
188 bb.0.entry:
189 liveins: $q0, $d0
190
191 ; CHECK-LABEL: name: test_rule30_id2246_at_idx1949
192 ; CHECK: liveins: $q0, $d0
193 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
194 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
195 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
196 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
197 ; CHECK: $noreg = PATCHABLE_RET
198 %1:fpr(p0) = COPY $d0
199 %0:fpr(<8 x s16>) = COPY $q0
200 G_STORE %0(<8 x s16>), %1(p0) :: (store 16)
201 $noreg = PATCHABLE_RET
202
203 ...
204 ---
205 name: test_rule34_id2250_at_idx2173
206 alignment: 2
207 legalized: true
208 regBankSelected: true
209 tracksRegLiveness: true
210 registers:
211 - { id: 0, class: fpr }
212 - { id: 1, class: fpr }
213 liveins:
214 - { reg: '$q0', virtual-reg: '%0' }
215 - { reg: '$d0', virtual-reg: '%1' }
216 body: |
217 bb.0.entry:
218 liveins: $q0, $d0
219
220 ; CHECK-LABEL: name: test_rule34_id2250_at_idx2173
221 ; CHECK: liveins: $q0, $d0
222 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
223 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
224 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
225 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
226 ; CHECK: $noreg = PATCHABLE_RET
227 %1:fpr(p0) = COPY $d0
228 %0:fpr(s128) = COPY $q0
229 G_STORE %0(s128), %1(p0) :: (store 16)
230 $noreg = PATCHABLE_RET
231
232 ...
233 ---
234 name: test_rule92_id2150_at_idx7770
235 alignment: 2
236 legalized: true
237 regBankSelected: true
238 tracksRegLiveness: true
239 registers:
240 - { id: 0, class: fpr }
241 - { id: 1, class: gpr }
242 - { id: 2, class: gpr }
243 liveins:
244 - { reg: '$x0', virtual-reg: '%2' }
245 body: |
246 bb.0.entry:
247 liveins: $x0
248
249 ; CHECK-LABEL: name: test_rule92_id2150_at_idx7770
250 ; CHECK: liveins: $x0
251 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
252 ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
253 ; CHECK: $noreg = PATCHABLE_RET [[LDRBBui]]
254 %2:gpr(p0) = COPY $x0
255 %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
256 %1:gpr(s32) = G_ANYEXT %0(s1)
257 $noreg = PATCHABLE_RET %1(s32)
258
259 ...
260 ---
261 name: test_rule96_id2146_at_idx8070
262 alignment: 2
263 legalized: true
264 regBankSelected: true
265 tracksRegLiveness: true
266 registers:
267 - { id: 0, class: fpr }
268 - { id: 1, class: gpr }
269 - { id: 2, class: gpr }
270 liveins:
271 - { reg: '$x0', virtual-reg: '%2' }
272 body: |
273 bb.0.entry:
274 liveins: $x0
275
276 ; CHECK-LABEL: name: test_rule96_id2146_at_idx8070
277 ; CHECK: liveins: $x0
278 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
279 ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
280 ; CHECK: $noreg = PATCHABLE_RET [[LDRBBui]]
281 %2:gpr(p0) = COPY $x0
282 %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
283 %1:gpr(s32) = G_ZEXT %0(s1)
284 $noreg = PATCHABLE_RET %1(s32)
285
286 ...
287 ---
288 name: test_rule129_id2130_at_idx10828
289 alignment: 2
290 legalized: true
291 regBankSelected: true
292 tracksRegLiveness: true
293 registers:
294 - { id: 0, class: fpr }
295 - { id: 1, class: fpr }
296 liveins:
297 - { reg: '$d0', virtual-reg: '%1' }
298 body: |
299 bb.0.entry:
300 liveins: $d0
301
302 ; CHECK-LABEL: name: test_rule129_id2130_at_idx10828
303 ; CHECK: liveins: $d0
304 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
305 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
306 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8)
307 ; CHECK: $noreg = PATCHABLE_RET [[LDRDui]]
308 %1:fpr(p0) = COPY $d0
309 %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load 8)
310 $noreg = PATCHABLE_RET %0(<8 x s8>)
311
312 ...
313 ---
314 name: test_rule130_id2131_at_idx10884
315 alignment: 2
316 legalized: true
317 regBankSelected: true
318 tracksRegLiveness: true
319 registers:
320 - { id: 0, class: fpr }
321 - { id: 1, class: fpr }
322 liveins:
323 - { reg: '$d0', virtual-reg: '%1' }
324 body: |
325 bb.0.entry:
326 liveins: $d0
327
328 ; CHECK-LABEL: name: test_rule130_id2131_at_idx10884
329 ; CHECK: liveins: $d0
330 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
331 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
332 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8)
333 ; CHECK: $noreg = PATCHABLE_RET [[LDRDui]]
334 %1:fpr(p0) = COPY $d0
335 %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8)
336 $noreg = PATCHABLE_RET %0(<4 x s16>)
337
338 ...
339 ---
340 name: test_rule135_id2136_at_idx11160
341 alignment: 2
342 legalized: true
343 regBankSelected: true
344 tracksRegLiveness: true
345 registers:
346 - { id: 0, class: fpr }
347 - { id: 1, class: fpr }
348 liveins:
349 - { reg: '$d0', virtual-reg: '%1' }
350 body: |
351 bb.0.entry:
352 liveins: $d0
353
354 ; CHECK-LABEL: name: test_rule135_id2136_at_idx11160
355 ; CHECK: liveins: $d0
356 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
357 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
358 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
359 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
360 %1:fpr(p0) = COPY $d0
361 %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16)
362 $noreg = PATCHABLE_RET %0(<4 x s32>)
363
364 ...
365 ---
366 name: test_rule136_id2137_at_idx11216
367 alignment: 2
368 legalized: true
369 regBankSelected: true
370 tracksRegLiveness: true
371 registers:
372 - { id: 0, class: fpr }
373 - { id: 1, class: fpr }
374 liveins:
375 - { reg: '$d0', virtual-reg: '%1' }
376 body: |
377 bb.0.entry:
378 liveins: $d0
379
380 ; CHECK-LABEL: name: test_rule136_id2137_at_idx11216
381 ; CHECK: liveins: $d0
382 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
383 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
384 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
385 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
386 %1:fpr(p0) = COPY $d0
387 %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16)
388 $noreg = PATCHABLE_RET %0(<2 x s64>)
389
390 ...
391 ---
392 name: test_rule137_id2138_at_idx11272
393 alignment: 2
394 legalized: true
395 regBankSelected: true
396 tracksRegLiveness: true
397 registers:
398 - { id: 0, class: fpr }
399 - { id: 1, class: fpr }
400 liveins:
401 - { reg: '$d0', virtual-reg: '%1' }
402 body: |
403 bb.0.entry:
404 liveins: $d0
405
406 ; CHECK-LABEL: name: test_rule137_id2138_at_idx11272
407 ; CHECK: liveins: $d0
408 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
409 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
410 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
411 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
412 %1:fpr(p0) = COPY $d0
413 %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load 16)
414 $noreg = PATCHABLE_RET %0(<16 x s8>)
415
416 ...
417 ---
418 name: test_rule138_id2139_at_idx11328
419 alignment: 2
420 legalized: true
421 regBankSelected: true
422 tracksRegLiveness: true
423 registers:
424 - { id: 0, class: fpr }
425 - { id: 1, class: fpr }
426 liveins:
427 - { reg: '$d0', virtual-reg: '%1' }
428 body: |
429 bb.0.entry:
430 liveins: $d0
431
432 ; CHECK-LABEL: name: test_rule138_id2139_at_idx11328
433 ; CHECK: liveins: $d0
434 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
435 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
436 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
437 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
438 %1:fpr(p0) = COPY $d0
439 %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16)
440 $noreg = PATCHABLE_RET %0(<8 x s16>)
441
442 ...
443 ---
444 name: test_rule339_id2369_at_idx26608
445 alignment: 2
446 legalized: true
447 regBankSelected: true
448 tracksRegLiveness: true
449 registers:
450 - { id: 0, class: fpr }
451 - { id: 1, class: fpr }
452 - { id: 2, class: fpr }
453 - { id: 3, class: fpr }
454 - { id: 4, class: fpr }
455 - { id: 5, class: fpr }
456 liveins:
457 - { reg: '$s0', virtual-reg: '%3' }
458 - { reg: '$s1', virtual-reg: '%4' }
459 - { reg: '$s2', virtual-reg: '%5' }
460 body: |
461 bb.0.entry:
462 liveins: $s0, $s1, $s2
463
464 ; CHECK-LABEL: name: test_rule339_id2369_at_idx26608
465 ; CHECK: liveins: $s0, $s1, $s2
466 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
467 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
468 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
469 ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
470 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
471 %5:fpr(s32) = COPY $s2
472 %4:fpr(s32) = COPY $s1
473 %3:fpr(s32) = COPY $s0
474 %1:fpr(s32) = G_FNEG %5
475 %0:fpr(s32) = G_FNEG %4
476 %2:fpr(s32) = G_FMA %0, %3, %1
477 $noreg = PATCHABLE_RET %2(s32)
478
479 ...
480 ---
481 name: test_rule340_id2370_at_idx26714
482 alignment: 2
483 legalized: true
484 regBankSelected: true
485 tracksRegLiveness: true
486 registers:
487 - { id: 0, class: fpr }
488 - { id: 1, class: fpr }
489 - { id: 2, class: fpr }
490 - { id: 3, class: fpr }
491 - { id: 4, class: fpr }
492 - { id: 5, class: fpr }
493 liveins:
494 - { reg: '$d0', virtual-reg: '%3' }
495 - { reg: '$d1', virtual-reg: '%4' }
496 - { reg: '$d2', virtual-reg: '%5' }
497 body: |
498 bb.0.entry:
499 liveins: $d0, $d1, $d2
500
501 ; CHECK-LABEL: name: test_rule340_id2370_at_idx26714
502 ; CHECK: liveins: $d0, $d1, $d2
503 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
504 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
505 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
506 ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
507 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
508 %5:fpr(s64) = COPY $d2
509 %4:fpr(s64) = COPY $d1
510 %3:fpr(s64) = COPY $d0
511 %1:fpr(s64) = G_FNEG %5
512 %0:fpr(s64) = G_FNEG %4
513 %2:fpr(s64) = G_FMA %0, %3, %1
514 $noreg = PATCHABLE_RET %2(s64)
515
516 ...
517 ---
518 name: test_rule341_id2371_at_idx26820
519 alignment: 2
520 legalized: true
521 regBankSelected: true
522 tracksRegLiveness: true
523 registers:
524 - { id: 0, class: fpr }
525 - { id: 1, class: fpr }
526 - { id: 2, class: fpr }
527 - { id: 3, class: fpr }
528 - { id: 4, class: fpr }
529 - { id: 5, class: fpr }
530 liveins:
531 - { reg: '$s0', virtual-reg: '%3' }
532 - { reg: '$s1', virtual-reg: '%4' }
533 - { reg: '$s2', virtual-reg: '%5' }
534 body: |
535 bb.0.entry:
536 liveins: $s0, $s1, $s2
537
538 ; CHECK-LABEL: name: test_rule341_id2371_at_idx26820
539 ; CHECK: liveins: $s0, $s1, $s2
540 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
541 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
542 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
543 ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]]
544 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
545 %5:fpr(s32) = COPY $s2
546 %4:fpr(s32) = COPY $s1
547 %3:fpr(s32) = COPY $s0
548 %1:fpr(s32) = G_FNEG %5
549 %0:fpr(s32) = G_FNEG %4
550 %2:fpr(s32) = G_FMA %3, %0, %1
551 $noreg = PATCHABLE_RET %2(s32)
552
553 ...
554 ---
555 name: test_rule342_id2372_at_idx26926
556 alignment: 2
557 legalized: true
558 regBankSelected: true
559 tracksRegLiveness: true
560 registers:
561 - { id: 0, class: fpr }
562 - { id: 1, class: fpr }
563 - { id: 2, class: fpr }
564 - { id: 3, class: fpr }
565 - { id: 4, class: fpr }
566 - { id: 5, class: fpr }
567 liveins:
568 - { reg: '$d0', virtual-reg: '%3' }
569 - { reg: '$d1', virtual-reg: '%4' }
570 - { reg: '$d2', virtual-reg: '%5' }
571 body: |
572 bb.0.entry:
573 liveins: $d0, $d1, $d2
574
575 ; CHECK-LABEL: name: test_rule342_id2372_at_idx26926
576 ; CHECK: liveins: $d0, $d1, $d2
577 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
578 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
579 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
580 ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]]
581 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
582 %5:fpr(s64) = COPY $d2
583 %4:fpr(s64) = COPY $d1
584 %3:fpr(s64) = COPY $d0
585 %1:fpr(s64) = G_FNEG %5
586 %0:fpr(s64) = G_FNEG %4
587 %2:fpr(s64) = G_FMA %3, %0, %1
588 $noreg = PATCHABLE_RET %2(s64)
589
590 ...
591 ---
592 name: test_rule343_id1266_at_idx27032
593 alignment: 2
594 legalized: true
595 regBankSelected: true
596 tracksRegLiveness: true
597 registers:
598 - { id: 0, class: fpr }
599 - { id: 1, class: fpr }
600 - { id: 2, class: fpr }
601 - { id: 3, class: fpr }
602 - { id: 4, class: fpr }
603 liveins:
604 - { reg: '$d0', virtual-reg: '%3' }
605 - { reg: '$d1', virtual-reg: '%4' }
606 body: |
607 bb.0.entry:
608 liveins: $d0, $d1
609
610 ; CHECK-LABEL: name: test_rule343_id1266_at_idx27032
611 ; CHECK: liveins: $d0, $d1
612 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
613 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
614 ; CHECK: [[SADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDLv8i8_v8i16 [[COPY1]], [[COPY]]
615 ; CHECK: $noreg = PATCHABLE_RET [[SADDLv8i8_v8i16_]]
616 %4:fpr(<8 x s8>) = COPY $d1
617 %3:fpr(<8 x s8>) = COPY $d0
618 %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
619 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
620 %2:fpr(<8 x s16>) = G_ADD %0, %1
621 $noreg = PATCHABLE_RET %2(<8 x s16>)
622
623 ...
624 ---
625 name: test_rule344_id1268_at_idx27128
626 alignment: 2
627 legalized: true
628 regBankSelected: true
629 tracksRegLiveness: true
630 registers:
631 - { id: 0, class: fpr }
632 - { id: 1, class: fpr }
633 - { id: 2, class: fpr }
634 - { id: 3, class: fpr }
635 - { id: 4, class: fpr }
636 liveins:
637 - { reg: '$d0', virtual-reg: '%3' }
638 - { reg: '$d1', virtual-reg: '%4' }
639 body: |
640 bb.0.entry:
641 liveins: $d0, $d1
642
643 ; CHECK-LABEL: name: test_rule344_id1268_at_idx27128
644 ; CHECK: liveins: $d0, $d1
645 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
646 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
647 ; CHECK: [[SADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDLv4i16_v4i32 [[COPY1]], [[COPY]]
648 ; CHECK: $noreg = PATCHABLE_RET [[SADDLv4i16_v4i32_]]
649 %4:fpr(<4 x s16>) = COPY $d1
650 %3:fpr(<4 x s16>) = COPY $d0
651 %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)
652 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
653 %2:fpr(<4 x s32>) = G_ADD %0, %1
654 $noreg = PATCHABLE_RET %2(<4 x s32>)
655
656 ...
657 ---
658 name: test_rule345_id1270_at_idx27224
659 alignment: 2
660 legalized: true
661 regBankSelected: true
662 tracksRegLiveness: true
663 registers:
664 - { id: 0, class: fpr }
665 - { id: 1, class: fpr }
666 - { id: 2, class: fpr }
667 - { id: 3, class: fpr }
668 - { id: 4, class: fpr }
669 liveins:
670 - { reg: '$d0', virtual-reg: '%3' }
671 - { reg: '$d1', virtual-reg: '%4' }
672 body: |
673 bb.0.entry:
674 liveins: $d0, $d1
675
676 ; CHECK-LABEL: name: test_rule345_id1270_at_idx27224
677 ; CHECK: liveins: $d0, $d1
678 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
679 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
680 ; CHECK: [[SADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDLv2i32_v2i64 [[COPY1]], [[COPY]]
681 ; CHECK: $noreg = PATCHABLE_RET [[SADDLv2i32_v2i64_]]
682 %4:fpr(<2 x s32>) = COPY $d1
683 %3:fpr(<2 x s32>) = COPY $d0
684 %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)
685 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
686 %2:fpr(<2 x s64>) = G_ADD %0, %1
687 $noreg = PATCHABLE_RET %2(<2 x s64>)
688
689 ...
690 ---
691 name: test_rule346_id1326_at_idx27320
692 alignment: 2
693 legalized: true
694 regBankSelected: true
695 tracksRegLiveness: true
696 registers:
697 - { id: 0, class: fpr }
698 - { id: 1, class: fpr }
699 - { id: 2, class: fpr }
700 - { id: 3, class: fpr }
701 - { id: 4, class: fpr }
702 liveins:
703 - { reg: '$d0', virtual-reg: '%3' }
704 - { reg: '$d1', virtual-reg: '%4' }
705 body: |
706 bb.0.entry:
707 liveins: $d0, $d1
708
709 ; CHECK-LABEL: name: test_rule346_id1326_at_idx27320
710 ; CHECK: liveins: $d0, $d1
711 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
712 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
713 ; CHECK: [[UADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDLv8i8_v8i16 [[COPY1]], [[COPY]]
714 ; CHECK: $noreg = PATCHABLE_RET [[UADDLv8i8_v8i16_]]
715 %4:fpr(<8 x s8>) = COPY $d1
716 %3:fpr(<8 x s8>) = COPY $d0
717 %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)
718 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
719 %2:fpr(<8 x s16>) = G_ADD %0, %1
720 $noreg = PATCHABLE_RET %2(<8 x s16>)
721
722 ...
723 ---
724 name: test_rule347_id1328_at_idx27416
725 alignment: 2
726 legalized: true
727 regBankSelected: true
728 tracksRegLiveness: true
729 registers:
730 - { id: 0, class: fpr }
731 - { id: 1, class: fpr }
732 - { id: 2, class: fpr }
733 - { id: 3, class: fpr }
734 - { id: 4, class: fpr }
735 liveins:
736 - { reg: '$d0', virtual-reg: '%3' }
737 - { reg: '$d1', virtual-reg: '%4' }
738 body: |
739 bb.0.entry:
740 liveins: $d0, $d1
741
742 ; CHECK-LABEL: name: test_rule347_id1328_at_idx27416
743 ; CHECK: liveins: $d0, $d1
744 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
745 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
746 ; CHECK: [[UADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDLv4i16_v4i32 [[COPY1]], [[COPY]]
747 ; CHECK: $noreg = PATCHABLE_RET [[UADDLv4i16_v4i32_]]
748 %4:fpr(<4 x s16>) = COPY $d1
749 %3:fpr(<4 x s16>) = COPY $d0
750 %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)
751 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
752 %2:fpr(<4 x s32>) = G_ADD %0, %1
753 $noreg = PATCHABLE_RET %2(<4 x s32>)
754
755 ...
756 ---
757 name: test_rule348_id1330_at_idx27512
758 alignment: 2
759 legalized: true
760 regBankSelected: true
761 tracksRegLiveness: true
762 registers:
763 - { id: 0, class: fpr }
764 - { id: 1, class: fpr }
765 - { id: 2, class: fpr }
766 - { id: 3, class: fpr }
767 - { id: 4, class: fpr }
768 liveins:
769 - { reg: '$d0', virtual-reg: '%3' }
770 - { reg: '$d1', virtual-reg: '%4' }
771 body: |
772 bb.0.entry:
773 liveins: $d0, $d1
774
775 ; CHECK-LABEL: name: test_rule348_id1330_at_idx27512
776 ; CHECK: liveins: $d0, $d1
777 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
778 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
779 ; CHECK: [[UADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDLv2i32_v2i64 [[COPY1]], [[COPY]]
780 ; CHECK: $noreg = PATCHABLE_RET [[UADDLv2i32_v2i64_]]
781 %4:fpr(<2 x s32>) = COPY $d1
782 %3:fpr(<2 x s32>) = COPY $d0
783 %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)
784 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
785 %2:fpr(<2 x s64>) = G_ADD %0, %1
786 $noreg = PATCHABLE_RET %2(<2 x s64>)
787
788 ...
789 ---
790 name: test_rule349_id1308_at_idx27608
791 alignment: 2
792 legalized: true
793 regBankSelected: true
794 tracksRegLiveness: true
795 registers:
796 - { id: 0, class: fpr }
797 - { id: 1, class: fpr }
798 - { id: 2, class: fpr }
799 - { id: 3, class: fpr }
800 - { id: 4, class: fpr }
801 liveins:
802 - { reg: '$d0', virtual-reg: '%3' }
803 - { reg: '$d1', virtual-reg: '%4' }
804 body: |
805 bb.0.entry:
806 liveins: $d0, $d1
807
808 ; CHECK-LABEL: name: test_rule349_id1308_at_idx27608
809 ; CHECK: liveins: $d0, $d1
810 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
811 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
812 ; CHECK: [[SSUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBLv8i8_v8i16 [[COPY1]], [[COPY]]
813 ; CHECK: $noreg = PATCHABLE_RET [[SSUBLv8i8_v8i16_]]
814 %4:fpr(<8 x s8>) = COPY $d1
815 %3:fpr(<8 x s8>) = COPY $d0
816 %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
817 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
818 %2:fpr(<8 x s16>) = G_SUB %0, %1
819 $noreg = PATCHABLE_RET %2(<8 x s16>)
820
821 ...
822 ---
823 name: test_rule350_id1310_at_idx27704
824 alignment: 2
825 legalized: true
826 regBankSelected: true
827 tracksRegLiveness: true
828 registers:
829 - { id: 0, class: fpr }
830 - { id: 1, class: fpr }
831 - { id: 2, class: fpr }
832 - { id: 3, class: fpr }
833 - { id: 4, class: fpr }
834 liveins:
835 - { reg: '$d0', virtual-reg: '%3' }
836 - { reg: '$d1', virtual-reg: '%4' }
837 body: |
838 bb.0.entry:
839 liveins: $d0, $d1
840
841 ; CHECK-LABEL: name: test_rule350_id1310_at_idx27704
842 ; CHECK: liveins: $d0, $d1
843 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
844 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
845 ; CHECK: [[SSUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBLv4i16_v4i32 [[COPY1]], [[COPY]]
846 ; CHECK: $noreg = PATCHABLE_RET [[SSUBLv4i16_v4i32_]]
847 %4:fpr(<4 x s16>) = COPY $d1
848 %3:fpr(<4 x s16>) = COPY $d0
849 %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)
850 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
851 %2:fpr(<4 x s32>) = G_SUB %0, %1
852 $noreg = PATCHABLE_RET %2(<4 x s32>)
853
854 ...
855 ---
856 name: test_rule351_id1312_at_idx27800
857 alignment: 2
858 legalized: true
859 regBankSelected: true
860 tracksRegLiveness: true
861 registers:
862 - { id: 0, class: fpr }
863 - { id: 1, class: fpr }
864 - { id: 2, class: fpr }
865 - { id: 3, class: fpr }
866 - { id: 4, class: fpr }
867 liveins:
868 - { reg: '$d0', virtual-reg: '%3' }
869 - { reg: '$d1', virtual-reg: '%4' }
870 body: |
871 bb.0.entry:
872 liveins: $d0, $d1
873
874 ; CHECK-LABEL: name: test_rule351_id1312_at_idx27800
875 ; CHECK: liveins: $d0, $d1
876 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
877 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
878 ; CHECK: [[SSUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBLv2i32_v2i64 [[COPY1]], [[COPY]]
879 ; CHECK: $noreg = PATCHABLE_RET [[SSUBLv2i32_v2i64_]]
880 %4:fpr(<2 x s32>) = COPY $d1
881 %3:fpr(<2 x s32>) = COPY $d0
882 %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)
883 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
884 %2:fpr(<2 x s64>) = G_SUB %0, %1
885 $noreg = PATCHABLE_RET %2(<2 x s64>)
886
887 ...
888 ---
889 name: test_rule352_id1356_at_idx27896
890 alignment: 2
891 legalized: true
892 regBankSelected: true
893 tracksRegLiveness: true
894 registers:
895 - { id: 0, class: fpr }
896 - { id: 1, class: fpr }
897 - { id: 2, class: fpr }
898 - { id: 3, class: fpr }
899 - { id: 4, class: fpr }
900 liveins:
901 - { reg: '$d0', virtual-reg: '%3' }
902 - { reg: '$d1', virtual-reg: '%4' }
903 body: |
904 bb.0.entry:
905 liveins: $d0, $d1
906
907 ; CHECK-LABEL: name: test_rule352_id1356_at_idx27896
908 ; CHECK: liveins: $d0, $d1
909 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
910 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
911 ; CHECK: [[USUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBLv8i8_v8i16 [[COPY1]], [[COPY]]
912 ; CHECK: $noreg = PATCHABLE_RET [[USUBLv8i8_v8i16_]]
913 %4:fpr(<8 x s8>) = COPY $d1
914 %3:fpr(<8 x s8>) = COPY $d0
915 %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)
916 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
917 %2:fpr(<8 x s16>) = G_SUB %0, %1
918 $noreg = PATCHABLE_RET %2(<8 x s16>)
919
920 ...
921 ---
922 name: test_rule353_id1358_at_idx27992
923 alignment: 2
924 legalized: true
925 regBankSelected: true
926 tracksRegLiveness: true
927 registers:
928 - { id: 0, class: fpr }
929 - { id: 1, class: fpr }
930 - { id: 2, class: fpr }
931 - { id: 3, class: fpr }
932 - { id: 4, class: fpr }
933 liveins:
934 - { reg: '$d0', virtual-reg: '%3' }
935 - { reg: '$d1', virtual-reg: '%4' }
936 body: |
937 bb.0.entry:
938 liveins: $d0, $d1
939
940 ; CHECK-LABEL: name: test_rule353_id1358_at_idx27992
941 ; CHECK: liveins: $d0, $d1
942 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
943 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
944 ; CHECK: [[USUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBLv4i16_v4i32 [[COPY1]], [[COPY]]
945 ; CHECK: $noreg = PATCHABLE_RET [[USUBLv4i16_v4i32_]]
946 %4:fpr(<4 x s16>) = COPY $d1
947 %3:fpr(<4 x s16>) = COPY $d0
948 %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)
949 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
950 %2:fpr(<4 x s32>) = G_SUB %0, %1
951 $noreg = PATCHABLE_RET %2(<4 x s32>)
952
953 ...
954 ---
955 name: test_rule354_id1360_at_idx28088
956 alignment: 2
957 legalized: true
958 regBankSelected: true
959 tracksRegLiveness: true
960 registers:
961 - { id: 0, class: fpr }
962 - { id: 1, class: fpr }
963 - { id: 2, class: fpr }
964 - { id: 3, class: fpr }
965 - { id: 4, class: fpr }
966 liveins:
967 - { reg: '$d0', virtual-reg: '%3' }
968 - { reg: '$d1', virtual-reg: '%4' }
969 body: |
970 bb.0.entry:
971 liveins: $d0, $d1
972
973 ; CHECK-LABEL: name: test_rule354_id1360_at_idx28088
974 ; CHECK: liveins: $d0, $d1
975 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
976 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
977 ; CHECK: [[USUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBLv2i32_v2i64 [[COPY1]], [[COPY]]
978 ; CHECK: $noreg = PATCHABLE_RET [[USUBLv2i32_v2i64_]]
979 %4:fpr(<2 x s32>) = COPY $d1
980 %3:fpr(<2 x s32>) = COPY $d0
981 %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)
982 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
983 %2:fpr(<2 x s64>) = G_SUB %0, %1
984 $noreg = PATCHABLE_RET %2(<2 x s64>)
985
986 ...
987 ---
988 name: test_rule928_id2367_at_idx60019
989 alignment: 2
990 legalized: true
991 regBankSelected: true
992 tracksRegLiveness: true
993 registers:
994 - { id: 0, class: fpr }
995 - { id: 1, class: fpr }
996 - { id: 2, class: fpr }
997 - { id: 3, class: fpr }
998 - { id: 4, class: fpr }
999 liveins:
1000 - { reg: '$s0', virtual-reg: '%2' }
1001 - { reg: '$s1', virtual-reg: '%3' }
1002 - { reg: '$s2', virtual-reg: '%4' }
1003 body: |
1004 bb.0.entry:
1005 liveins: $s0, $s1, $s2
1006
1007 ; CHECK-LABEL: name: test_rule928_id2367_at_idx60019
1008 ; CHECK: liveins: $s0, $s1, $s2
1009 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
1010 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
1011 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
1012 ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]]
1013 ; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
1014 %4:fpr(s32) = COPY $s2
1015 %3:fpr(s32) = COPY $s1
1016 %2:fpr(s32) = COPY $s0
1017 %0:fpr(s32) = G_FNEG %4
1018 %1:fpr(s32) = G_FMA %0, %2, %3
1019 $noreg = PATCHABLE_RET %1(s32)
1020
1021 ...
1022 ---
1023 name: test_rule929_id2368_at_idx60105
1024 alignment: 2
1025 legalized: true
1026 regBankSelected: true
1027 tracksRegLiveness: true
1028 registers:
1029 - { id: 0, class: fpr }
1030 - { id: 1, class: fpr }
1031 - { id: 2, class: fpr }
1032 - { id: 3, class: fpr }
1033 - { id: 4, class: fpr }
1034 liveins:
1035 - { reg: '$d0', virtual-reg: '%2' }
1036 - { reg: '$d1', virtual-reg: '%3' }
1037 - { reg: '$d2', virtual-reg: '%4' }
1038 body: |
1039 bb.0.entry:
1040 liveins: $d0, $d1, $d2
1041
1042 ; CHECK-LABEL: name: test_rule929_id2368_at_idx60105
1043 ; CHECK: liveins: $d0, $d1, $d2
1044 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
1045 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
1046 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
1047 ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]]
1048 ; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
1049 %4:fpr(s64) = COPY $d2
1050 %3:fpr(s64) = COPY $d1
1051 %2:fpr(s64) = COPY $d0
1052 %0:fpr(s64) = G_FNEG %4
1053 %1:fpr(s64) = G_FMA %0, %2, %3
1054 $noreg = PATCHABLE_RET %1(s64)
1055
1056 ...
1057 ---
1058 name: test_rule930_id2446_at_idx60191
1059 alignment: 2
1060 legalized: true
1061 regBankSelected: true
1062 tracksRegLiveness: true
1063 registers:
1064 - { id: 0, class: fpr }
1065 - { id: 1, class: fpr }
1066 - { id: 2, class: fpr }
1067 - { id: 3, class: fpr }
1068 - { id: 4, class: fpr }
1069 liveins:
1070 - { reg: '$d0', virtual-reg: '%2' }
1071 - { reg: '$d1', virtual-reg: '%3' }
1072 - { reg: '$d2', virtual-reg: '%4' }
1073 body: |
1074 bb.0.entry:
1075 liveins: $d0, $d1, $d2
1076
1077 ; CHECK-LABEL: name: test_rule930_id2446_at_idx60191
1078 ; CHECK: liveins: $d0, $d1, $d2
1079 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
1080 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
1081 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
1082 ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY]], [[COPY2]]
1083 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
1084 %4:fpr(<2 x s32>) = COPY $d2
1085 %3:fpr(<2 x s32>) = COPY $d1
1086 %2:fpr(<2 x s32>) = COPY $d0
1087 %0:fpr(<2 x s32>) = G_FNEG %4
1088 %1:fpr(<2 x s32>) = G_FMA %0, %2, %3
1089 $noreg = PATCHABLE_RET %1(<2 x s32>)
1090
1091 ...
1092 ---
1093 name: test_rule931_id2447_at_idx60277
1094 alignment: 2
1095 legalized: true
1096 regBankSelected: true
1097 tracksRegLiveness: true
1098 registers:
1099 - { id: 0, class: fpr }
1100 - { id: 1, class: fpr }
1101 - { id: 2, class: fpr }
1102 - { id: 3, class: fpr }
1103 - { id: 4, class: fpr }
1104 liveins:
1105 - { reg: '$q0', virtual-reg: '%2' }
1106 - { reg: '$q1', virtual-reg: '%3' }
1107 - { reg: '$q2', virtual-reg: '%4' }
1108 body: |
1109 bb.0.entry:
1110 liveins: $q0, $q1, $q2
1111
1112 ; CHECK-LABEL: name: test_rule931_id2447_at_idx60277
1113 ; CHECK: liveins: $q0, $q1, $q2
1114 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
1115 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
1116 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
1117 ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY]], [[COPY2]]
1118 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
1119 %4:fpr(<4 x s32>) = COPY $q2
1120 %3:fpr(<4 x s32>) = COPY $q1
1121 %2:fpr(<4 x s32>) = COPY $q0
1122 %0:fpr(<4 x s32>) = G_FNEG %4
1123 %1:fpr(<4 x s32>) = G_FMA %0, %2, %3
1124 $noreg = PATCHABLE_RET %1(<4 x s32>)
1125
1126 ...
1127 ---
1128 name: test_rule932_id2448_at_idx60363
1129 alignment: 2
1130 legalized: true
1131 regBankSelected: true
1132 tracksRegLiveness: true
1133 registers:
1134 - { id: 0, class: fpr }
1135 - { id: 1, class: fpr }
1136 - { id: 2, class: fpr }
1137 - { id: 3, class: fpr }
1138 - { id: 4, class: fpr }
1139 liveins:
1140 - { reg: '$q0', virtual-reg: '%2' }
1141 - { reg: '$q1', virtual-reg: '%3' }
1142 - { reg: '$q2', virtual-reg: '%4' }
1143 body: |
1144 bb.0.entry:
1145 liveins: $q0, $q1, $q2
1146
1147 ; CHECK-LABEL: name: test_rule932_id2448_at_idx60363
1148 ; CHECK: liveins: $q0, $q1, $q2
1149 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
1150 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
1151 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
1152 ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY]], [[COPY2]]
1153 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
1154 %4:fpr(<2 x s64>) = COPY $q2
1155 %3:fpr(<2 x s64>) = COPY $q1
1156 %2:fpr(<2 x s64>) = COPY $q0
1157 %0:fpr(<2 x s64>) = G_FNEG %4
1158 %1:fpr(<2 x s64>) = G_FMA %0, %2, %3
1159 $noreg = PATCHABLE_RET %1(<2 x s64>)
1160
1161 ...
1162 ---
1163 name: test_rule934_id429_at_idx60537
1164 alignment: 2
1165 legalized: true
1166 regBankSelected: true
1167 tracksRegLiveness: true
1168 registers:
1169 - { id: 0, class: fpr }
1170 - { id: 1, class: fpr }
1171 - { id: 2, class: fpr }
1172 - { id: 3, class: fpr }
1173 - { id: 4, class: fpr }
1174 liveins:
1175 - { reg: '$s0', virtual-reg: '%2' }
1176 - { reg: '$s1', virtual-reg: '%3' }
1177 - { reg: '$s2', virtual-reg: '%4' }
1178 body: |
1179 bb.0.entry:
1180 liveins: $s0, $s1, $s2
1181
1182 ; CHECK-LABEL: name: test_rule934_id429_at_idx60537
1183 ; CHECK: liveins: $s0, $s1, $s2
1184 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
1185 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
1186 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
1187 ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]]
1188 ; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
1189 %4:fpr(s32) = COPY $s2
1190 %3:fpr(s32) = COPY $s1
1191 %2:fpr(s32) = COPY $s0
1192 %0:fpr(s32) = G_FNEG %4
1193 %1:fpr(s32) = G_FMA %2, %0, %3
1194 $noreg = PATCHABLE_RET %1(s32)
1195
1196 ...
1197 ---
1198 name: test_rule935_id430_at_idx60625
1199 alignment: 2
1200 legalized: true
1201 regBankSelected: true
1202 tracksRegLiveness: true
1203 registers:
1204 - { id: 0, class: fpr }
1205 - { id: 1, class: fpr }
1206 - { id: 2, class: fpr }
1207 - { id: 3, class: fpr }
1208 - { id: 4, class: fpr }
1209 liveins:
1210 - { reg: '$d0', virtual-reg: '%2' }
1211 - { reg: '$d1', virtual-reg: '%3' }
1212 - { reg: '$d2', virtual-reg: '%4' }
1213 body: |
1214 bb.0.entry:
1215 liveins: $d0, $d1, $d2
1216
1217 ; CHECK-LABEL: name: test_rule935_id430_at_idx60625
1218 ; CHECK: liveins: $d0, $d1, $d2
1219 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
1220 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
1221 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
1222 ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]]
1223 ; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
1224 %4:fpr(s64) = COPY $d2
1225 %3:fpr(s64) = COPY $d1
1226 %2:fpr(s64) = COPY $d0
1227 %0:fpr(s64) = G_FNEG %4
1228 %1:fpr(s64) = G_FMA %2, %0, %3
1229 $noreg = PATCHABLE_RET %1(s64)
1230
1231 ...
1232 ---
1233 name: test_rule938_id899_at_idx60889
1234 alignment: 2
1235 legalized: true
1236 regBankSelected: true
1237 tracksRegLiveness: true
1238 registers:
1239 - { id: 0, class: fpr }
1240 - { id: 1, class: fpr }
1241 - { id: 2, class: fpr }
1242 - { id: 3, class: fpr }
1243 - { id: 4, class: fpr }
1244 liveins:
1245 - { reg: '$d0', virtual-reg: '%2' }
1246 - { reg: '$d1', virtual-reg: '%3' }
1247 - { reg: '$d2', virtual-reg: '%4' }
1248 body: |
1249 bb.0.entry:
1250 liveins: $d0, $d1, $d2
1251
1252 ; CHECK-LABEL: name: test_rule938_id899_at_idx60889
1253 ; CHECK: liveins: $d0, $d1, $d2
1254 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
1255 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
1256 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
1257 ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
1258 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
1259 %4:fpr(<2 x s32>) = COPY $d2
1260 %3:fpr(<2 x s32>) = COPY $d1
1261 %2:fpr(<2 x s32>) = COPY $d0
1262 %0:fpr(<2 x s32>) = G_FNEG %4
1263 %1:fpr(<2 x s32>) = G_FMA %2, %0, %3
1264 $noreg = PATCHABLE_RET %1(<2 x s32>)
1265
1266 ...
1267 ---
1268 name: test_rule939_id900_at_idx60977
1269 alignment: 2
1270 legalized: true
1271 regBankSelected: true
1272 tracksRegLiveness: true
1273 registers:
1274 - { id: 0, class: fpr }
1275 - { id: 1, class: fpr }
1276 - { id: 2, class: fpr }
1277 - { id: 3, class: fpr }
1278 - { id: 4, class: fpr }
1279 liveins:
1280 - { reg: '$q0', virtual-reg: '%2' }
1281 - { reg: '$q1', virtual-reg: '%3' }
1282 - { reg: '$q2', virtual-reg: '%4' }
1283 body: |
1284 bb.0.entry:
1285 liveins: $q0, $q1, $q2
1286
1287 ; CHECK-LABEL: name: test_rule939_id900_at_idx60977
1288 ; CHECK: liveins: $q0, $q1, $q2
1289 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
1290 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
1291 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
1292 ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
1293 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
1294 %4:fpr(<4 x s32>) = COPY $q2
1295 %3:fpr(<4 x s32>) = COPY $q1
1296 %2:fpr(<4 x s32>) = COPY $q0
1297 %0:fpr(<4 x s32>) = G_FNEG %4
1298 %1:fpr(<4 x s32>) = G_FMA %2, %0, %3
1299 $noreg = PATCHABLE_RET %1(<4 x s32>)
1300
1301 ...
1302 ---
1303 name: test_rule940_id901_at_idx61065
1304 alignment: 2
1305 legalized: true
1306 regBankSelected: true
1307 tracksRegLiveness: true
1308 registers:
1309 - { id: 0, class: fpr }
1310 - { id: 1, class: fpr }
1311 - { id: 2, class: fpr }
1312 - { id: 3, class: fpr }
1313 - { id: 4, class: fpr }
1314 liveins:
1315 - { reg: '$q0', virtual-reg: '%2' }
1316 - { reg: '$q1', virtual-reg: '%3' }
1317 - { reg: '$q2', virtual-reg: '%4' }
1318 body: |
1319 bb.0.entry:
1320 liveins: $q0, $q1, $q2
1321
1322 ; CHECK-LABEL: name: test_rule940_id901_at_idx61065
1323 ; CHECK: liveins: $q0, $q1, $q2
1324 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
1325 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
1326 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
1327 ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
1328 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
1329 %4:fpr(<2 x s64>) = COPY $q2
1330 %3:fpr(<2 x s64>) = COPY $q1
1331 %2:fpr(<2 x s64>) = COPY $q0
1332 %0:fpr(<2 x s64>) = G_FNEG %4
1333 %1:fpr(<2 x s64>) = G_FMA %2, %0, %3
1334 $noreg = PATCHABLE_RET %1(<2 x s64>)
1335
1336 ...
1337 ---
1338 name: test_rule942_id435_at_idx61241
1339 alignment: 2
1340 legalized: true
1341 regBankSelected: true
1342 tracksRegLiveness: true
1343 registers:
1344 - { id: 0, class: fpr }
1345 - { id: 1, class: fpr }
1346 - { id: 2, class: fpr }
1347 - { id: 3, class: fpr }
1348 - { id: 4, class: fpr }
1349 liveins:
1350 - { reg: '$s0', virtual-reg: '%2' }
1351 - { reg: '$s1', virtual-reg: '%3' }
1352 - { reg: '$s2', virtual-reg: '%4' }
1353 body: |
1354 bb.0.entry:
1355 liveins: $s0, $s1, $s2
1356
1357 ; CHECK-LABEL: name: test_rule942_id435_at_idx61241
1358 ; CHECK: liveins: $s0, $s1, $s2
1359 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
1360 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
1361 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
1362 ; CHECK: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]]
1363 ; CHECK: $noreg = PATCHABLE_RET [[FNMSUBSrrr]]
1364 %4:fpr(s32) = COPY $s2
1365 %3:fpr(s32) = COPY $s1
1366 %2:fpr(s32) = COPY $s0
1367 %0:fpr(s32) = G_FNEG %4
1368 %1:fpr(s32) = G_FMA %2, %3, %0
1369 $noreg = PATCHABLE_RET %1(s32)
1370
1371 ...
1372 ---
1373 name: test_rule943_id436_at_idx61329
1374 alignment: 2
1375 legalized: true
1376 regBankSelected: true
1377 tracksRegLiveness: true
1378 registers:
1379 - { id: 0, class: fpr }
1380 - { id: 1, class: fpr }
1381 - { id: 2, class: fpr }
1382 - { id: 3, class: fpr }
1383 - { id: 4, class: fpr }
1384 liveins:
1385 - { reg: '$d0', virtual-reg: '%2' }
1386 - { reg: '$d1', virtual-reg: '%3' }
1387 - { reg: '$d2', virtual-reg: '%4' }
1388 body: |
1389 bb.0.entry:
1390 liveins: $d0, $d1, $d2
1391
1392 ; CHECK-LABEL: name: test_rule943_id436_at_idx61329
1393 ; CHECK: liveins: $d0, $d1, $d2
1394 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
1395 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
1396 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
1397 ; CHECK: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]]
1398 ; CHECK: $noreg = PATCHABLE_RET [[FNMSUBDrrr]]
1399 %4:fpr(s64) = COPY $d2
1400 %3:fpr(s64) = COPY $d1
1401 %2:fpr(s64) = COPY $d0
1402 %0:fpr(s64) = G_FNEG %4
1403 %1:fpr(s64) = G_FMA %2, %3, %0
1404 $noreg = PATCHABLE_RET %1(s64)
1405
1406 ...
1407 ---
1408 name: test_rule944_id3803_at_idx61417
1409 alignment: 2
1410 legalized: true
1411 regBankSelected: true
1412 tracksRegLiveness: true
1413 registers:
1414 - { id: 0, class: fpr }
1415 - { id: 1, class: fpr }
1416 - { id: 2, class: fpr }
1417 - { id: 3, class: fpr }
1418 - { id: 4, class: fpr }
1419 liveins:
1420 - { reg: '$d0', virtual-reg: '%2' }
1421 - { reg: '$d1', virtual-reg: '%3' }
1422 - { reg: '$d2', virtual-reg: '%4' }
1423 body: |
1424 bb.0.entry:
1425 liveins: $d0, $d1, $d2
1426
1427 ; CHECK-LABEL: name: test_rule944_id3803_at_idx61417
1428 ; CHECK: liveins: $d0, $d1, $d2
1429 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
1430 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
1431 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
1432 ; CHECK: [[MLAv8i8_:%[0-9]+]]:fpr64 = MLAv8i8 [[COPY2]], [[COPY1]], [[COPY]]
1433 ; CHECK: $noreg = PATCHABLE_RET [[MLAv8i8_]]
1434 %4:fpr(<8 x s8>) = COPY $d2
1435 %3:fpr(<8 x s8>) = COPY $d1
1436 %2:fpr(<8 x s8>) = COPY $d0
1437 %0:fpr(<8 x s8>) = G_MUL %3, %4
1438 %1:fpr(<8 x s8>) = G_ADD %0, %2
1439 $noreg = PATCHABLE_RET %1(<8 x s8>)
1440
1441 ...
1442 ---
1443 name: test_rule945_id3804_at_idx61505
1444 alignment: 2
1445 legalized: true
1446 regBankSelected: true
1447 tracksRegLiveness: true
1448 registers:
1449 - { id: 0, class: fpr }
1450 - { id: 1, class: fpr }
1451 - { id: 2, class: fpr }
1452 - { id: 3, class: fpr }
1453 - { id: 4, class: fpr }
1454 liveins:
1455 - { reg: '$q0', virtual-reg: '%2' }
1456 - { reg: '$q1', virtual-reg: '%3' }
1457 - { reg: '$q2', virtual-reg: '%4' }
1458 body: |
1459 bb.0.entry:
1460 liveins: $q0, $q1, $q2
1461
1462 ; CHECK-LABEL: name: test_rule945_id3804_at_idx61505
1463 ; CHECK: liveins: $q0, $q1, $q2
1464 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
1465 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
1466 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
1467 ; CHECK: [[MLAv16i8_:%[0-9]+]]:fpr128 = MLAv16i8 [[COPY2]], [[COPY1]], [[COPY]]
1468 ; CHECK: $noreg = PATCHABLE_RET [[MLAv16i8_]]
1469 %4:fpr(<16 x s8>) = COPY $q2
1470 %3:fpr(<16 x s8>) = COPY $q1
1471 %2:fpr(<16 x s8>) = COPY $q0
1472 %0:fpr(<16 x s8>) = G_MUL %3, %4
1473 %1:fpr(<16 x s8>) = G_ADD %0, %2
1474 $noreg = PATCHABLE_RET %1(<16 x s8>)
1475
1476 ...
1477 ---
1478 name: test_rule946_id3805_at_idx61593
1479 alignment: 2
1480 legalized: true
1481 regBankSelected: true
1482 tracksRegLiveness: true
1483 registers:
1484 - { id: 0, class: fpr }
1485 - { id: 1, class: fpr }
1486 - { id: 2, class: fpr }
1487 - { id: 3, class: fpr }
1488 - { id: 4, class: fpr }
1489 liveins:
1490 - { reg: '$d0', virtual-reg: '%2' }
1491 - { reg: '$d1', virtual-reg: '%3' }
1492 - { reg: '$d2', virtual-reg: '%4' }
1493 body: |
1494 bb.0.entry:
1495 liveins: $d0, $d1, $d2
1496
1497 ; CHECK-LABEL: name: test_rule946_id3805_at_idx61593
1498 ; CHECK: liveins: $d0, $d1, $d2
1499 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
1500 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
1501 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
1502 ; CHECK: [[MLAv4i16_:%[0-9]+]]:fpr64 = MLAv4i16 [[COPY2]], [[COPY1]], [[COPY]]
1503 ; CHECK: $noreg = PATCHABLE_RET [[MLAv4i16_]]
1504 %4:fpr(<4 x s16>) = COPY $d2
1505 %3:fpr(<4 x s16>) = COPY $d1
1506 %2:fpr(<4 x s16>) = COPY $d0
1507 %0:fpr(<4 x s16>) = G_MUL %3, %4
1508 %1:fpr(<4 x s16>) = G_ADD %0, %2
1509 $noreg = PATCHABLE_RET %1(<4 x s16>)
1510
1511 ...
1512 ---
1513 name: test_rule947_id3806_at_idx61681
1514 alignment: 2
1515 legalized: true
1516 regBankSelected: true
1517 tracksRegLiveness: true
1518 registers:
1519 - { id: 0, class: fpr }
1520 - { id: 1, class: fpr }
1521 - { id: 2, class: fpr }
1522 - { id: 3, class: fpr }
1523 - { id: 4, class: fpr }
1524 liveins:
1525 - { reg: '$q0', virtual-reg: '%2' }
1526 - { reg: '$q1', virtual-reg: '%3' }
1527 - { reg: '$q2', virtual-reg: '%4' }
1528 body: |
1529 bb.0.entry:
1530 liveins: $q0, $q1, $q2
1531
1532 ; CHECK-LABEL: name: test_rule947_id3806_at_idx61681
1533 ; CHECK: liveins: $q0, $q1, $q2
1534 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
1535 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
1536 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
1537 ; CHECK: [[MLAv8i16_:%[0-9]+]]:fpr128 = MLAv8i16 [[COPY2]], [[COPY1]], [[COPY]]
1538 ; CHECK: $noreg = PATCHABLE_RET [[MLAv8i16_]]
1539 %4:fpr(<8 x s16>) = COPY $q2
1540 %3:fpr(<8 x s16>) = COPY $q1
1541 %2:fpr(<8 x s16>) = COPY $q0
1542 %0:fpr(<8 x s16>) = G_MUL %3, %4
1543 %1:fpr(<8 x s16>) = G_ADD %0, %2
1544 $noreg = PATCHABLE_RET %1(<8 x s16>)
1545
1546 ...
1547 ---
1548 name: test_rule950_id3869_at_idx61945
1549 alignment: 2
1550 legalized: true
1551 regBankSelected: true
1552 tracksRegLiveness: true
1553 registers:
1554 - { id: 0, class: fpr }
1555 - { id: 1, class: fpr }
1556 - { id: 2, class: fpr }
1557 - { id: 3, class: fpr }
1558 liveins:
1559 - { reg: '$q0', virtual-reg: '%2' }
1560 - { reg: '$d0', virtual-reg: '%3' }
1561 body: |
1562 bb.0.entry:
1563 liveins: $q0, $d0
1564
1565 ; CHECK-LABEL: name: test_rule950_id3869_at_idx61945
1566 ; CHECK: liveins: $q0, $d0
1567 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
1568 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
1569 ; CHECK: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]]
1570 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]]
1571 %3:fpr(<8 x s8>) = COPY $d0
1572 %2:fpr(<8 x s16>) = COPY $q0
1573 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
1574 %1:fpr(<8 x s16>) = G_ADD %0, %2
1575 $noreg = PATCHABLE_RET %1(<8 x s16>)
1576
1577 ...
1578 ---
1579 name: test_rule951_id3871_at_idx62021
1580 alignment: 2
1581 legalized: true
1582 regBankSelected: true
1583 tracksRegLiveness: true
1584 registers:
1585 - { id: 0, class: fpr }
1586 - { id: 1, class: fpr }
1587 - { id: 2, class: fpr }
1588 - { id: 3, class: fpr }
1589 liveins:
1590 - { reg: '$q0', virtual-reg: '%2' }
1591 - { reg: '$d0', virtual-reg: '%3' }
1592 body: |
1593 bb.0.entry:
1594 liveins: $q0, $d0
1595
1596 ; CHECK-LABEL: name: test_rule951_id3871_at_idx62021
1597 ; CHECK: liveins: $q0, $d0
1598 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
1599 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
1600 ; CHECK: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]]
1601 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]]
1602 %3:fpr(<4 x s16>) = COPY $d0
1603 %2:fpr(<4 x s32>) = COPY $q0
1604 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
1605 %1:fpr(<4 x s32>) = G_ADD %0, %2
1606 $noreg = PATCHABLE_RET %1(<4 x s32>)
1607
1608 ...
1609 ---
1610 name: test_rule952_id3873_at_idx62097
1611 alignment: 2
1612 legalized: true
1613 regBankSelected: true
1614 tracksRegLiveness: true
1615 registers:
1616 - { id: 0, class: fpr }
1617 - { id: 1, class: fpr }
1618 - { id: 2, class: fpr }
1619 - { id: 3, class: fpr }
1620 liveins:
1621 - { reg: '$q0', virtual-reg: '%2' }
1622 - { reg: '$d0', virtual-reg: '%3' }
1623 body: |
1624 bb.0.entry:
1625 liveins: $q0, $d0
1626
1627 ; CHECK-LABEL: name: test_rule952_id3873_at_idx62097
1628 ; CHECK: liveins: $q0, $d0
1629 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
1630 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
1631 ; CHECK: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]]
1632 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]]
1633 %3:fpr(<2 x s32>) = COPY $d0
1634 %2:fpr(<2 x s64>) = COPY $q0
1635 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
1636 %1:fpr(<2 x s64>) = G_ADD %0, %2
1637 $noreg = PATCHABLE_RET %1(<2 x s64>)
1638
1639 ...
1640 ---
1641 name: test_rule953_id3887_at_idx62173
1642 alignment: 2
1643 legalized: true
1644 regBankSelected: true
1645 tracksRegLiveness: true
1646 registers:
1647 - { id: 0, class: fpr }
1648 - { id: 1, class: fpr }
1649 - { id: 2, class: fpr }
1650 - { id: 3, class: fpr }
1651 liveins:
1652 - { reg: '$q0', virtual-reg: '%2' }
1653 - { reg: '$d0', virtual-reg: '%3' }
1654 body: |
1655 bb.0.entry:
1656 liveins: $q0, $d0
1657
1658 ; CHECK-LABEL: name: test_rule953_id3887_at_idx62173
1659 ; CHECK: liveins: $q0, $d0
1660 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
1661 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
1662 ; CHECK: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]]
1663 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]]
1664 %3:fpr(<8 x s8>) = COPY $d0
1665 %2:fpr(<8 x s16>) = COPY $q0
1666 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
1667 %1:fpr(<8 x s16>) = G_ADD %0, %2
1668 $noreg = PATCHABLE_RET %1(<8 x s16>)
1669
1670 ...
1671 ---
1672 name: test_rule954_id3889_at_idx62249
1673 alignment: 2
1674 legalized: true
1675 regBankSelected: true
1676 tracksRegLiveness: true
1677 registers:
1678 - { id: 0, class: fpr }
1679 - { id: 1, class: fpr }
1680 - { id: 2, class: fpr }
1681 - { id: 3, class: fpr }
1682 liveins:
1683 - { reg: '$q0', virtual-reg: '%2' }
1684 - { reg: '$d0', virtual-reg: '%3' }
1685 body: |
1686 bb.0.entry:
1687 liveins: $q0, $d0
1688
1689 ; CHECK-LABEL: name: test_rule954_id3889_at_idx62249
1690 ; CHECK: liveins: $q0, $d0
1691 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
1692 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
1693 ; CHECK: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]]
1694 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]]
1695 %3:fpr(<4 x s16>) = COPY $d0
1696 %2:fpr(<4 x s32>) = COPY $q0
1697 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
1698 %1:fpr(<4 x s32>) = G_ADD %0, %2
1699 $noreg = PATCHABLE_RET %1(<4 x s32>)
1700
1701 ...
1702 ---
1703 name: test_rule955_id3891_at_idx62325
1704 alignment: 2
1705 legalized: true
1706 regBankSelected: true
1707 tracksRegLiveness: true
1708 registers:
1709 - { id: 0, class: fpr }
1710 - { id: 1, class: fpr }
1711 - { id: 2, class: fpr }
1712 - { id: 3, class: fpr }
1713 liveins:
1714 - { reg: '$q0', virtual-reg: '%2' }
1715 - { reg: '$d0', virtual-reg: '%3' }
1716 body: |
1717 bb.0.entry:
1718 liveins: $q0, $d0
1719
1720 ; CHECK-LABEL: name: test_rule955_id3891_at_idx62325
1721 ; CHECK: liveins: $q0, $d0
1722 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
1723 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
1724 ; CHECK: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]]
1725 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]]
1726 %3:fpr(<2 x s32>) = COPY $d0
1727 %2:fpr(<2 x s64>) = COPY $q0
1728 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
1729 %1:fpr(<2 x s64>) = G_ADD %0, %2
1730 $noreg = PATCHABLE_RET %1(<2 x s64>)
1731
1732 ...
1733 ---
1734 name: test_rule956_id927_at_idx62401
1735 alignment: 2
1736 legalized: true
1737 regBankSelected: true
1738 tracksRegLiveness: true
1739 registers:
1740 - { id: 0, class: fpr }
1741 - { id: 1, class: fpr }
1742 - { id: 2, class: fpr }
1743 - { id: 3, class: fpr }
1744 - { id: 4, class: fpr }
1745 liveins:
1746 - { reg: '$d0', virtual-reg: '%2' }
1747 - { reg: '$d1', virtual-reg: '%3' }
1748 - { reg: '$d2', virtual-reg: '%4' }
1749 body: |
1750 bb.0.entry:
1751 liveins: $d0, $d1, $d2
1752
1753 ; CHECK-LABEL: name: test_rule956_id927_at_idx62401
1754 ; CHECK: liveins: $d0, $d1, $d2
1755 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
1756 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
1757 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
1758 ; CHECK: [[MLAv8i8_:%[0-9]+]]:fpr64 = MLAv8i8 [[COPY2]], [[COPY1]], [[COPY]]
1759 ; CHECK: $noreg = PATCHABLE_RET [[MLAv8i8_]]
1760 %4:fpr(<8 x s8>) = COPY $d2
1761 %3:fpr(<8 x s8>) = COPY $d1
1762 %2:fpr(<8 x s8>) = COPY $d0
1763 %0:fpr(<8 x s8>) = G_MUL %3, %4
1764 %1:fpr(<8 x s8>) = G_ADD %2, %0
1765 $noreg = PATCHABLE_RET %1(<8 x s8>)
1766
1767 ...
1768 ---
1769 name: test_rule957_id928_at_idx62489
1770 alignment: 2
1771 legalized: true
1772 regBankSelected: true
1773 tracksRegLiveness: true
1774 registers:
1775 - { id: 0, class: fpr }
1776 - { id: 1, class: fpr }
1777 - { id: 2, class: fpr }
1778 - { id: 3, class: fpr }
1779 - { id: 4, class: fpr }
1780 liveins:
1781 - { reg: '$q0', virtual-reg: '%2' }
1782 - { reg: '$q1', virtual-reg: '%3' }
1783 - { reg: '$q2', virtual-reg: '%4' }
1784 body: |
1785 bb.0.entry:
1786 liveins: $q0, $q1, $q2
1787
1788 ; CHECK-LABEL: name: test_rule957_id928_at_idx62489
1789 ; CHECK: liveins: $q0, $q1, $q2
1790 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
1791 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
1792 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
1793 ; CHECK: [[MLAv16i8_:%[0-9]+]]:fpr128 = MLAv16i8 [[COPY2]], [[COPY1]], [[COPY]]
1794 ; CHECK: $noreg = PATCHABLE_RET [[MLAv16i8_]]
1795 %4:fpr(<16 x s8>) = COPY $q2
1796 %3:fpr(<16 x s8>) = COPY $q1
1797 %2:fpr(<16 x s8>) = COPY $q0
1798 %0:fpr(<16 x s8>) = G_MUL %3, %4
1799 %1:fpr(<16 x s8>) = G_ADD %2, %0
1800 $noreg = PATCHABLE_RET %1(<16 x s8>)
1801
1802 ...
1803 ---
1804 name: test_rule958_id929_at_idx62577
1805 alignment: 2
1806 legalized: true
1807 regBankSelected: true
1808 tracksRegLiveness: true
1809 registers:
1810 - { id: 0, class: fpr }
1811 - { id: 1, class: fpr }
1812 - { id: 2, class: fpr }
1813 - { id: 3, class: fpr }
1814 - { id: 4, class: fpr }
1815 liveins:
1816 - { reg: '$d0', virtual-reg: '%2' }
1817 - { reg: '$d1', virtual-reg: '%3' }
1818 - { reg: '$d2', virtual-reg: '%4' }
1819 body: |
1820 bb.0.entry:
1821 liveins: $d0, $d1, $d2
1822
1823 ; CHECK-LABEL: name: test_rule958_id929_at_idx62577
1824 ; CHECK: liveins: $d0, $d1, $d2
1825 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
1826 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
1827 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
1828 ; CHECK: [[MLAv4i16_:%[0-9]+]]:fpr64 = MLAv4i16 [[COPY2]], [[COPY1]], [[COPY]]
1829 ; CHECK: $noreg = PATCHABLE_RET [[MLAv4i16_]]
1830 %4:fpr(<4 x s16>) = COPY $d2
1831 %3:fpr(<4 x s16>) = COPY $d1
1832 %2:fpr(<4 x s16>) = COPY $d0
1833 %0:fpr(<4 x s16>) = G_MUL %3, %4
1834 %1:fpr(<4 x s16>) = G_ADD %2, %0
1835 $noreg = PATCHABLE_RET %1(<4 x s16>)
1836
1837 ...
1838 ---
1839 name: test_rule959_id930_at_idx62665
1840 alignment: 2
1841 legalized: true
1842 regBankSelected: true
1843 tracksRegLiveness: true
1844 registers:
1845 - { id: 0, class: fpr }
1846 - { id: 1, class: fpr }
1847 - { id: 2, class: fpr }
1848 - { id: 3, class: fpr }
1849 - { id: 4, class: fpr }
1850 liveins:
1851 - { reg: '$q0', virtual-reg: '%2' }
1852 - { reg: '$q1', virtual-reg: '%3' }
1853 - { reg: '$q2', virtual-reg: '%4' }
1854 body: |
1855 bb.0.entry:
1856 liveins: $q0, $q1, $q2
1857
1858 ; CHECK-LABEL: name: test_rule959_id930_at_idx62665
1859 ; CHECK: liveins: $q0, $q1, $q2
1860 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
1861 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
1862 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
1863 ; CHECK: [[MLAv8i16_:%[0-9]+]]:fpr128 = MLAv8i16 [[COPY2]], [[COPY1]], [[COPY]]
1864 ; CHECK: $noreg = PATCHABLE_RET [[MLAv8i16_]]
1865 %4:fpr(<8 x s16>) = COPY $q2
1866 %3:fpr(<8 x s16>) = COPY $q1
1867 %2:fpr(<8 x s16>) = COPY $q0
1868 %0:fpr(<8 x s16>) = G_MUL %3, %4
1869 %1:fpr(<8 x s16>) = G_ADD %2, %0
1870 $noreg = PATCHABLE_RET %1(<8 x s16>)
1871
1872 ...
1873 ---
1874 name: test_rule962_id1272_at_idx62929
1875 alignment: 2
1876 legalized: true
1877 regBankSelected: true
1878 tracksRegLiveness: true
1879 registers:
1880 - { id: 0, class: fpr }
1881 - { id: 1, class: fpr }
1882 - { id: 2, class: fpr }
1883 - { id: 3, class: fpr }
1884 liveins:
1885 - { reg: '$q0', virtual-reg: '%2' }
1886 - { reg: '$d0', virtual-reg: '%3' }
1887 body: |
1888 bb.0.entry:
1889 liveins: $q0, $d0
1890
1891 ; CHECK-LABEL: name: test_rule962_id1272_at_idx62929
1892 ; CHECK: liveins: $q0, $d0
1893 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
1894 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
1895 ; CHECK: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]]
1896 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]]
1897 %3:fpr(<8 x s8>) = COPY $d0
1898 %2:fpr(<8 x s16>) = COPY $q0
1899 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
1900 %1:fpr(<8 x s16>) = G_ADD %2, %0
1901 $noreg = PATCHABLE_RET %1(<8 x s16>)
1902
1903 ...
1904 ---
1905 name: test_rule963_id1274_at_idx63005
1906 alignment: 2
1907 legalized: true
1908 regBankSelected: true
1909 tracksRegLiveness: true
1910 registers:
1911 - { id: 0, class: fpr }
1912 - { id: 1, class: fpr }
1913 - { id: 2, class: fpr }
1914 - { id: 3, class: fpr }
1915 liveins:
1916 - { reg: '$q0', virtual-reg: '%2' }
1917 - { reg: '$d0', virtual-reg: '%3' }
1918 body: |
1919 bb.0.entry:
1920 liveins: $q0, $d0
1921
1922 ; CHECK-LABEL: name: test_rule963_id1274_at_idx63005
1923 ; CHECK: liveins: $q0, $d0
1924 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
1925 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
1926 ; CHECK: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]]
1927 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]]
1928 %3:fpr(<4 x s16>) = COPY $d0
1929 %2:fpr(<4 x s32>) = COPY $q0
1930 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
1931 %1:fpr(<4 x s32>) = G_ADD %2, %0
1932 $noreg = PATCHABLE_RET %1(<4 x s32>)
1933
1934 ...
1935 ---
1936 name: test_rule964_id1276_at_idx63081
1937 alignment: 2
1938 legalized: true
1939 regBankSelected: true
1940 tracksRegLiveness: true
1941 registers:
1942 - { id: 0, class: fpr }
1943 - { id: 1, class: fpr }
1944 - { id: 2, class: fpr }
1945 - { id: 3, class: fpr }
1946 liveins:
1947 - { reg: '$q0', virtual-reg: '%2' }
1948 - { reg: '$d0', virtual-reg: '%3' }
1949 body: |
1950 bb.0.entry:
1951 liveins: $q0, $d0
1952
1953 ; CHECK-LABEL: name: test_rule964_id1276_at_idx63081
1954 ; CHECK: liveins: $q0, $d0
1955 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
1956 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
1957 ; CHECK: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]]
1958 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]]
1959 %3:fpr(<2 x s32>) = COPY $d0
1960 %2:fpr(<2 x s64>) = COPY $q0
1961 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
1962 %1:fpr(<2 x s64>) = G_ADD %2, %0
1963 $noreg = PATCHABLE_RET %1(<2 x s64>)
1964
1965 ...
1966 ---
1967 name: test_rule965_id1332_at_idx63157
1968 alignment: 2
1969 legalized: true
1970 regBankSelected: true
1971 tracksRegLiveness: true
1972 registers:
1973 - { id: 0, class: fpr }
1974 - { id: 1, class: fpr }
1975 - { id: 2, class: fpr }
1976 - { id: 3, class: fpr }
1977 liveins:
1978 - { reg: '$q0', virtual-reg: '%2' }
1979 - { reg: '$d0', virtual-reg: '%3' }
1980 body: |
1981 bb.0.entry:
1982 liveins: $q0, $d0
1983
1984 ; CHECK-LABEL: name: test_rule965_id1332_at_idx63157
1985 ; CHECK: liveins: $q0, $d0
1986 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
1987 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
1988 ; CHECK: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]]
1989 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]]
1990 %3:fpr(<8 x s8>) = COPY $d0
1991 %2:fpr(<8 x s16>) = COPY $q0
1992 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
1993 %1:fpr(<8 x s16>) = G_ADD %2, %0
1994 $noreg = PATCHABLE_RET %1(<8 x s16>)
1995
1996 ...
1997 ---
1998 name: test_rule966_id1334_at_idx63233
1999 alignment: 2
2000 legalized: true
2001 regBankSelected: true
2002 tracksRegLiveness: true
2003 registers:
2004 - { id: 0, class: fpr }
2005 - { id: 1, class: fpr }
2006 - { id: 2, class: fpr }
2007 - { id: 3, class: fpr }
2008 liveins:
2009 - { reg: '$q0', virtual-reg: '%2' }
2010 - { reg: '$d0', virtual-reg: '%3' }
2011 body: |
2012 bb.0.entry:
2013 liveins: $q0, $d0
2014
2015 ; CHECK-LABEL: name: test_rule966_id1334_at_idx63233
2016 ; CHECK: liveins: $q0, $d0
2017 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
2018 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2019 ; CHECK: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]]
2020 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]]
2021 %3:fpr(<4 x s16>) = COPY $d0
2022 %2:fpr(<4 x s32>) = COPY $q0
2023 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
2024 %1:fpr(<4 x s32>) = G_ADD %2, %0
2025 $noreg = PATCHABLE_RET %1(<4 x s32>)
2026
2027 ...
2028 ---
2029 name: test_rule967_id1336_at_idx63309
2030 alignment: 2
2031 legalized: true
2032 regBankSelected: true
2033 tracksRegLiveness: true
2034 registers:
2035 - { id: 0, class: fpr }
2036 - { id: 1, class: fpr }
2037 - { id: 2, class: fpr }
2038 - { id: 3, class: fpr }
2039 liveins:
2040 - { reg: '$q0', virtual-reg: '%2' }
2041 - { reg: '$d0', virtual-reg: '%3' }
2042 body: |
2043 bb.0.entry:
2044 liveins: $q0, $d0
2045
2046 ; CHECK-LABEL: name: test_rule967_id1336_at_idx63309
2047 ; CHECK: liveins: $q0, $d0
2048 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
2049 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2050 ; CHECK: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]]
2051 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]]
2052 %3:fpr(<2 x s32>) = COPY $d0
2053 %2:fpr(<2 x s64>) = COPY $q0
2054 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
2055 %1:fpr(<2 x s64>) = G_ADD %2, %0
2056 $noreg = PATCHABLE_RET %1(<2 x s64>)
2057
2058 ...
2059 ---
2060 name: test_rule977_id933_at_idx64051
2061 alignment: 2
2062 legalized: true
2063 regBankSelected: true
2064 tracksRegLiveness: true
2065 registers:
2066 - { id: 0, class: fpr }
2067 - { id: 1, class: fpr }
2068 - { id: 2, class: fpr }
2069 - { id: 3, class: fpr }
2070 - { id: 4, class: fpr }
2071 liveins:
2072 - { reg: '$d0', virtual-reg: '%2' }
2073 - { reg: '$d1', virtual-reg: '%3' }
2074 - { reg: '$d2', virtual-reg: '%4' }
2075 body: |
2076 bb.0.entry:
2077 liveins: $d0, $d1, $d2
2078
2079 ; CHECK-LABEL: name: test_rule977_id933_at_idx64051
2080 ; CHECK: liveins: $d0, $d1, $d2
2081 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
2082 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
2083 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
2084 ; CHECK: [[MLSv8i8_:%[0-9]+]]:fpr64 = MLSv8i8 [[COPY2]], [[COPY1]], [[COPY]]
2085 ; CHECK: $noreg = PATCHABLE_RET [[MLSv8i8_]]
2086 %4:fpr(<8 x s8>) = COPY $d2
2087 %3:fpr(<8 x s8>) = COPY $d1
2088 %2:fpr(<8 x s8>) = COPY $d0
2089 %0:fpr(<8 x s8>) = G_MUL %3, %4
2090 %1:fpr(<8 x s8>) = G_SUB %2, %0
2091 $noreg = PATCHABLE_RET %1(<8 x s8>)
2092
2093 ...
2094 ---
2095 name: test_rule978_id934_at_idx64139
2096 alignment: 2
2097 legalized: true
2098 regBankSelected: true
2099 tracksRegLiveness: true
2100 registers:
2101 - { id: 0, class: fpr }
2102 - { id: 1, class: fpr }
2103 - { id: 2, class: fpr }
2104 - { id: 3, class: fpr }
2105 - { id: 4, class: fpr }
2106 liveins:
2107 - { reg: '$q0', virtual-reg: '%2' }
2108 - { reg: '$q1', virtual-reg: '%3' }
2109 - { reg: '$q2', virtual-reg: '%4' }
2110 body: |
2111 bb.0.entry:
2112 liveins: $q0, $q1, $q2
2113
2114 ; CHECK-LABEL: name: test_rule978_id934_at_idx64139
2115 ; CHECK: liveins: $q0, $q1, $q2
2116 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
2117 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
2118 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
2119 ; CHECK: [[MLSv16i8_:%[0-9]+]]:fpr128 = MLSv16i8 [[COPY2]], [[COPY1]], [[COPY]]
2120 ; CHECK: $noreg = PATCHABLE_RET [[MLSv16i8_]]
2121 %4:fpr(<16 x s8>) = COPY $q2
2122 %3:fpr(<16 x s8>) = COPY $q1
2123 %2:fpr(<16 x s8>) = COPY $q0
2124 %0:fpr(<16 x s8>) = G_MUL %3, %4
2125 %1:fpr(<16 x s8>) = G_SUB %2, %0
2126 $noreg = PATCHABLE_RET %1(<16 x s8>)
2127
2128 ...
2129 ---
2130 name: test_rule979_id935_at_idx64227
2131 alignment: 2
2132 legalized: true
2133 regBankSelected: true
2134 tracksRegLiveness: true
2135 registers:
2136 - { id: 0, class: fpr }
2137 - { id: 1, class: fpr }
2138 - { id: 2, class: fpr }
2139 - { id: 3, class: fpr }
2140 - { id: 4, class: fpr }
2141 liveins:
2142 - { reg: '$d0', virtual-reg: '%2' }
2143 - { reg: '$d1', virtual-reg: '%3' }
2144 - { reg: '$d2', virtual-reg: '%4' }
2145 body: |
2146 bb.0.entry:
2147 liveins: $d0, $d1, $d2
2148
2149 ; CHECK-LABEL: name: test_rule979_id935_at_idx64227
2150 ; CHECK: liveins: $d0, $d1, $d2
2151 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
2152 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
2153 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
2154 ; CHECK: [[MLSv4i16_:%[0-9]+]]:fpr64 = MLSv4i16 [[COPY2]], [[COPY1]], [[COPY]]
2155 ; CHECK: $noreg = PATCHABLE_RET [[MLSv4i16_]]
2156 %4:fpr(<4 x s16>) = COPY $d2
2157 %3:fpr(<4 x s16>) = COPY $d1
2158 %2:fpr(<4 x s16>) = COPY $d0
2159 %0:fpr(<4 x s16>) = G_MUL %3, %4
2160 %1:fpr(<4 x s16>) = G_SUB %2, %0
2161 $noreg = PATCHABLE_RET %1(<4 x s16>)
2162
2163 ...
2164 ---
2165 name: test_rule980_id936_at_idx64315
2166 alignment: 2
2167 legalized: true
2168 regBankSelected: true
2169 tracksRegLiveness: true
2170 registers:
2171 - { id: 0, class: fpr }
2172 - { id: 1, class: fpr }
2173 - { id: 2, class: fpr }
2174 - { id: 3, class: fpr }
2175 - { id: 4, class: fpr }
2176 liveins:
2177 - { reg: '$q0', virtual-reg: '%2' }
2178 - { reg: '$q1', virtual-reg: '%3' }
2179 - { reg: '$q2', virtual-reg: '%4' }
2180 body: |
2181 bb.0.entry:
2182 liveins: $q0, $q1, $q2
2183
2184 ; CHECK-LABEL: name: test_rule980_id936_at_idx64315
2185 ; CHECK: liveins: $q0, $q1, $q2
2186 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
2187 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
2188 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
2189 ; CHECK: [[MLSv8i16_:%[0-9]+]]:fpr128 = MLSv8i16 [[COPY2]], [[COPY1]], [[COPY]]
2190 ; CHECK: $noreg = PATCHABLE_RET [[MLSv8i16_]]
2191 %4:fpr(<8 x s16>) = COPY $q2
2192 %3:fpr(<8 x s16>) = COPY $q1
2193 %2:fpr(<8 x s16>) = COPY $q0
2194 %0:fpr(<8 x s16>) = G_MUL %3, %4
2195 %1:fpr(<8 x s16>) = G_SUB %2, %0
2196 $noreg = PATCHABLE_RET %1(<8 x s16>)
2197
2198 ...
2199 ---
2200 name: test_rule983_id1314_at_idx64579
2201 alignment: 2
2202 legalized: true
2203 regBankSelected: true
2204 tracksRegLiveness: true
2205 registers:
2206 - { id: 0, class: fpr }
2207 - { id: 1, class: fpr }
2208 - { id: 2, class: fpr }
2209 - { id: 3, class: fpr }
2210 liveins:
2211 - { reg: '$q0', virtual-reg: '%2' }
2212 - { reg: '$d0', virtual-reg: '%3' }
2213 body: |
2214 bb.0.entry:
2215 liveins: $q0, $d0
2216
2217 ; CHECK-LABEL: name: test_rule983_id1314_at_idx64579
2218 ; CHECK: liveins: $q0, $d0
2219 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
2220 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2221 ; CHECK: [[SSUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBWv8i8_v8i16 [[COPY1]], [[COPY]]
2222 ; CHECK: $noreg = PATCHABLE_RET [[SSUBWv8i8_v8i16_]]
2223 %3:fpr(<8 x s8>) = COPY $d0
2224 %2:fpr(<8 x s16>) = COPY $q0
2225 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
2226 %1:fpr(<8 x s16>) = G_SUB %2, %0
2227 $noreg = PATCHABLE_RET %1(<8 x s16>)
2228
2229 ...
2230 ---
2231 name: test_rule984_id1316_at_idx64655
2232 alignment: 2
2233 legalized: true
2234 regBankSelected: true
2235 tracksRegLiveness: true
2236 registers:
2237 - { id: 0, class: fpr }
2238 - { id: 1, class: fpr }
2239 - { id: 2, class: fpr }
2240 - { id: 3, class: fpr }
2241 liveins:
2242 - { reg: '$q0', virtual-reg: '%2' }
2243 - { reg: '$d0', virtual-reg: '%3' }
2244 body: |
2245 bb.0.entry:
2246 liveins: $q0, $d0
2247
2248 ; CHECK-LABEL: name: test_rule984_id1316_at_idx64655
2249 ; CHECK: liveins: $q0, $d0
2250 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
2251 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2252 ; CHECK: [[SSUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBWv4i16_v4i32 [[COPY1]], [[COPY]]
2253 ; CHECK: $noreg = PATCHABLE_RET [[SSUBWv4i16_v4i32_]]
2254 %3:fpr(<4 x s16>) = COPY $d0
2255 %2:fpr(<4 x s32>) = COPY $q0
2256 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
2257 %1:fpr(<4 x s32>) = G_SUB %2, %0
2258 $noreg = PATCHABLE_RET %1(<4 x s32>)
2259
2260 ...
2261 ---
2262 name: test_rule985_id1318_at_idx64731
2263 alignment: 2
2264 legalized: true
2265 regBankSelected: true
2266 tracksRegLiveness: true
2267 registers:
2268 - { id: 0, class: fpr }
2269 - { id: 1, class: fpr }
2270 - { id: 2, class: fpr }
2271 - { id: 3, class: fpr }
2272 liveins:
2273 - { reg: '$q0', virtual-reg: '%2' }
2274 - { reg: '$d0', virtual-reg: '%3' }
2275 body: |
2276 bb.0.entry:
2277 liveins: $q0, $d0
2278
2279 ; CHECK-LABEL: name: test_rule985_id1318_at_idx64731
2280 ; CHECK: liveins: $q0, $d0
2281 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
2282 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2283 ; CHECK: [[SSUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBWv2i32_v2i64 [[COPY1]], [[COPY]]
2284 ; CHECK: $noreg = PATCHABLE_RET [[SSUBWv2i32_v2i64_]]
2285 %3:fpr(<2 x s32>) = COPY $d0
2286 %2:fpr(<2 x s64>) = COPY $q0
2287 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
2288 %1:fpr(<2 x s64>) = G_SUB %2, %0
2289 $noreg = PATCHABLE_RET %1(<2 x s64>)
2290
2291 ...
2292 ---
2293 name: test_rule986_id1362_at_idx64807
2294 alignment: 2
2295 legalized: true
2296 regBankSelected: true
2297 tracksRegLiveness: true
2298 registers:
2299 - { id: 0, class: fpr }
2300 - { id: 1, class: fpr }
2301 - { id: 2, class: fpr }
2302 - { id: 3, class: fpr }
2303 liveins:
2304 - { reg: '$q0', virtual-reg: '%2' }
2305 - { reg: '$d0', virtual-reg: '%3' }
2306 body: |
2307 bb.0.entry:
2308 liveins: $q0, $d0
2309
2310 ; CHECK-LABEL: name: test_rule986_id1362_at_idx64807
2311 ; CHECK: liveins: $q0, $d0
2312 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
2313 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2314 ; CHECK: [[USUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBWv8i8_v8i16 [[COPY1]], [[COPY]]
2315 ; CHECK: $noreg = PATCHABLE_RET [[USUBWv8i8_v8i16_]]
2316 %3:fpr(<8 x s8>) = COPY $d0
2317 %2:fpr(<8 x s16>) = COPY $q0
2318 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
2319 %1:fpr(<8 x s16>) = G_SUB %2, %0
2320 $noreg = PATCHABLE_RET %1(<8 x s16>)
2321
2322 ...
2323 ---
2324 name: test_rule987_id1364_at_idx64883
2325 alignment: 2
2326 legalized: true
2327 regBankSelected: true
2328 tracksRegLiveness: true
2329 registers:
2330 - { id: 0, class: fpr }
2331 - { id: 1, class: fpr }
2332 - { id: 2, class: fpr }
2333 - { id: 3, class: fpr }
2334 liveins:
2335 - { reg: '$q0', virtual-reg: '%2' }
2336 - { reg: '$d0', virtual-reg: '%3' }
2337 body: |
2338 bb.0.entry:
2339 liveins: $q0, $d0
2340
2341 ; CHECK-LABEL: name: test_rule987_id1364_at_idx64883
2342 ; CHECK: liveins: $q0, $d0
2343 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
2344 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2345 ; CHECK: [[USUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBWv4i16_v4i32 [[COPY1]], [[COPY]]
2346 ; CHECK: $noreg = PATCHABLE_RET [[USUBWv4i16_v4i32_]]
2347 %3:fpr(<4 x s16>) = COPY $d0
2348 %2:fpr(<4 x s32>) = COPY $q0
2349 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
2350 %1:fpr(<4 x s32>) = G_SUB %2, %0
2351 $noreg = PATCHABLE_RET %1(<4 x s32>)
2352
2353 ...
2354 ---
2355 name: test_rule988_id1366_at_idx64959
2356 alignment: 2
2357 legalized: true
2358 regBankSelected: true
2359 tracksRegLiveness: true
2360 registers:
2361 - { id: 0, class: fpr }
2362 - { id: 1, class: fpr }
2363 - { id: 2, class: fpr }
2364 - { id: 3, class: fpr }
2365 liveins:
2366 - { reg: '$q0', virtual-reg: '%2' }
2367 - { reg: '$d0', virtual-reg: '%3' }
2368 body: |
2369 bb.0.entry:
2370 liveins: $q0, $d0
2371
2372 ; CHECK-LABEL: name: test_rule988_id1366_at_idx64959
2373 ; CHECK: liveins: $q0, $d0
2374 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
2375 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2376 ; CHECK: [[USUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBWv2i32_v2i64 [[COPY1]], [[COPY]]
2377 ; CHECK: $noreg = PATCHABLE_RET [[USUBWv2i32_v2i64_]]
2378 %3:fpr(<2 x s32>) = COPY $d0
2379 %2:fpr(<2 x s64>) = COPY $q0
2380 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
2381 %1:fpr(<2 x s64>) = G_SUB %2, %0
2382 $noreg = PATCHABLE_RET %1(<2 x s64>)
2383
2384 ...
2385 ---
2386 name: test_rule990_id432_at_idx65123
2387 alignment: 2
2388 legalized: true
2389 regBankSelected: true
2390 tracksRegLiveness: true
2391 registers:
2392 - { id: 0, class: fpr }
2393 - { id: 1, class: fpr }
2394 - { id: 2, class: fpr }
2395 - { id: 3, class: fpr }
2396 - { id: 4, class: fpr }
2397 liveins:
2398 - { reg: '$s0', virtual-reg: '%2' }
2399 - { reg: '$s1', virtual-reg: '%3' }
2400 - { reg: '$s2', virtual-reg: '%4' }
2401 body: |
2402 bb.0.entry:
2403 liveins: $s0, $s1, $s2
2404
2405 ; CHECK-LABEL: name: test_rule990_id432_at_idx65123
2406 ; CHECK: liveins: $s0, $s1, $s2
2407 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
2408 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
2409 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
2410 ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]]
2411 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
2412 %4:fpr(s32) = COPY $s2
2413 %3:fpr(s32) = COPY $s1
2414 %2:fpr(s32) = COPY $s0
2415 %0:fpr(s32) = G_FMA %2, %3, %4
2416 %1:fpr(s32) = G_FNEG %0
2417 $noreg = PATCHABLE_RET %1(s32)
2418
2419 ...
2420 ---
2421 name: test_rule991_id433_at_idx65211
2422 alignment: 2
2423 legalized: true
2424 regBankSelected: true
2425 tracksRegLiveness: true
2426 registers:
2427 - { id: 0, class: fpr }
2428 - { id: 1, class: fpr }
2429 - { id: 2, class: fpr }
2430 - { id: 3, class: fpr }
2431 - { id: 4, class: fpr }
2432 liveins:
2433 - { reg: '$d0', virtual-reg: '%2' }
2434 - { reg: '$d1', virtual-reg: '%3' }
2435 - { reg: '$d2', virtual-reg: '%4' }
2436 body: |
2437 bb.0.entry:
2438 liveins: $d0, $d1, $d2
2439
2440 ; CHECK-LABEL: name: test_rule991_id433_at_idx65211
2441 ; CHECK: liveins: $d0, $d1, $d2
2442 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
2443 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
2444 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
2445 ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]]
2446 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
2447 %4:fpr(s64) = COPY $d2
2448 %3:fpr(s64) = COPY $d1
2449 %2:fpr(s64) = COPY $d0
2450 %0:fpr(s64) = G_FMA %2, %3, %4
2451 %1:fpr(s64) = G_FNEG %0
2452 $noreg = PATCHABLE_RET %1(s64)
2453
2454 ...
2455 ---
2456 name: test_rule993_id420_at_idx65375
2457 alignment: 2
2458 legalized: true
2459 regBankSelected: true
2460 tracksRegLiveness: true
2461 registers:
2462 - { id: 0, class: fpr }
2463 - { id: 1, class: fpr }
2464 - { id: 2, class: fpr }
2465 - { id: 3, class: fpr }
2466 liveins:
2467 - { reg: '$s0', virtual-reg: '%2' }
2468 - { reg: '$s1', virtual-reg: '%3' }
2469 body: |
2470 bb.0.entry:
2471 liveins: $s0, $s1
2472
2473 ; CHECK-LABEL: name: test_rule993_id420_at_idx65375
2474 ; CHECK: liveins: $s0, $s1
2475 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
2476 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
2477 ; CHECK: [[FNMULSrr:%[0-9]+]]:fpr32 = FNMULSrr [[COPY1]], [[COPY]]
2478 ; CHECK: $noreg = PATCHABLE_RET [[FNMULSrr]]
2479 %3:fpr(s32) = COPY $s1
2480 %2:fpr(s32) = COPY $s0
2481 %0:fpr(s32) = G_FMUL %2, %3
2482 %1:fpr(s32) = G_FNEG %0
2483 $noreg = PATCHABLE_RET %1(s32)
2484
2485 ...
2486 ---
2487 name: test_rule994_id421_at_idx65451
2488 alignment: 2
2489 legalized: true
2490 regBankSelected: true
2491 tracksRegLiveness: true
2492 registers:
2493 - { id: 0, class: fpr }
2494 - { id: 1, class: fpr }
2495 - { id: 2, class: fpr }
2496 - { id: 3, class: fpr }
2497 liveins:
2498 - { reg: '$d0', virtual-reg: '%2' }
2499 - { reg: '$d1', virtual-reg: '%3' }
2500 body: |
2501 bb.0.entry:
2502 liveins: $d0, $d1
2503
2504 ; CHECK-LABEL: name: test_rule994_id421_at_idx65451
2505 ; CHECK: liveins: $d0, $d1
2506 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
2507 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
2508 ; CHECK: [[FNMULDrr:%[0-9]+]]:fpr64 = FNMULDrr [[COPY1]], [[COPY]]
2509 ; CHECK: $noreg = PATCHABLE_RET [[FNMULDrr]]
2510 %3:fpr(s64) = COPY $d1
2511 %2:fpr(s64) = COPY $d0
2512 %0:fpr(s64) = G_FMUL %2, %3
2513 %1:fpr(s64) = G_FNEG %0
2514 $noreg = PATCHABLE_RET %1(s64)
2515
2516 ...
2517 ---
2518 name: test_rule1230_id2969_at_idx81784
2519 alignment: 2
2520 legalized: true
2521 regBankSelected: true
2522 tracksRegLiveness: true
2523 registers:
2524 - { id: 0, class: gpr }
2525 - { id: 1, class: gpr }
2526 liveins:
2527 - { reg: '$x0', virtual-reg: '%0' }
2528 - { reg: '$x1', virtual-reg: '%1' }
2529 body: |
2530 bb.0.entry:
2531 liveins: $x0, $x1
2532
2533 ; CHECK-LABEL: name: test_rule1230_id2969_at_idx81784
2534 ; CHECK: liveins: $x0, $x1
2535 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
2536 ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0
2537 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]
2538 ; CHECK: ST1Onev8b [[COPY2]], [[COPY]] :: (store 8)
2539 ; CHECK: $noreg = PATCHABLE_RET
2540 %1:gpr(p0) = COPY $x1
2541 %0:gpr(<8 x s8>) = COPY $x0
2542 G_STORE %0(<8 x s8>), %1(p0) :: (store 8)
2543 $noreg = PATCHABLE_RET
2544
2545 ...
2546 ---
2547 name: test_rule1231_id2970_at_idx81816
2548 alignment: 2
2549 legalized: true
2550 regBankSelected: true
2551 tracksRegLiveness: true
2552 registers:
2553 - { id: 0, class: gpr }
2554 - { id: 1, class: gpr }
2555 liveins:
2556 - { reg: '$x0', virtual-reg: '%0' }
2557 - { reg: '$x1', virtual-reg: '%1' }
2558 body: |
2559 bb.0.entry:
2560 liveins: $x0, $x1
2561
2562 ; CHECK-LABEL: name: test_rule1231_id2970_at_idx81816
2563 ; CHECK: liveins: $x0, $x1
2564 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
2565 ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0
2566 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]
2567 ; CHECK: ST1Onev4h [[COPY2]], [[COPY]] :: (store 8)
2568 ; CHECK: $noreg = PATCHABLE_RET
2569 %1:gpr(p0) = COPY $x1
2570 %0:gpr(<4 x s16>) = COPY $x0
2571 G_STORE %0(<4 x s16>), %1(p0) :: (store 8)
2572 $noreg = PATCHABLE_RET
2573
2574 ...
2575 ---
2576 name: test_rule1239_id894_at_idx82201
2577 alignment: 2
2578 legalized: true
2579 regBankSelected: true
2580 tracksRegLiveness: true
2581 registers:
2582 - { id: 0, class: fpr }
2583 - { id: 1, class: fpr }
2584 - { id: 2, class: fpr }
2585 - { id: 3, class: fpr }
2586 liveins:
2587 - { reg: '$d0', virtual-reg: '%1' }
2588 - { reg: '$d1', virtual-reg: '%2' }
2589 - { reg: '$d2', virtual-reg: '%3' }
2590 body: |
2591 bb.0.entry:
2592 liveins: $d0, $d1, $d2
2593
2594 ; CHECK-LABEL: name: test_rule1239_id894_at_idx82201
2595 ; CHECK: liveins: $d0, $d1, $d2
2596 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
2597 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
2598 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
2599 ; CHECK: [[FMLAv2f32_:%[0-9]+]]:fpr64 = FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]]
2600 ; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f32_]]
2601 %3:fpr(<2 x s32>) = COPY $d2
2602 %2:fpr(<2 x s32>) = COPY $d1
2603 %1:fpr(<2 x s32>) = COPY $d0
2604 %0:fpr(<2 x s32>) = G_FMA %1, %2, %3
2605 $noreg = PATCHABLE_RET %0(<2 x s32>)
2606
2607 ...
2608 ---
2609 name: test_rule1240_id895_at_idx82269
2610 alignment: 2
2611 legalized: true
2612 regBankSelected: true
2613 tracksRegLiveness: true
2614 registers:
2615 - { id: 0, class: fpr }
2616 - { id: 1, class: fpr }
2617 - { id: 2, class: fpr }
2618 - { id: 3, class: fpr }
2619 liveins:
2620 - { reg: '$q0', virtual-reg: '%1' }
2621 - { reg: '$q1', virtual-reg: '%2' }
2622 - { reg: '$q2', virtual-reg: '%3' }
2623 body: |
2624 bb.0.entry:
2625 liveins: $q0, $q1, $q2
2626
2627 ; CHECK-LABEL: name: test_rule1240_id895_at_idx82269
2628 ; CHECK: liveins: $q0, $q1, $q2
2629 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
2630 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
2631 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
2632 ; CHECK: [[FMLAv4f32_:%[0-9]+]]:fpr128 = FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]]
2633 ; CHECK: $noreg = PATCHABLE_RET [[FMLAv4f32_]]
2634 %3:fpr(<4 x s32>) = COPY $q2
2635 %2:fpr(<4 x s32>) = COPY $q1
2636 %1:fpr(<4 x s32>) = COPY $q0
2637 %0:fpr(<4 x s32>) = G_FMA %1, %2, %3
2638 $noreg = PATCHABLE_RET %0(<4 x s32>)
2639
2640 ...
2641 ---
2642 name: test_rule1241_id896_at_idx82337
2643 alignment: 2
2644 legalized: true
2645 regBankSelected: true
2646 tracksRegLiveness: true
2647 registers:
2648 - { id: 0, class: fpr }
2649 - { id: 1, class: fpr }
2650 - { id: 2, class: fpr }
2651 - { id: 3, class: fpr }
2652 liveins:
2653 - { reg: '$q0', virtual-reg: '%1' }
2654 - { reg: '$q1', virtual-reg: '%2' }
2655 - { reg: '$q2', virtual-reg: '%3' }
2656 body: |
2657 bb.0.entry:
2658 liveins: $q0, $q1, $q2
2659
2660 ; CHECK-LABEL: name: test_rule1241_id896_at_idx82337
2661 ; CHECK: liveins: $q0, $q1, $q2
2662 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
2663 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
2664 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
2665 ; CHECK: [[FMLAv2f64_:%[0-9]+]]:fpr128 = FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]]
2666 ; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f64_]]
2667 %3:fpr(<2 x s64>) = COPY $q2
2668 %2:fpr(<2 x s64>) = COPY $q1
2669 %1:fpr(<2 x s64>) = COPY $q0
2670 %0:fpr(<2 x s64>) = G_FMA %1, %2, %3
2671 $noreg = PATCHABLE_RET %0(<2 x s64>)
2672
2673 ...
2674 ---
2675 name: test_rule1244_id751_at_idx82487
2676 alignment: 2
2677 legalized: true
2678 regBankSelected: true
2679 tracksRegLiveness: true
2680 registers:
2681 - { id: 0, class: fpr }
2682 - { id: 1, class: fpr }
2683 - { id: 2, class: fpr }
2684 liveins:
2685 - { reg: '$d0', virtual-reg: '%1' }
2686 - { reg: '$d1', virtual-reg: '%2' }
2687 body: |
2688 bb.0.entry:
2689 liveins: $d0, $d1
2690
2691 ; CHECK-LABEL: name: test_rule1244_id751_at_idx82487
2692 ; CHECK: liveins: $d0, $d1
2693 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
2694 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
2695 ; CHECK: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY1]], [[COPY]]
2696 ; CHECK: $noreg = PATCHABLE_RET [[ADDv8i8_]]
2697 %2:fpr(<8 x s8>) = COPY $d1
2698 %1:fpr(<8 x s8>) = COPY $d0
2699 %0:fpr(<8 x s8>) = G_ADD %1, %2
2700 $noreg = PATCHABLE_RET %0(<8 x s8>)
2701
2702 ...
2703 ---
2704 name: test_rule1245_id752_at_idx82530
2705 alignment: 2
2706 legalized: true
2707 regBankSelected: true
2708 tracksRegLiveness: true
2709 registers:
2710 - { id: 0, class: fpr }
2711 - { id: 1, class: fpr }
2712 - { id: 2, class: fpr }
2713 liveins:
2714 - { reg: '$q0', virtual-reg: '%1' }
2715 - { reg: '$q1', virtual-reg: '%2' }
2716 body: |
2717 bb.0.entry:
2718 liveins: $q0, $q1
2719
2720 ; CHECK-LABEL: name: test_rule1245_id752_at_idx82530
2721 ; CHECK: liveins: $q0, $q1
2722 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
2723 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2724 ; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY1]], [[COPY]]
2725 ; CHECK: $noreg = PATCHABLE_RET [[ADDv16i8_]]
2726 %2:fpr(<16 x s8>) = COPY $q1
2727 %1:fpr(<16 x s8>) = COPY $q0
2728 %0:fpr(<16 x s8>) = G_ADD %1, %2
2729 $noreg = PATCHABLE_RET %0(<16 x s8>)
2730
2731 ...
2732 ---
2733 name: test_rule1246_id753_at_idx82573
2734 alignment: 2
2735 legalized: true
2736 regBankSelected: true
2737 tracksRegLiveness: true
2738 registers:
2739 - { id: 0, class: fpr }
2740 - { id: 1, class: fpr }
2741 - { id: 2, class: fpr }
2742 liveins:
2743 - { reg: '$d0', virtual-reg: '%1' }
2744 - { reg: '$d1', virtual-reg: '%2' }
2745 body: |
2746 bb.0.entry:
2747 liveins: $d0, $d1
2748
2749 ; CHECK-LABEL: name: test_rule1246_id753_at_idx82573
2750 ; CHECK: liveins: $d0, $d1
2751 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
2752 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
2753 ; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY1]], [[COPY]]
2754 ; CHECK: $noreg = PATCHABLE_RET [[ADDv4i16_]]
2755 %2:fpr(<4 x s16>) = COPY $d1
2756 %1:fpr(<4 x s16>) = COPY $d0
2757 %0:fpr(<4 x s16>) = G_ADD %1, %2
2758 $noreg = PATCHABLE_RET %0(<4 x s16>)
2759
2760 ...
2761 ---
2762 name: test_rule1247_id754_at_idx82616
2763 alignment: 2
2764 legalized: true
2765 regBankSelected: true
2766 tracksRegLiveness: true
2767 registers:
2768 - { id: 0, class: fpr }
2769 - { id: 1, class: fpr }
2770 - { id: 2, class: fpr }
2771 liveins:
2772 - { reg: '$q0', virtual-reg: '%1' }
2773 - { reg: '$q1', virtual-reg: '%2' }
2774 body: |
2775 bb.0.entry:
2776 liveins: $q0, $q1
2777
2778 ; CHECK-LABEL: name: test_rule1247_id754_at_idx82616
2779 ; CHECK: liveins: $q0, $q1
2780 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
2781 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2782 ; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY1]], [[COPY]]
2783 ; CHECK: $noreg = PATCHABLE_RET [[ADDv8i16_]]
2784 %2:fpr(<8 x s16>) = COPY $q1
2785 %1:fpr(<8 x s16>) = COPY $q0
2786 %0:fpr(<8 x s16>) = G_ADD %1, %2
2787 $noreg = PATCHABLE_RET %0(<8 x s16>)
2788
2789 ...
2790 ---
2791 name: test_rule1254_id1162_at_idx82913
2792 alignment: 2
2793 legalized: true
2794 regBankSelected: true
2795 tracksRegLiveness: true
2796 registers:
2797 - { id: 0, class: fpr }
2798 - { id: 1, class: fpr }
2799 - { id: 2, class: fpr }
2800 liveins:
2801 - { reg: '$d0', virtual-reg: '%1' }
2802 - { reg: '$d1', virtual-reg: '%2' }
2803 body: |
2804 bb.0.entry:
2805 liveins: $d0, $d1
2806
2807 ; CHECK-LABEL: name: test_rule1254_id1162_at_idx82913
2808 ; CHECK: liveins: $d0, $d1
2809 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
2810 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
2811 ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]
2812 ; CHECK: $noreg = PATCHABLE_RET [[ANDv8i8_]]
2813 %2:fpr(<8 x s8>) = COPY $d1
2814 %1:fpr(<8 x s8>) = COPY $d0
2815 %0:fpr(<8 x s8>) = G_AND %1, %2
2816 $noreg = PATCHABLE_RET %0(<8 x s8>)
2817
2818 ...
2819 ---
2820 name: test_rule1255_id1163_at_idx82956
2821 alignment: 2
2822 legalized: true
2823 regBankSelected: true
2824 tracksRegLiveness: true
2825 registers:
2826 - { id: 0, class: fpr }
2827 - { id: 1, class: fpr }
2828 - { id: 2, class: fpr }
2829 liveins:
2830 - { reg: '$q0', virtual-reg: '%1' }
2831 - { reg: '$q1', virtual-reg: '%2' }
2832 body: |
2833 bb.0.entry:
2834 liveins: $q0, $q1
2835
2836 ; CHECK-LABEL: name: test_rule1255_id1163_at_idx82956
2837 ; CHECK: liveins: $q0, $q1
2838 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
2839 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2840 ; CHECK: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]
2841 ; CHECK: $noreg = PATCHABLE_RET [[ANDv16i8_]]
2842 %2:fpr(<16 x s8>) = COPY $q1
2843 %1:fpr(<16 x s8>) = COPY $q0
2844 %0:fpr(<16 x s8>) = G_AND %1, %2
2845 $noreg = PATCHABLE_RET %0(<16 x s8>)
2846
2847 ...
2848 ---
2849 name: test_rule1256_id1751_at_idx82999
2850 alignment: 2
2851 legalized: true
2852 regBankSelected: true
2853 tracksRegLiveness: true
2854 registers:
2855 - { id: 0, class: fpr }
2856 - { id: 1, class: fpr }
2857 - { id: 2, class: fpr }
2858 liveins:
2859 - { reg: '$d0', virtual-reg: '%1' }
2860 - { reg: '$d1', virtual-reg: '%2' }
2861 body: |
2862 bb.0.entry:
2863 liveins: $d0, $d1
2864
2865 ; CHECK-LABEL: name: test_rule1256_id1751_at_idx82999
2866 ; CHECK: liveins: $d0, $d1
2867 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
2868 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
2869 ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]
2870 ; CHECK: $noreg = PATCHABLE_RET [[ANDv8i8_]]
2871 %2:fpr(<4 x s16>) = COPY $d1
2872 %1:fpr(<4 x s16>) = COPY $d0
2873 %0:fpr(<4 x s16>) = G_AND %1, %2
2874 $noreg = PATCHABLE_RET %0(<4 x s16>)
2875
2876 ...
2877 ---
2878 name: test_rule1259_id1754_at_idx83128
2879 alignment: 2
2880 legalized: true
2881 regBankSelected: true
2882 tracksRegLiveness: true
2883 registers:
2884 - { id: 0, class: fpr }
2885 - { id: 1, class: fpr }
2886 - { id: 2, class: fpr }
2887 liveins:
2888 - { reg: '$q0', virtual-reg: '%1' }
2889 - { reg: '$q1', virtual-reg: '%2' }
2890 body: |
2891 bb.0.entry:
2892 liveins: $q0, $q1
2893
2894 ; CHECK-LABEL: name: test_rule1259_id1754_at_idx83128
2895 ; CHECK: liveins: $q0, $q1
2896 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
2897 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2898 ; CHECK: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]
2899 ; CHECK: $noreg = PATCHABLE_RET [[ANDv16i8_]]
2900 %2:fpr(<8 x s16>) = COPY $q1
2901 %1:fpr(<8 x s16>) = COPY $q0
2902 %0:fpr(<8 x s16>) = G_AND %1, %2
2903 $noreg = PATCHABLE_RET %0(<8 x s16>)
2904
2905 ...
2906 ---
2907 name: test_rule1268_id829_at_idx83513
2908 alignment: 2
2909 legalized: true
2910 regBankSelected: true
2911 tracksRegLiveness: true
2912 registers:
2913 - { id: 0, class: fpr }
2914 - { id: 1, class: fpr }
2915 - { id: 2, class: fpr }
2916 liveins:
2917 - { reg: '$d0', virtual-reg: '%1' }
2918 - { reg: '$d1', virtual-reg: '%2' }
2919 body: |
2920 bb.0.entry:
2921 liveins: $d0, $d1
2922
2923 ; CHECK-LABEL: name: test_rule1268_id829_at_idx83513
2924 ; CHECK: liveins: $d0, $d1
2925 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
2926 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
2927 ; CHECK: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 [[COPY1]], [[COPY]]
2928 ; CHECK: $noreg = PATCHABLE_RET [[FADDv2f32_]]
2929 %2:fpr(<2 x s32>) = COPY $d1
2930 %1:fpr(<2 x s32>) = COPY $d0
2931 %0:fpr(<2 x s32>) = G_FADD %1, %2
2932 $noreg = PATCHABLE_RET %0(<2 x s32>)
2933
2934 ...
2935 ---
2936 name: test_rule1269_id830_at_idx83556
2937 alignment: 2
2938 legalized: true
2939 regBankSelected: true
2940 tracksRegLiveness: true
2941 registers:
2942 - { id: 0, class: fpr }
2943 - { id: 1, class: fpr }
2944 - { id: 2, class: fpr }
2945 liveins:
2946 - { reg: '$q0', virtual-reg: '%1' }
2947 - { reg: '$q1', virtual-reg: '%2' }
2948 body: |
2949 bb.0.entry:
2950 liveins: $q0, $q1
2951
2952 ; CHECK-LABEL: name: test_rule1269_id830_at_idx83556
2953 ; CHECK: liveins: $q0, $q1
2954 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
2955 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2956 ; CHECK: [[FADDv4f32_:%[0-9]+]]:fpr128 = FADDv4f32 [[COPY1]], [[COPY]]
2957 ; CHECK: $noreg = PATCHABLE_RET [[FADDv4f32_]]
2958 %2:fpr(<4 x s32>) = COPY $q1
2959 %1:fpr(<4 x s32>) = COPY $q0
2960 %0:fpr(<4 x s32>) = G_FADD %1, %2
2961 $noreg = PATCHABLE_RET %0(<4 x s32>)
2962
2963 ...
2964 ---
2965 name: test_rule1270_id831_at_idx83599
2966 alignment: 2
2967 legalized: true
2968 regBankSelected: true
2969 tracksRegLiveness: true
2970 registers:
2971 - { id: 0, class: fpr }
2972 - { id: 1, class: fpr }
2973 - { id: 2, class: fpr }
2974 liveins:
2975 - { reg: '$q0', virtual-reg: '%1' }
2976 - { reg: '$q1', virtual-reg: '%2' }
2977 body: |
2978 bb.0.entry:
2979 liveins: $q0, $q1
2980
2981 ; CHECK-LABEL: name: test_rule1270_id831_at_idx83599
2982 ; CHECK: liveins: $q0, $q1
2983 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
2984 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
2985 ; CHECK: [[FADDv2f64_:%[0-9]+]]:fpr128 = FADDv2f64 [[COPY1]], [[COPY]]
2986 ; CHECK: $noreg = PATCHABLE_RET [[FADDv2f64_]]
2987 %2:fpr(<2 x s64>) = COPY $q1
2988 %1:fpr(<2 x s64>) = COPY $q0
2989 %0:fpr(<2 x s64>) = G_FADD %1, %2
2990 $noreg = PATCHABLE_RET %0(<2 x s64>)
2991
2992 ...
2993 ---
2994 name: test_rule1276_id849_at_idx83857
2995 alignment: 2
2996 legalized: true
2997 regBankSelected: true
2998 tracksRegLiveness: true
2999 registers:
3000 - { id: 0, class: fpr }
3001 - { id: 1, class: fpr }
3002 - { id: 2, class: fpr }
3003 liveins:
3004 - { reg: '$d0', virtual-reg: '%1' }
3005 - { reg: '$d1', virtual-reg: '%2' }
3006 body: |
3007 bb.0.entry:
3008 liveins: $d0, $d1
3009
3010 ; CHECK-LABEL: name: test_rule1276_id849_at_idx83857
3011 ; CHECK: liveins: $d0, $d1
3012 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
3013 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
3014 ; CHECK: [[FDIVv2f32_:%[0-9]+]]:fpr64 = FDIVv2f32 [[COPY1]], [[COPY]]
3015 ; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f32_]]
3016 %2:fpr(<2 x s32>) = COPY $d1
3017 %1:fpr(<2 x s32>) = COPY $d0
3018 %0:fpr(<2 x s32>) = G_FDIV %1, %2
3019 $noreg = PATCHABLE_RET %0(<2 x s32>)
3020
3021 ...
3022 ---
3023 name: test_rule1277_id850_at_idx83900
3024 alignment: 2
3025 legalized: true
3026 regBankSelected: true
3027 tracksRegLiveness: true
3028 registers:
3029 - { id: 0, class: fpr }
3030 - { id: 1, class: fpr }
3031 - { id: 2, class: fpr }
3032 liveins:
3033 - { reg: '$q0', virtual-reg: '%1' }
3034 - { reg: '$q1', virtual-reg: '%2' }
3035 body: |
3036 bb.0.entry:
3037 liveins: $q0, $q1
3038
3039 ; CHECK-LABEL: name: test_rule1277_id850_at_idx83900
3040 ; CHECK: liveins: $q0, $q1
3041 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
3042 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
3043 ; CHECK: [[FDIVv4f32_:%[0-9]+]]:fpr128 = FDIVv4f32 [[COPY1]], [[COPY]]
3044 ; CHECK: $noreg = PATCHABLE_RET [[FDIVv4f32_]]
3045 %2:fpr(<4 x s32>) = COPY $q1
3046 %1:fpr(<4 x s32>) = COPY $q0
3047 %0:fpr(<4 x s32>) = G_FDIV %1, %2
3048 $noreg = PATCHABLE_RET %0(<4 x s32>)
3049
3050 ...
3051 ---
3052 name: test_rule1278_id851_at_idx83943
3053 alignment: 2
3054 legalized: true
3055 regBankSelected: true
3056 tracksRegLiveness: true
3057 registers:
3058 - { id: 0, class: fpr }
3059 - { id: 1, class: fpr }
3060 - { id: 2, class: fpr }
3061 liveins:
3062 - { reg: '$q0', virtual-reg: '%1' }
3063 - { reg: '$q1', virtual-reg: '%2' }
3064 body: |
3065 bb.0.entry:
3066 liveins: $q0, $q1
3067
3068 ; CHECK-LABEL: name: test_rule1278_id851_at_idx83943
3069 ; CHECK: liveins: $q0, $q1
3070 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
3071 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
3072 ; CHECK: [[FDIVv2f64_:%[0-9]+]]:fpr128 = FDIVv2f64 [[COPY1]], [[COPY]]
3073 ; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f64_]]
3074 %2:fpr(<2 x s64>) = COPY $q1
3075 %1:fpr(<2 x s64>) = COPY $q0
3076 %0:fpr(<2 x s64>) = G_FDIV %1, %2
3077 $noreg = PATCHABLE_RET %0(<2 x s64>)
3078
3079 ...
3080 ---
3081 name: test_rule1284_id909_at_idx84201
3082 alignment: 2
3083 legalized: true
3084 regBankSelected: true
3085 tracksRegLiveness: true
3086 registers:
3087 - { id: 0, class: fpr }
3088 - { id: 1, class: fpr }
3089 - { id: 2, class: fpr }
3090 liveins:
3091 - { reg: '$d0', virtual-reg: '%1' }
3092 - { reg: '$d1', virtual-reg: '%2' }
3093 body: |
3094 bb.0.entry:
3095 liveins: $d0, $d1
3096
3097 ; CHECK-LABEL: name: test_rule1284_id909_at_idx84201
3098 ; CHECK: liveins: $d0, $d1
3099 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
3100 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
3101 ; CHECK: [[FMULv2f32_:%[0-9]+]]:fpr64 = FMULv2f32 [[COPY1]], [[COPY]]
3102 ; CHECK: $noreg = PATCHABLE_RET [[FMULv2f32_]]
3103 %2:fpr(<2 x s32>) = COPY $d1
3104 %1:fpr(<2 x s32>) = COPY $d0
3105 %0:fpr(<2 x s32>) = G_FMUL %1, %2
3106 $noreg = PATCHABLE_RET %0(<2 x s32>)
3107
3108 ...
3109 ---
3110 name: test_rule1285_id910_at_idx84244
3111 alignment: 2
3112 legalized: true
3113 regBankSelected: true
3114 tracksRegLiveness: true
3115 registers:
3116 - { id: 0, class: fpr }
3117 - { id: 1, class: fpr }
3118 - { id: 2, class: fpr }
3119 liveins:
3120 - { reg: '$q0', virtual-reg: '%1' }
3121 - { reg: '$q1', virtual-reg: '%2' }
3122 body: |
3123 bb.0.entry:
3124 liveins: $q0, $q1
3125
3126 ; CHECK-LABEL: name: test_rule1285_id910_at_idx84244
3127 ; CHECK: liveins: $q0, $q1
3128 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
3129 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
3130 ; CHECK: [[FMULv4f32_:%[0-9]+]]:fpr128 = FMULv4f32 [[COPY1]], [[COPY]]
3131 ; CHECK: $noreg = PATCHABLE_RET [[FMULv4f32_]]
3132 %2:fpr(<4 x s32>) = COPY $q1
3133 %1:fpr(<4 x s32>) = COPY $q0
3134 %0:fpr(<4 x s32>) = G_FMUL %1, %2
3135 $noreg = PATCHABLE_RET %0(<4 x s32>)
3136
3137 ...
3138 ---
3139 name: test_rule1286_id911_at_idx84287
3140 alignment: 2
3141 legalized: true
3142 regBankSelected: true
3143 tracksRegLiveness: true
3144 registers:
3145 - { id: 0, class: fpr }
3146 - { id: 1, class: fpr }
3147 - { id: 2, class: fpr }
3148 liveins:
3149 - { reg: '$q0', virtual-reg: '%1' }
3150 - { reg: '$q1', virtual-reg: '%2' }
3151 body: |
3152 bb.0.entry:
3153 liveins: $q0, $q1
3154
3155 ; CHECK-LABEL: name: test_rule1286_id911_at_idx84287
3156 ; CHECK: liveins: $q0, $q1
3157 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
3158 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
3159 ; CHECK: [[FMULv2f64_:%[0-9]+]]:fpr128 = FMULv2f64 [[COPY1]], [[COPY]]
3160 ; CHECK: $noreg = PATCHABLE_RET [[FMULv2f64_]]
3161 %2:fpr(<2 x s64>) = COPY $q1
3162 %1:fpr(<2 x s64>) = COPY $q0
3163 %0:fpr(<2 x s64>) = G_FMUL %1, %2
3164 $noreg = PATCHABLE_RET %0(<2 x s64>)
3165
3166 ...
3167 ---
3168 name: test_rule1292_id924_at_idx84545
3169 alignment: 2
3170 legalized: true
3171 regBankSelected: true
3172 tracksRegLiveness: true
3173 registers:
3174 - { id: 0, class: fpr }
3175 - { id: 1, class: fpr }
3176 - { id: 2, class: fpr }
3177 liveins:
3178 - { reg: '$d0', virtual-reg: '%1' }
3179 - { reg: '$d1', virtual-reg: '%2' }
3180 body: |
3181 bb.0.entry:
3182 liveins: $d0, $d1
3183
3184 ; CHECK-LABEL: name: test_rule1292_id924_at_idx84545
3185 ; CHECK: liveins: $d0, $d1
3186 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
3187 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
3188 ; CHECK: [[FSUBv2f32_:%[0-9]+]]:fpr64 = FSUBv2f32 [[COPY1]], [[COPY]]
3189 ; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f32_]]
3190 %2:fpr(<2 x s32>) = COPY $d1
3191 %1:fpr(<2 x s32>) = COPY $d0
3192 %0:fpr(<2 x s32>) = G_FSUB %1, %2
3193 $noreg = PATCHABLE_RET %0(<2 x s32>)
3194
3195 ...
3196 ---
3197 name: test_rule1293_id925_at_idx84588
3198 alignment: 2
3199 legalized: true
3200 regBankSelected: true
3201 tracksRegLiveness: true
3202 registers:
3203 - { id: 0, class: fpr }
3204 - { id: 1, class: fpr }
3205 - { id: 2, class: fpr }
3206 liveins:
3207 - { reg: '$q0', virtual-reg: '%1' }
3208 - { reg: '$q1', virtual-reg: '%2' }
3209 body: |
3210 bb.0.entry:
3211 liveins: $q0, $q1
3212
3213 ; CHECK-LABEL: name: test_rule1293_id925_at_idx84588
3214 ; CHECK: liveins: $q0, $q1
3215 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
3216 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
3217 ; CHECK: [[FSUBv4f32_:%[0-9]+]]:fpr128 = FSUBv4f32 [[COPY1]], [[COPY]]
3218 ; CHECK: $noreg = PATCHABLE_RET [[FSUBv4f32_]]
3219 %2:fpr(<4 x s32>) = COPY $q1
3220 %1:fpr(<4 x s32>) = COPY $q0
3221 %0:fpr(<4 x s32>) = G_FSUB %1, %2
3222 $noreg = PATCHABLE_RET %0(<4 x s32>)
3223
3224 ...
3225 ---
3226 name: test_rule1294_id926_at_idx84631
3227 alignment: 2
3228 legalized: true
3229 regBankSelected: true
3230 tracksRegLiveness: true
3231 registers:
3232 - { id: 0, class: fpr }
3233 - { id: 1, class: fpr }
3234 - { id: 2, class: fpr }
3235 liveins:
3236 - { reg: '$q0', virtual-reg: '%1' }
3237 - { reg: '$q1', virtual-reg: '%2' }
3238 body: |
3239 bb.0.entry:
3240 liveins: $q0, $q1
3241
3242 ; CHECK-LABEL: name: test_rule1294_id926_at_idx84631
3243 ; CHECK: liveins: $q0, $q1
3244 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
3245 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
3246 ; CHECK: [[FSUBv2f64_:%[0-9]+]]:fpr128 = FSUBv2f64 [[COPY1]], [[COPY]]
3247 ; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f64_]]
3248 %2:fpr(<2 x s64>) = COPY $q1
3249 %1:fpr(<2 x s64>) = COPY $q0
3250 %0:fpr(<2 x s64>) = G_FSUB %1, %2
3251 $noreg = PATCHABLE_RET %0(<2 x s64>)
3252
3253 ...
3254 ---
3255 name: test_rule1296_id939_at_idx84715
3256 alignment: 2
3257 legalized: true
3258 regBankSelected: true
3259 tracksRegLiveness: true
3260 registers:
3261 - { id: 0, class: fpr }
3262 - { id: 1, class: fpr }
3263 - { id: 2, class: fpr }
3264 liveins:
3265 - { reg: '$d0', virtual-reg: '%1' }
3266 - { reg: '$d1', virtual-reg: '%2' }
3267 body: |
3268 bb.0.entry:
3269 liveins: $d0, $d1
3270
3271 ; CHECK-LABEL: name: test_rule1296_id939_at_idx84715
3272 ; CHECK: liveins: $d0, $d1
3273 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
3274 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
3275 ; CHECK: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]
3276 ; CHECK: $noreg = PATCHABLE_RET [[MULv8i8_]]
3277 %2:fpr(<8 x s8>) = COPY $d1
3278 %1:fpr(<8 x s8>) = COPY $d0
3279 %0:fpr(<8 x s8>) = G_MUL %1, %2
3280 $noreg = PATCHABLE_RET %0(<8 x s8>)
3281
3282 ...
3283 ---
3284 name: test_rule1297_id940_at_idx84758
3285 alignment: 2
3286 legalized: true
3287 regBankSelected: true
3288 tracksRegLiveness: true
3289 registers:
3290 - { id: 0, class: fpr }
3291 - { id: 1, class: fpr }
3292 - { id: 2, class: fpr }
3293 liveins:
3294 - { reg: '$q0', virtual-reg: '%1' }
3295 - { reg: '$q1', virtual-reg: '%2' }
3296 body: |
3297 bb.0.entry:
3298 liveins: $q0, $q1
3299
3300 ; CHECK-LABEL: name: test_rule1297_id940_at_idx84758
3301 ; CHECK: liveins: $q0, $q1
3302 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
3303 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
3304 ; CHECK: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]
3305 ; CHECK: $noreg = PATCHABLE_RET [[MULv16i8_]]
3306 %2:fpr(<16 x s8>) = COPY $q1
3307 %1:fpr(<16 x s8>) = COPY $q0
3308 %0:fpr(<16 x s8>) = G_MUL %1, %2
3309 $noreg = PATCHABLE_RET %0(<16 x s8>)
3310
3311 ...
3312 ---
3313 name: test_rule1298_id941_at_idx84801
3314 alignment: 2
3315 legalized: true
3316 regBankSelected: true
3317 tracksRegLiveness: true
3318 registers:
3319 - { id: 0, class: fpr }
3320 - { id: 1, class: fpr }
3321 - { id: 2, class: fpr }
3322 liveins:
3323 - { reg: '$d0', virtual-reg: '%1' }
3324 - { reg: '$d1', virtual-reg: '%2' }
3325 body: |
3326 bb.0.entry:
3327 liveins: $d0, $d1
3328
3329 ; CHECK-LABEL: name: test_rule1298_id941_at_idx84801
3330 ; CHECK: liveins: $d0, $d1
3331 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
3332 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
3333 ; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]
3334 ; CHECK: $noreg = PATCHABLE_RET [[MULv4i16_]]
3335 %2:fpr(<4 x s16>) = COPY $d1
3336 %1:fpr(<4 x s16>) = COPY $d0
3337 %0:fpr(<4 x s16>) = G_MUL %1, %2
3338 $noreg = PATCHABLE_RET %0(<4 x s16>)
3339
3340 ...
3341 ---
3342 name: test_rule1299_id942_at_idx84844
3343 alignment: 2
3344 legalized: true
3345 regBankSelected: true
3346 tracksRegLiveness: true
3347 registers:
3348 - { id: 0, class: fpr }
3349 - { id: 1, class: fpr }
3350 - { id: 2, class: fpr }
3351 liveins:
3352 - { reg: '$q0', virtual-reg: '%1' }
3353 - { reg: '$q1', virtual-reg: '%2' }
3354 body: |
3355 bb.0.entry:
3356 liveins: $q0, $q1
3357
3358 ; CHECK-LABEL: name: test_rule1299_id942_at_idx84844
3359 ; CHECK: liveins: $q0, $q1
3360 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
3361 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
3362 ; CHECK: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]
3363 ; CHECK: $noreg = PATCHABLE_RET [[MULv8i16_]]
3364 %2:fpr(<8 x s16>) = COPY $q1
3365 %1:fpr(<8 x s16>) = COPY $q0
3366 %0:fpr(<8 x s16>) = G_MUL %1, %2
3367 $noreg = PATCHABLE_RET %0(<8 x s16>)
3368
3369 ...
3370 ---
3371 name: test_rule1304_id1174_at_idx85055
3372 alignment: 2
3373 legalized: true
3374 regBankSelected: true
3375 tracksRegLiveness: true
3376 registers:
3377 - { id: 0, class: fpr }
3378 - { id: 1, class: fpr }
3379 - { id: 2, class: fpr }
3380 liveins:
3381 - { reg: '$d0', virtual-reg: '%1' }
3382 - { reg: '$d1', virtual-reg: '%2' }
3383 body: |
3384 bb.0.entry:
3385 liveins: $d0, $d1
3386
3387 ; CHECK-LABEL: name: test_rule1304_id1174_at_idx85055
3388 ; CHECK: liveins: $d0, $d1
3389 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
3390 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
3391 ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]
3392 ; CHECK: $noreg = PATCHABLE_RET [[ORRv8i8_]]
3393 %2:fpr(<8 x s8>) = COPY $d1
3394 %1:fpr(<8 x s8>) = COPY $d0
3395 %0:fpr(<8 x s8>) = G_OR %1, %2
3396 $noreg = PATCHABLE_RET %0(<8 x s8>)
3397
3398 ...
3399 ---
3400 name: test_rule1305_id1175_at_idx85098
3401 alignment: 2
3402 legalized: true
3403 regBankSelected: true
3404 tracksRegLiveness: true
3405 registers:
3406 - { id: 0, class: fpr }
3407 - { id: 1, class: fpr }
3408 - { id: 2, class: fpr }
3409 liveins:
3410 - { reg: '$q0', virtual-reg: '%1' }
3411 - { reg: '$q1', virtual-reg: '%2' }
3412 body: |
3413 bb.0.entry:
3414 liveins: $q0, $q1
3415
3416 ; CHECK-LABEL: name: test_rule1305_id1175_at_idx85098
3417 ; CHECK: liveins: $q0, $q1
3418 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
3419 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
3420 ; CHECK: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]