llvm.org GIT mirror llvm / 4b97985
Merging r354808: ------------------------------------------------------------------------ r354808 | nikic | 2019-02-25 10:54:17 -0800 (Mon, 25 Feb 2019) | 11 lines [Mips] Fix missing masking in fast-isel of br (PR40325) Fixes https://bugs.llvm.org/show_bug.cgi?id=40325 by zero extending (and x, 1) the condition before branching on it. To avoid regressing trivial cases, I'm combining emission of cmp+br sequences for the single-use + same block case (similar to what we do in x86). icmpbr1.ll still regresses due to the cross-bb usage of the condition. Differential Revision: https://reviews.llvm.org/D58576 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_80@358925 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 months ago
3 changed file(s) with 52 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
953953 //
954954 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
955955 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
956 // For now, just try the simplest case where it's fed by a compare.
956
957 // Fold the common case of a conditional branch with a comparison
958 // in the same block.
959 unsigned ZExtCondReg = 0;
957960 if (const CmpInst *CI = dyn_cast(BI->getCondition())) {
958 MVT CIMVT =
959 TLI.getValueType(DL, CI->getOperand(0)->getType(), true).getSimpleVT();
960 if (CIMVT == MVT::i1)
961 return false;
962
963 unsigned CondReg = getRegForValue(CI);
964 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
965 .addReg(CondReg)
966 .addMBB(TBB);
967 finishCondBranch(BI->getParent(), TBB, FBB);
968 return true;
969 }
970 return false;
961 if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
962 ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
963 if (!emitCmp(ZExtCondReg, CI))
964 return false;
965 }
966 }
967
968 // For the general case, we need to mask with 1.
969 if (ZExtCondReg == 0) {
970 unsigned CondReg = getRegForValue(BI->getCondition());
971 if (CondReg == 0)
972 return false;
973
974 ZExtCondReg = emitIntExt(MVT::i1, CondReg, MVT::i32, true);
975 if (ZExtCondReg == 0)
976 return false;
977 }
978
979 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
980 .addReg(ZExtCondReg)
981 .addMBB(TBB);
982 finishCondBranch(BI->getParent(), TBB, FBB);
983 return true;
971984 }
972985
973986 bool MipsFastISel::selectCmp(const Instruction *I) {
1616 bb1:
1717 ; CHECK: # %bb.1: # %bb1
1818 ; CHECK-NEXT: lw $[[REG2:[0-9]+]], [[SPILL]]($sp) # 4-byte Folded Reload
19 ; CHECK-NEXT: bgtz $[[REG2]], $BB0_3
19 ; CHECK-NEXT: andi $[[REG3:[0-9]+]], $[[REG2]], 1
20 ; CHECK-NEXT: bgtz $[[REG3]], $BB0_3
2021 br i1 %2, label %bb2, label %bb3
2122 bb2:
2223 ; CHECK: $BB0_3: # %bb2
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -mcpu=mips32 < %s | FileCheck %s
2
3 define void @test(i32 %x, i1* %p) nounwind {
4 ; CHECK-LABEL: test:
5 ; CHECK: # %bb.0:
6 ; CHECK-NEXT: move $1, $4
7 ; CHECK-NEXT: andi $4, $4, 1
8 ; CHECK-NEXT: sb $4, 0($5)
9 ; CHECK-NEXT: andi $1, $1, 1
10 ; CHECK-NEXT: bgtz $1, $BB0_1
11 ; CHECK-NEXT: nop
12 ; CHECK-NEXT: # %bb.1: # %foo
13 ; CHECK-NEXT: jr $ra
14 ; CHECK-NEXT: nop
15 %y = and i32 %x, 1
16 %c = icmp eq i32 %y, 1
17 store i1 %c, i1* %p
18 br i1 %c, label %foo, label %foo
19
20 foo:
21 ret void
22 }