llvm.org GIT mirror llvm / 4b1aa96
Switch MRI::UsedPhysRegs to a register unit bit vector. This is a more compact, less redundant representation, and it avoids scanning long lists of aliases for ARM D-registers, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166124 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 7 years ago
2 changed file(s) with 20 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
7676 return MO->Contents.Reg.Next;
7777 }
7878
79 /// UsedPhysRegs - This is a bit vector that is computed and set by the
79 /// UsedRegUnits - This is a bit vector that is computed and set by the
8080 /// register allocator, and must be kept up to date by passes that run after
8181 /// register allocation (though most don't modify this). This is used
8282 /// so that the code generator knows which callee save registers to save and
8383 /// for other target specific uses.
84 /// This vector only has bits set for registers explicitly used, not their
85 /// aliases.
86 BitVector UsedPhysRegs;
87
88 /// UsedPhysRegMask - Additional used physregs, but including aliases.
84 /// This vector has bits set for register units that are modified in the
85 /// current function. It doesn't include registers clobbered by function
86 /// calls with register mask operands.
87 BitVector UsedRegUnits;
88
89 /// UsedPhysRegMask - Additional used physregs including aliases.
90 /// This bit vector represents all the registers clobbered by function calls.
91 /// It can model things that UsedRegUnits can't, such as function calls that
92 /// clobber ymm7 but preserve the low half in xmm7.
8993 BitVector UsedPhysRegMask;
9094
9195 /// ReservedRegs - This is a bit vector of reserved registers. The target
365369 bool isPhysRegUsed(unsigned Reg) const {
366370 if (UsedPhysRegMask.test(Reg))
367371 return true;
368 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
369 if (UsedPhysRegs.test(*AI))
372 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
373 if (UsedRegUnits.test(*Units))
370374 return true;
371375 return false;
372376 }
373377
374378 /// setPhysRegUsed - Mark the specified register used in this function.
375379 /// This should only be called during and after register allocation.
376 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs.set(Reg); }
380 void setPhysRegUsed(unsigned Reg) {
381 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
382 UsedRegUnits.set(*Units);
383 }
377384
378385 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
379386 /// This corresponds to the bit mask attached to register mask operands.
384391 /// setPhysRegUnused - Mark the specified register unused in this function.
385392 /// This should only be called during and after register allocation.
386393 void setPhysRegUnused(unsigned Reg) {
387 UsedPhysRegs.reset(Reg);
388394 UsedPhysRegMask.reset(Reg);
395 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
396 UsedRegUnits.reset(*Units);
389397 }
390398
391399
2020 : TRI(&TRI), IsSSA(true), TracksLiveness(true) {
2121 VRegInfo.reserve(256);
2222 RegAllocHints.reserve(256);
23 UsedPhysRegs.resize(TRI.getNumRegs());
23 UsedRegUnits.resize(TRI.getNumRegUnits());
2424 UsedPhysRegMask.resize(TRI.getNumRegs());
2525
2626 // Create the physreg use/def lists.
3131 MachineRegisterInfo::~MachineRegisterInfo() {
3232 #ifndef NDEBUG
3333 clearVirtRegs();
34 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
34 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
3535 assert(!PhysRegUseDefLists[i] &&
3636 "PhysRegUseDefLists has entries after all instructions are deleted");
3737 #endif