llvm.org GIT mirror llvm / 4aee1bb
Fix inconsistent usage of PALIGN and PALIGNR when referring to the same instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 7 years ago
7 changed file(s) with 35 addition(s) and 34 deletion(s). Raw diff Collapse all Expand all
7676 case X86::VPALIGNR128rm:
7777 Src2Name = getRegName(MI->getOperand(1).getReg());
7878 DestName = getRegName(MI->getOperand(0).getReg());
79 DecodePALIGNMask(MVT::v16i8,
80 MI->getOperand(MI->getNumOperands()-1).getImm(),
81 ShuffleMask);
79 DecodePALIGNRMask(MVT::v16i8,
80 MI->getOperand(MI->getNumOperands()-1).getImm(),
81 ShuffleMask);
8282 break;
8383 case X86::VPALIGNR256rr:
8484 Src1Name = getRegName(MI->getOperand(2).getReg());
8686 case X86::VPALIGNR256rm:
8787 Src2Name = getRegName(MI->getOperand(1).getReg());
8888 DestName = getRegName(MI->getOperand(0).getReg());
89 DecodePALIGNMask(MVT::v32i8,
90 MI->getOperand(MI->getNumOperands()-1).getImm(),
91 ShuffleMask);
89 DecodePALIGNRMask(MVT::v32i8,
90 MI->getOperand(MI->getNumOperands()-1).getImm(),
91 ShuffleMask);
9292
9393 case X86::PSHUFDri:
9494 case X86::VPSHUFDri:
6060 ShuffleMask.push_back(NElts+i);
6161 }
6262
63 void DecodePALIGNMask(MVT VT, unsigned Imm, SmallVectorImpl &ShuffleMask) {
63 void DecodePALIGNRMask(MVT VT, unsigned Imm,
64 SmallVectorImpl &ShuffleMask) {
6465 unsigned NumElts = VT.getVectorNumElements();
6566 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8);
6667
3434 // <0,2> or <0,1,4,5>
3535 void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl &ShuffleMask);
3636
37 void DecodePALIGNMask(MVT VT, unsigned Imm, SmallVectorImpl &ShuffleMask);
37 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl &ShuffleMask);
3838
3939 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl &ShuffleMask);
4040
30033003 case X86ISD::PSHUFHW:
30043004 case X86ISD::PSHUFLW:
30053005 case X86ISD::SHUFP:
3006 case X86ISD::PALIGN:
3006 case X86ISD::PALIGNR:
30073007 case X86ISD::MOVLHPS:
30083008 case X86ISD::MOVLHPD:
30093009 case X86ISD::MOVHLPS:
30533053 SelectionDAG &DAG) {
30543054 switch(Opc) {
30553055 default: llvm_unreachable("Unknown x86 shuffle node");
3056 case X86ISD::PALIGN:
3056 case X86ISD::PALIGNR:
30573057 case X86ISD::SHUFP:
30583058 case X86ISD::VPERM2X128:
30593059 return DAG.getNode(Opc, dl, VT, V1, V2,
45914591 case X86ISD::MOVLHPS:
45924592 DecodeMOVLHPSMask(NumElems, Mask);
45934593 break;
4594 case X86ISD::PALIGN:
4594 case X86ISD::PALIGNR:
45954595 ImmN = N->getOperand(N->getNumOperands()-1);
4596 DecodePALIGNMask(VT, cast(ImmN)->getZExtValue(), Mask);
4596 DecodePALIGNRMask(VT, cast(ImmN)->getZExtValue(), Mask);
45974597 break;
45984598 case X86ISD::PSHUFD:
45994599 case X86ISD::VPERMILP:
69316931 // nodes, and remove one by one until they don't return Op anymore.
69326932
69336933 if (isPALIGNRMask(M, VT, Subtarget))
6934 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6934 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
69356935 getShufflePALIGNRImmediate(SVOp),
69366936 DAG);
69376937
1243412434 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
1243512435 case X86ISD::PTEST: return "X86ISD::PTEST";
1243612436 case X86ISD::TESTP: return "X86ISD::TESTP";
12437 case X86ISD::PALIGN: return "X86ISD::PALIGN";
12437 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
1243812438 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
1243912439 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
1244012440 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
1741517415 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
1741617416 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
1741717417 case X86ISD::SHUFP: // Handle all target specific shuffles
17418 case X86ISD::PALIGN:
17418 case X86ISD::PALIGNR:
1741917419 case X86ISD::UNPCKH:
1742017420 case X86ISD::UNPCKL:
1742117421 case X86ISD::MOVHLPS:
293293 TESTP,
294294
295295 // Several flavors of instructions with vector shuffle behaviors.
296 PALIGN,
296 PALIGNR,
297297 PSHUFD,
298298 PSHUFHW,
299299 PSHUFLW,
159159 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
160160 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
161161
162 def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
162 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
163163
164164 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
165165 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
51665166 // SSSE3 - Packed Align Instruction Patterns
51675167 //===---------------------------------------------------------------------===//
51685168
5169 multiclass ssse3_palign {
5169 multiclass ssse3_palignr {
51705170 let neverHasSideEffects = 1 in {
51715171 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
51725172 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
51865186 }
51875187 }
51885188
5189 multiclass ssse3_palign_y {
5189 multiclass ssse3_palignr_y {
51905190 let neverHasSideEffects = 1 in {
51915191 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
51925192 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
52035203 }
52045204
52055205 let Predicates = [HasAVX] in
5206 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5206 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
52075207 let Predicates = [HasAVX2] in
5208 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V, VEX_L;
5208 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
52095209 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5210 defm PALIGN : ssse3_palign<"palignr">;
5210 defm PALIGN : ssse3_palignr<"palignr">;
52115211
52125212 let Predicates = [HasAVX2] in {
5213 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5213 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
52145214 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5215 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5215 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
52165216 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5217 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5217 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
52185218 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5219 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5219 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
52205220 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
52215221 }
52225222
52235223 let Predicates = [HasAVX] in {
5224 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5224 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52255225 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5226 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5226 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52275227 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5228 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5228 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52295229 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5230 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5230 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52315231 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
52325232 }
52335233
52345234 let Predicates = [UseSSSE3] in {
5235 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5235 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52365236 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5237 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5237 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52385238 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5239 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5239 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52405240 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5241 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5241 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52425242 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
52435243 }
52445244