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Merging r245907: ------------------------------------------------------------------------ r245907 | hfinkel | 2015-08-24 19:48:28 -0400 (Mon, 24 Aug 2015) | 6 lines [PowerPC] PPCVSXFMAMutate should ignore trivial-copy addends We might end up with a trivial copy as the addend, and if so, we should ignore the corresponding FMA instruction. The trivial copy can be coalesced away later, so there's nothing to do here. We should not, however, assert. Fixes PR24544. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@252476 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
2 changed file(s) with 46 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
185185 if (!KilledProdOp)
186186 continue;
187187
188 // For virtual registers, verify that the addend source register
189 // is live here (as should have been assured above).
190 assert((!TargetRegisterInfo::isVirtualRegister(AddendSrcReg) ||
191 LIS->getInterval(AddendSrcReg).liveAt(FMAIdx)) &&
192 "Addend source register is not live!");
188 // If the addend copy is used only by this MI, then the addend source
189 // register is likely not live here. This could be fixed (based on the
190 // legality checks above, the live range for the addend source register
191 // could be extended), but it seems likely that such a trivial copy can
192 // be coalesced away later, and thus is not worth the effort.
193 if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg) &&
194 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx))
195 continue;
193196
194197 // Transform: (O2 * O3) + O1 -> (O2 * O1) + O3.
195198
0 ; RUN: llc < %s | FileCheck %s
1 target datalayout = "E-m:e-i64:64-n32:64"
2 target triple = "powerpc64-unknown-linux-gnu"
3
4 ; Function Attrs: nounwind
5 define void @LSH_recall_init(float %d_min, float %W) #0 {
6 entry:
7 br i1 undef, label %for.body.lr.ph, label %for.end
8
9 ; CHECK-LABEL: @LSH_recall_init
10 ; CHECK: xsnmsubadp
11
12 for.body.lr.ph: ; preds = %entry
13 %conv3 = fpext float %W to double
14 br label %for.body
15
16 for.body: ; preds = %for.body, %for.body.lr.ph
17 %div = fdiv fast float 0.000000e+00, 0.000000e+00
18 %add = fadd fast float %div, %d_min
19 %conv2 = fpext float %add to double
20 %0 = tail call double @llvm.sqrt.f64(double %conv2)
21 %div4 = fdiv fast double %conv3, %0
22 %call = tail call signext i32 bitcast (i32 (...)* @p_col_helper to i32 (double)*)(double %div4) #2
23 br label %for.body
24
25 for.end: ; preds = %entry
26 ret void
27 }
28
29 ; Function Attrs: nounwind readnone
30 declare double @llvm.sqrt.f64(double) #1
31
32 declare signext i32 @p_col_helper(...) #2
33
34 attributes #0 = { nounwind "no-infs-fp-math"="true" "no-nans-fp-math"="true" "target-cpu"="pwr7" "unsafe-fp-math"="true" }
35 attributes #1 = { nounwind readnone }
36 attributes #2 = { nounwind }
37