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[anyregcc] Fix callee-save mask for anyregcc Use separate callee-save masks for XMM and YMM registers for anyregcc on X86 and select the proper mask depending on the target cpu we compile for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198985 91177308-0d34-0410-b5e6-96231b3b80d8 Juergen Ributzka 6 years ago
4 changed file(s) with 141 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
728728 * ``ccc``: code 0
729729 * ``fastcc``: code 8
730730 * ``coldcc``: code 9
731 * ``webkit_jscc``: code 12
732 * ``anyregcc``: code 13
731733 * ``x86_stdcallcc``: code 64
732734 * ``x86_fastcallcc``: code 65
733735 * ``arm_apcscc``: code 66
619619 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
620620 (sequence "XMM%u", 6, 15))>;
621621
622 def CSR_MostRegs_64 : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
622 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
623623 R11, R12, R13, R14, R15, RBP,
624624 (sequence "XMM%u", 0, 15))>;
625625
626 def CSR_AllRegs_64 : CalleeSavedRegs<(add CSR_MostRegs_64, RAX, RSP,
627 (sequence "XMM%u", 16, 31),
628 (sequence "YMM%u", 0, 31),
629 (sequence "ZMM%u", 0, 31))>;
626 def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP,
627 (sequence "XMM%u", 16, 31))>;
628 def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP,
629 (sequence "YMM%u", 0, 31)),
630 (sequence "XMM%u", 0, 15))>;
630631
631632 // Standard C + YMM6-15
632633 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
233233
234234 const uint16_t *
235235 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
236 bool HasAVX = TM.getSubtarget().hasAVX();
237 bool HasAVX512 = TM.getSubtarget().hasAVX512();
238
236239 switch (MF->getFunction()->getCallingConv()) {
237240 case CallingConv::GHC:
238241 case CallingConv::HiPE:
239242 return CSR_NoRegs_SaveList;
240
241243 case CallingConv::AnyReg:
242 return CSR_AllRegs_64_SaveList;
243
244 if (HasAVX)
245 return CSR_64_AllRegs_AVX_SaveList;
246 return CSR_64_AllRegs_SaveList;
244247 case CallingConv::Intel_OCL_BI: {
245 bool HasAVX = TM.getSubtarget().hasAVX();
246 bool HasAVX512 = TM.getSubtarget().hasAVX512();
247248 if (HasAVX512 && IsWin64)
248249 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
249250 if (HasAVX512 && Is64Bit)
256257 return CSR_64_Intel_OCL_BI_SaveList;
257258 break;
258259 }
259
260260 case CallingConv::Cold:
261261 if (Is64Bit)
262 return CSR_MostRegs_64_SaveList;
262 return CSR_64_MostRegs_SaveList;
263263 break;
264
265264 default:
266265 break;
267266 }
284283 bool HasAVX = TM.getSubtarget().hasAVX();
285284 bool HasAVX512 = TM.getSubtarget().hasAVX512();
286285
287 if (CC == CallingConv::Intel_OCL_BI) {
286 switch (CC) {
287 case CallingConv::GHC:
288 case CallingConv::HiPE:
289 return CSR_NoRegs_RegMask;
290 case CallingConv::AnyReg:
291 if (HasAVX)
292 return CSR_64_AllRegs_AVX_RegMask;
293 return CSR_64_AllRegs_RegMask;
294 case CallingConv::Intel_OCL_BI: {
288295 if (IsWin64 && HasAVX512)
289296 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
290297 if (Is64Bit && HasAVX512)
296303 if (!HasAVX && !IsWin64 && Is64Bit)
297304 return CSR_64_Intel_OCL_BI_RegMask;
298305 }
299 if (CC == CallingConv::GHC || CC == CallingConv::HiPE)
300 return CSR_NoRegs_RegMask;
301 if (CC == CallingConv::AnyReg)
302 return CSR_AllRegs_64_RegMask;
303 if (!Is64Bit)
304 return CSR_32_RegMask;
305 if (CC == CallingConv::Cold)
306 return CSR_MostRegs_64_RegMask;
307 if (IsWin64)
308 return CSR_Win64_RegMask;
309 return CSR_64_RegMask;
306 case CallingConv::Cold:
307 if (Is64Bit)
308 return CSR_64_MostRegs_RegMask;
309 break;
310 default:
311 break;
312 }
313
314 if (Is64Bit) {
315 if (IsWin64)
316 return CSR_Win64_RegMask;
317 return CSR_64_RegMask;
318 }
319 return CSR_32_RegMask;
310320 }
311321
312322 const uint32_t*
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -disable-fp-elim | FileCheck %s
1 ; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck --check-prefix=SSE %s
2 ; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck --check-prefix=AVX %s
3
14
25 ; Stackmap Header: no constants - 6 callsites
36 ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
335338 ret i64 %result
336339 }
337340
341 ; Make sure all regs are spilled
342 define anyregcc void @anyregcc1() {
343 entry:
344 ;SSE-LABEL: anyregcc1
345 ;SSE: pushq %rax
346 ;SSE: pushq %rbp
347 ;SSE: pushq %r15
348 ;SSE: pushq %r14
349 ;SSE: pushq %r13
350 ;SSE: pushq %r12
351 ;SSE: pushq %r11
352 ;SSE: pushq %r10
353 ;SSE: pushq %r9
354 ;SSE: pushq %r8
355 ;SSE: pushq %rdi
356 ;SSE: pushq %rsi
357 ;SSE: pushq %rdx
358 ;SSE: pushq %rcx
359 ;SSE: pushq %rbx
360 ;SSE: movaps %xmm15
361 ;SSE-NEXT: movaps %xmm14
362 ;SSE-NEXT: movaps %xmm13
363 ;SSE-NEXT: movaps %xmm12
364 ;SSE-NEXT: movaps %xmm11
365 ;SSE-NEXT: movaps %xmm10
366 ;SSE-NEXT: movaps %xmm9
367 ;SSE-NEXT: movaps %xmm8
368 ;SSE-NEXT: movaps %xmm7
369 ;SSE-NEXT: movaps %xmm6
370 ;SSE-NEXT: movaps %xmm5
371 ;SSE-NEXT: movaps %xmm4
372 ;SSE-NEXT: movaps %xmm3
373 ;SSE-NEXT: movaps %xmm2
374 ;SSE-NEXT: movaps %xmm1
375 ;SSE-NEXT: movaps %xmm0
376 ;AVX-LABEL:anyregcc1
377 ;AVX: pushq %rax
378 ;AVX: pushq %rbp
379 ;AVX: pushq %r15
380 ;AVX: pushq %r14
381 ;AVX: pushq %r13
382 ;AVX: pushq %r12
383 ;AVX: pushq %r11
384 ;AVX: pushq %r10
385 ;AVX: pushq %r9
386 ;AVX: pushq %r8
387 ;AVX: pushq %rdi
388 ;AVX: pushq %rsi
389 ;AVX: pushq %rdx
390 ;AVX: pushq %rcx
391 ;AVX: pushq %rbx
392 ;AVX: vmovups %ymm15
393 ;AVX-NEXT: vmovups %ymm14
394 ;AVX-NEXT: vmovups %ymm13
395 ;AVX-NEXT: vmovups %ymm12
396 ;AVX-NEXT: vmovups %ymm11
397 ;AVX-NEXT: vmovups %ymm10
398 ;AVX-NEXT: vmovups %ymm9
399 ;AVX-NEXT: vmovups %ymm8
400 ;AVX-NEXT: vmovups %ymm7
401 ;AVX-NEXT: vmovups %ymm6
402 ;AVX-NEXT: vmovups %ymm5
403 ;AVX-NEXT: vmovups %ymm4
404 ;AVX-NEXT: vmovups %ymm3
405 ;AVX-NEXT: vmovups %ymm2
406 ;AVX-NEXT: vmovups %ymm1
407 ;AVX-NEXT: vmovups %ymm0
408 call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{rbp},~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15}"()
409 ret void
410 }
411
412 ; Make sure we don't spill any XMMs/YMMs
413 declare anyregcc void @foo()
414 define void @anyregcc2() {
415 entry:
416 ;SSE-LABEL: anyregcc2
417 ;SSE-NOT: movaps %xmm
418 ;AVX-LABEL: anyregcc2
419 ;AVX-NOT: vmovups %ymm
420 %a0 = call <2 x double> asm sideeffect "", "={xmm0}"() nounwind
421 %a1 = call <2 x double> asm sideeffect "", "={xmm1}"() nounwind
422 %a2 = call <2 x double> asm sideeffect "", "={xmm2}"() nounwind
423 %a3 = call <2 x double> asm sideeffect "", "={xmm3}"() nounwind
424 %a4 = call <2 x double> asm sideeffect "", "={xmm4}"() nounwind
425 %a5 = call <2 x double> asm sideeffect "", "={xmm5}"() nounwind
426 %a6 = call <2 x double> asm sideeffect "", "={xmm6}"() nounwind
427 %a7 = call <2 x double> asm sideeffect "", "={xmm7}"() nounwind
428 %a8 = call <2 x double> asm sideeffect "", "={xmm8}"() nounwind
429 %a9 = call <2 x double> asm sideeffect "", "={xmm9}"() nounwind
430 %a10 = call <2 x double> asm sideeffect "", "={xmm10}"() nounwind
431 %a11 = call <2 x double> asm sideeffect "", "={xmm11}"() nounwind
432 %a12 = call <2 x double> asm sideeffect "", "={xmm12}"() nounwind
433 %a13 = call <2 x double> asm sideeffect "", "={xmm13}"() nounwind
434 %a14 = call <2 x double> asm sideeffect "", "={xmm14}"() nounwind
435 %a15 = call <2 x double> asm sideeffect "", "={xmm15}"() nounwind
436 call anyregcc void @foo()
437 call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},{xmm8},{xmm9},{xmm10},{xmm11},{xmm12},{xmm13},{xmm14},{xmm15}"(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> %a3, <2 x double> %a4, <2 x double> %a5, <2 x double> %a6, <2 x double> %a7, <2 x double> %a8, <2 x double> %a9, <2 x double> %a10, <2 x double> %a11, <2 x double> %a12, <2 x double> %a13, <2 x double> %a14, <2 x double> %a15)
438 ret void
439 }
440
338441 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
339442 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)