llvm.org GIT mirror llvm / 49b5e6b
[RISCV] Add RISC-V ELF defines Add the necessary definitions for RISC-V ELF files, including relocs. Also make necessary trivial change to ELFYaml, llvm-objdump, and llvm-readobj in order to work with RISC-V ELFs. Differential Revision: https://reviews.llvm.org/D23557 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285708 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Bradbury 2 years ago
6 changed file(s) with 32 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
864864 return "ELF32-mips";
865865 case ELF::EM_PPC:
866866 return "ELF32-ppc";
867 case ELF::EM_RISCV:
868 return "ELF32-riscv";
867869 case ELF::EM_SPARC:
868870 case ELF::EM_SPARC32PLUS:
869871 return "ELF32-sparc";
884886 return (IsLittleEndian ? "ELF64-aarch64-little" : "ELF64-aarch64-big");
885887 case ELF::EM_PPC64:
886888 return "ELF64-ppc64";
889 case ELF::EM_RISCV:
890 return "ELF64-riscv";
887891 case ELF::EM_S390:
888892 return "ELF64-s390";
889893 case ELF::EM_SPARCV9:
939943 return Triple::ppc;
940944 case ELF::EM_PPC64:
941945 return IsLittleEndian ? Triple::ppc64le : Triple::ppc64;
946 case ELF::EM_RISCV:
947 switch (EF.getHeader()->e_ident[ELF::EI_CLASS]) {
948 case ELF::ELFCLASS32:
949 return Triple::riscv32;
950 case ELF::ELFCLASS64:
951 return Triple::riscv64;
952 default:
953 report_fatal_error("Invalid ELFCLASS!");
954 }
942955 case ELF::EM_S390:
943956 return Triple::systemz;
944957
309309 EM_NORC = 218, // Nanoradio Optimized RISC
310310 EM_CSR_KALIMBA = 219, // CSR Kalimba architecture family
311311 EM_AMDGPU = 224, // AMD GPU architecture
312 EM_RISCV = 243, // RISC-V
312313 EM_LANAI = 244, // Lanai 32-bit processor
313314 EM_BPF = 247, // Linux kernel bpf virtual machine
314315
594595 // ELF Relocation type for Lanai.
595596 enum {
596597 #include "ELFRelocs/Lanai.def"
598 };
599
600 // ELF Relocation types for RISC-V
601 enum {
602 #include "ELFRelocs/RISCV.def"
597603 };
598604
599605 // ELF Relocation types for S390/zSeries
8888 break;
8989 }
9090 break;
91 case ELF::EM_RISCV:
92 switch (Type) {
93 #include "llvm/Support/ELFRelocs/RISCV.def"
94 default:
95 break;
96 }
97 break;
9198 case ELF::EM_S390:
9299 switch (Type) {
93100 #include "llvm/Support/ELFRelocs/SystemZ.def"
193193 ECase(EM_78KOR)
194194 ECase(EM_56800EX)
195195 ECase(EM_AMDGPU)
196 ECase(EM_RISCV)
196197 ECase(EM_LANAI)
197198 ECase(EM_BPF)
198199 #undef ECase
528529 case ELF::EM_ARM:
529530 #include "llvm/Support/ELFRelocs/ARM.def"
530531 break;
532 case ELF::EM_RISCV:
533 #include "llvm/Support/ELFRelocs/RISCV.def"
534 break;
531535 case ELF::EM_LANAI:
532536 #include "llvm/Support/ELFRelocs/Lanai.def"
533537 break;
703703 case ELF::EM_HEXAGON:
704704 case ELF::EM_MIPS:
705705 case ELF::EM_BPF:
706 case ELF::EM_RISCV:
706707 res = Target;
707708 break;
708709 case ELF::EM_WEBASSEMBLY:
944944 ENUM_ENT(EM_78KOR, "EM_78KOR"),
945945 ENUM_ENT(EM_56800EX, "EM_56800EX"),
946946 ENUM_ENT(EM_AMDGPU, "EM_AMDGPU"),
947 ENUM_ENT(EM_RISCV, "RISC-V"),
947948 ENUM_ENT(EM_WEBASSEMBLY, "EM_WEBASSEMBLY"),
948949 ENUM_ENT(EM_LANAI, "EM_LANAI"),
949950 ENUM_ENT(EM_BPF, "EM_BPF"),