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[AMDGPU][MC] Enabled labels with s_call_b64 and s_cbranch_i_fork See https://bugs.llvm.org/show_bug.cgi?id=41888 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D62016 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361040 91177308-0d34-0410-b5e6-96231b3b80d8 Dmitry Preobrazhensky 5 months ago
5 changed file(s) with 31 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
719719 let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in
720720 def S_CBRANCH_I_FORK : SOPK_Pseudo <
721721 "s_cbranch_i_fork",
722 (outs), (ins SReg_64:$sdst, s16imm:$simm16),
722 (outs), (ins SReg_64:$sdst, sopp_brtarget:$simm16),
723723 "$sdst, $simm16"
724724 >;
725725
770770 def S_CALL_B64 : SOPK_Pseudo<
771771 "s_call_b64",
772772 (outs SReg_64:$sdst),
773 (ins s16imm:$simm16),
773 (ins sopp_brtarget:$simm16),
774774 "$sdst, $simm16"> {
775775 let isCall = 1;
776776 }
0 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
1 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
2
3 loop_start:
4
5 s_call_b64 s[10:11], loop_end
6 // GFX9: s_call_b64 s[10:11], loop_end ; encoding: [A,A,0x8a,0xba]
7 // GFX9-NEXT: ; fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
8 // BIN: loop_start:
9 // BIN-NEXT: s_call_b64 s[10:11], loop_end // 000000000000: BA8A0001
10
11 s_call_b64 s[10:11], loop_start
12 // GFX9: s_call_b64 s[10:11], loop_start ; encoding: [A,A,0x8a,0xba]
13 // GFX9-NEXT: ; fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
14 // BIN: s_call_b64 s[10:11], loop_start // 000000000004: BA8AFFFE
15 // BIN: loop_end:
16
17 loop_end:
18 s_nop 0
8787 // VI9: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x82,0xb7]
8888
8989 s_cbranch_i_fork s[2:3], 0x6
90 // SICI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
91 // VI9: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
90 // SICI: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x82,0xb8]
91 // VI9: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x02,0xb8]
9292
9393 // raw number mapped to known HW register
9494 s_getreg_b32 s2, 0x6
281281 // NOSICIVI: error: instruction not supported on this GPU
282282
283283 s_call_b64 s[12:13], 12609
284 // GFX9: s_call_b64 s[12:13], 0x3141 ; encoding: [0x41,0x31,0x8c,0xba]
284 // GFX9: s_call_b64 s[12:13], 12609 ; encoding: [0x41,0x31,0x8c,0xba]
285285 // NOSICIVI: error: instruction not supported on this GPU
286286
287287 s_call_b64 s[100:101], 12609
288 // GFX9: s_call_b64 s[100:101], 0x3141 ; encoding: [0x41,0x31,0xe4,0xba]
288 // GFX9: s_call_b64 s[100:101], 12609 ; encoding: [0x41,0x31,0xe4,0xba]
289289 // NOSICIVI: error: instruction not supported on this GPU
290290
291291 s_call_b64 s[10:11], 49617
292 // GFX9: s_call_b64 s[10:11], 0xc1d1 ; encoding: [0xd1,0xc1,0x8a,0xba]
293 // NOSICIVI: error: instruction not supported on this GPU
292 // GFX9: s_call_b64 s[10:11], 49617 ; encoding: [0xd1,0xc1,0x8a,0xba]
293 // NOSICIVI: error: instruction not supported on this GPU
22 # GFX9: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
33 0x00,0x00,0x9e,0xbf
44
5 # GFX9: s_call_b64 s[10:11], 0x3141 ; encoding: [0x41,0x31,0x8a,0xba]
5 # GFX9: s_call_b64 s[10:11], 12609 ; encoding: [0x41,0x31,0x8a,0xba]
66 0x41,0x31,0x8a,0xba
77
8 # GFX9: s_call_b64 s[100:101], 0x3141 ; encoding: [0x41,0x31,0xe4,0xba]
8 # GFX9: s_call_b64 s[100:101], 12609 ; encoding: [0x41,0x31,0xe4,0xba]
99 0x41,0x31,0xe4,0xba
1010
11 # GFX9: s_call_b64 s[10:11], 0xc1d1 ; encoding: [0xd1,0xc1,0x8a,0xba]
11 # GFX9: s_call_b64 s[10:11], 49617 ; encoding: [0xd1,0xc1,0x8a,0xba]
1212 0xd1,0xc1,0x8a,0xba
4444 # VI: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]
4545 0x06 0x00 0x82 0xb7
4646
47 # VI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
47 # VI: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x02,0xb8]
4848 0x06 0x00 0x02 0xb8
4949
5050 # VI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC) ; encoding: [0x06,0xf8,0x82,0xb8]