llvm.org GIT mirror llvm / 491d049
[mips] Rename accumulator register classes and FP register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 6 years ago
12 changed file(s) with 249 addition(s) and 249 deletion(s). Raw diff Collapse all Expand all
111111 parseFCCRegs(SmallVectorImpl &Operands);
112112
113113 MipsAsmParser::OperandMatchResultTy
114 parseACRegsDSP(SmallVectorImpl &Operands);
114 parseACC64DSP(SmallVectorImpl &Operands);
115115
116116 bool searchSymbolAlias(SmallVectorImpl &Operands,
117117 unsigned RegKind);
222222 Kind_AFGR64Regs,
223223 Kind_CCRRegs,
224224 Kind_FCCRegs,
225 Kind_ACRegsDSP
225 Kind_ACC64DSP
226226 };
227227
228228 private:
404404 return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
405405 }
406406
407 bool isACRegsDSPAsm() const {
408 return Kind == k_Register && Reg.Kind == Kind_ACRegsDSP;
407 bool isACC64DSPAsm() const {
408 return Kind == k_Register && Reg.Kind == Kind_ACC64DSP;
409409 }
410410
411411 /// getStartLoc - Get the location of the first token of this operand.
13671367 }
13681368
13691369 MipsAsmParser::OperandMatchResultTy
1370 MipsAsmParser::parseACRegsDSP(SmallVectorImpl &Operands) {
1370 MipsAsmParser::parseACC64DSP(SmallVectorImpl &Operands) {
13711371 // If the first token is not '$' we have an error.
13721372 if (Parser.getTok().isNot(AsmToken::Dollar))
13731373 return MatchOperand_NoMatch;
13891389 if (NumString.getAsInteger(10, IntVal))
13901390 return MatchOperand_NoMatch;
13911391
1392 unsigned Reg = matchRegisterByNumber(IntVal, Mips::ACRegsDSPRegClassID);
1392 unsigned Reg = matchRegisterByNumber(IntVal, Mips::ACC64DSPRegClassID);
13931393
13941394 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1395 Op->setRegKind(MipsOperand::Kind_ACRegsDSP);
1395 Op->setRegKind(MipsOperand::Kind_ACC64DSP);
13961396 Operands.push_back(Op);
13971397
13981398 Parser.Lex(); // Eat the register number.
137137 uint64_t Address,
138138 const void *Decoder);
139139
140 static DecodeStatus DecodeACRegsDSPRegisterClass(MCInst &Inst,
141 unsigned RegNo,
142 uint64_t Address,
143 const void *Decoder);
140 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
141 unsigned RegNo,
142 uint64_t Address,
143 const void *Decoder);
144144
145145 static DecodeStatus DecodeHIRegsDSPRegisterClass(MCInst &Inst,
146146 unsigned RegNo,
476476 return MCDisassembler::Success;
477477 }
478478
479 static DecodeStatus DecodeACRegsDSPRegisterClass(MCInst &Inst,
480 unsigned RegNo,
481 uint64_t Address,
482 const void *Decoder) {
479 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
480 unsigned RegNo,
481 uint64_t Address,
482 const void *Decoder) {
483483 if (RegNo >= 4)
484484 return MCDisassembler::Fail;
485485
486 unsigned Reg = getReg(Decoder, Mips::ACRegsDSPRegClassID, RegNo);
486 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
487487 Inst.addOperand(MCOperand::CreateReg(Reg));
488488 return MCDisassembler::Success;
489489 }
6161
6262 /// Pseudo instructions for loading and storing accumulator registers.
6363 let isPseudo = 1, isCodeGenOnly = 1 in {
64 defm LOAD_AC128 : LoadM<"", ACRegs128>;
65 defm STORE_AC128 : StoreM<"", ACRegs128>;
64 defm LOAD_ACC128 : LoadM<"", ACC128>;
65 defm STORE_ACC128 : StoreM<"", ACC128>;
6666 }
6767
6868 //===----------------------------------------------------------------------===//
190190 MULT_FM<0, 0x1c>;
191191 def DMULTu : Mult<"dmultu", IIImult, GPR64Opnd, [HI64, LO64]>,
192192 MULT_FM<0, 0x1d>;
193 def PseudoDMULT : MultDivPseudoRegs128, GPR64Opnd, MipsMult,
193 def PseudoDMULT : MultDivPseudoC128, GPR64Opnd, MipsMult,
194194 IIImult>;
195 def PseudoDMULTu : MultDivPseudoRegs128, GPR64Opnd, MipsMultu,
195 def PseudoDMULTu : MultDivPseudoC128, GPR64Opnd, MipsMultu,
196196 IIImult>;
197197 def DSDIV : Div<"ddiv", IIIdiv, GPR64Opnd, [HI64, LO64]>, MULT_FM<0, 0x1e>;
198198 def DUDIV : Div<"ddivu", IIIdiv, GPR64Opnd, [HI64, LO64]>, MULT_FM<0, 0x1f>;
199 def PseudoDSDIV : MultDivPseudoRegs128, GPR64Opnd, MipsDivRem,
199 def PseudoDSDIV : MultDivPseudoC128, GPR64Opnd, MipsDivRem,
200200 IIIdiv, 0, 1, 1>;
201 def PseudoDUDIV : MultDivPseudoRegs128, GPR64Opnd, MipsDivRemU,
201 def PseudoDUDIV : MultDivPseudoC128, GPR64Opnd, MipsDivRemU,
202202 IIIdiv, 0, 1, 1>;
203203
204204 let isCodeGenOnly = 1 in {
330330 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
331331
332332 // mflo/hi patterns.
333 def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)),
334 (EXTRACT_SUBREG ACRegs128:$ac, imm:$lohi_idx)>;
333 def : MipsPat<(i64 (ExtractLOHI ACC128:$ac, imm:$lohi_idx)),
334 (EXTRACT_SUBREG ACC128:$ac, imm:$lohi_idx)>;
335335
336336 //===----------------------------------------------------------------------===//
337337 // Instruction aliases
126126 NoItinerary>, ADD_FM<0, 0xb>;
127127 }
128128
129 def MOVZ_I_S : CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32RegsOpnd, IIFmove>,
129 def MOVZ_I_S : CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, IIFmove>,
130130 CMov_I_F_FM<18, 16>;
131131
132132 let isCodeGenOnly = 1 in
133 def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32RegsOpnd, IIFmove>,
133 def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, IIFmove>,
134134 CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]>;
135135
136 def MOVN_I_S : CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32RegsOpnd, IIFmove>,
136 def MOVN_I_S : CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, IIFmove>,
137137 CMov_I_F_FM<19, 16>;
138138
139139 let isCodeGenOnly = 1 in
140 def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32RegsOpnd, IIFmove>,
140 def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, IIFmove>,
141141 CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]>;
142142
143143 let Predicates = [NotFP64bit, HasStdEnc] in {
144 def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64RegsOpnd, IIFmove>,
144 def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, IIFmove>,
145145 CMov_I_F_FM<18, 17>;
146 def MOVN_I_D32 : CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64RegsOpnd, IIFmove>,
146 def MOVN_I_D32 : CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, IIFmove>,
147147 CMov_I_F_FM<19, 17>;
148148 }
149149
150150 let Predicates = [IsFP64bit, HasStdEnc], isCodeGenOnly = 1 in {
151 def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64RegsOpnd, IIFmove>,
151 def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, IIFmove>,
152152 CMov_I_F_FM<18, 17>;
153 def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64RegsOpnd,
153 def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd,
154154 IIFmove>, CMov_I_F_FM<18, 17>;
155 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64RegsOpnd, IIFmove>,
155 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, IIFmove>,
156156 CMov_I_F_FM<19, 17>;
157 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64RegsOpnd,
157 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd,
158158 IIFmove>, CMov_I_F_FM<19, 17>;
159159 }
160160
172172 def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, IIArith, MipsCMovFP_F>,
173173 CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]>;
174174
175 def MOVT_S : CMov_F_F_FT<"movt.s", FGR32RegsOpnd, IIFmove, MipsCMovFP_T>,
175 def MOVT_S : CMov_F_F_FT<"movt.s", FGR32Opnd, IIFmove, MipsCMovFP_T>,
176176 CMov_F_F_FM<16, 1>;
177 def MOVF_S : CMov_F_F_FT<"movf.s", FGR32RegsOpnd, IIFmove, MipsCMovFP_F>,
177 def MOVF_S : CMov_F_F_FT<"movf.s", FGR32Opnd, IIFmove, MipsCMovFP_F>,
178178 CMov_F_F_FM<16, 0>;
179179
180180 let Predicates = [NotFP64bit, HasStdEnc] in {
181 def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64RegsOpnd, IIFmove, MipsCMovFP_T>,
181 def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64Opnd, IIFmove, MipsCMovFP_T>,
182182 CMov_F_F_FM<17, 1>;
183 def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64RegsOpnd, IIFmove, MipsCMovFP_F>,
183 def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64Opnd, IIFmove, MipsCMovFP_F>,
184184 CMov_F_F_FM<17, 0>;
185185 }
186186 let Predicates = [IsFP64bit, HasStdEnc], isCodeGenOnly = 1 in {
187 def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64RegsOpnd, IIFmove, MipsCMovFP_T>,
187 def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, IIFmove, MipsCMovFP_T>,
188188 CMov_F_F_FM<17, 1>;
189 def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64RegsOpnd, IIFmove, MipsCMovFP_F>,
189 def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, IIFmove, MipsCMovFP_F>,
190190 CMov_F_F_FM<17, 0>;
191191 }
192192
379379 class EXTR_W_TY1_R2_DESC_BASE
380380 InstrItinClass itin> {
381381 dag OutOperandList = (outs GPR32:$rt);
382 dag InOperandList = (ins ACRegsDSP:$ac, GPR32:$shift_rs);
382 dag InOperandList = (ins ACC64DSP:$ac, GPR32:$shift_rs);
383383 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
384384 InstrItinClass Itinerary = itin;
385385 }
387387 class EXTR_W_TY1_R1_DESC_BASE
388388 InstrItinClass itin> {
389389 dag OutOperandList = (outs GPR32:$rt);
390 dag InOperandList = (ins ACRegsDSP:$ac, uimm16:$shift_rs);
390 dag InOperandList = (ins ACC64DSP:$ac, uimm16:$shift_rs);
391391 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
392392 InstrItinClass Itinerary = itin;
393393 }
394394
395395 class SHILO_R1_DESC_BASE {
396 dag OutOperandList = (outs ACRegsDSP:$ac);
397 dag InOperandList = (ins simm16:$shift, ACRegsDSP:$acin);
396 dag OutOperandList = (outs ACC64DSP:$ac);
397 dag InOperandList = (ins simm16:$shift, ACC64DSP:$acin);
398398 string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
399 list Pattern = [(set ACRegsDSP:$ac,
400 (OpNode immSExt6:$shift, ACRegsDSP:$acin))];
399 list Pattern = [(set ACC64DSP:$ac,
400 (OpNode immSExt6:$shift, ACC64DSP:$acin))];
401401 string Constraints = "$acin = $ac";
402402 }
403403
404404 class SHILO_R2_DESC_BASE {
405 dag OutOperandList = (outs ACRegsDSP:$ac);
406 dag InOperandList = (ins GPR32:$rs, ACRegsDSP:$acin);
405 dag OutOperandList = (outs ACC64DSP:$ac);
406 dag InOperandList = (ins GPR32:$rs, ACC64DSP:$acin);
407407 string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
408 list Pattern = [(set ACRegsDSP:$ac,
409 (OpNode GPR32:$rs, ACRegsDSP:$acin))];
408 list Pattern = [(set ACC64DSP:$ac,
409 (OpNode GPR32:$rs, ACC64DSP:$acin))];
410410 string Constraints = "$acin = $ac";
411411 }
412412
413413 class MTHLIP_DESC_BASE {
414 dag OutOperandList = (outs ACRegsDSP:$ac);
415 dag InOperandList = (ins GPR32:$rs, ACRegsDSP:$acin);
414 dag OutOperandList = (outs ACC64DSP:$ac);
415 dag InOperandList = (ins GPR32:$rs, ACC64DSP:$acin);
416416 string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
417 list Pattern = [(set ACRegsDSP:$ac,
418 (OpNode GPR32:$rs, ACRegsDSP:$acin))];
417 list Pattern = [(set ACC64DSP:$ac,
418 (OpNode GPR32:$rs, ACC64DSP:$acin))];
419419 string Constraints = "$acin = $ac";
420420 }
421421
438438 }
439439
440440 class DPA_W_PH_DESC_BASE {
441 dag OutOperandList = (outs ACRegsDSP:$ac);
442 dag InOperandList = (ins GPR32:$rs, GPR32:$rt, ACRegsDSP:$acin);
441 dag OutOperandList = (outs ACC64DSP:$ac);
442 dag InOperandList = (ins GPR32:$rs, GPR32:$rt, ACC64DSP:$acin);
443443 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
444 list Pattern = [(set ACRegsDSP:$ac,
445 (OpNode GPR32:$rs, GPR32:$rt, ACRegsDSP:$acin))];
444 list Pattern = [(set ACC64DSP:$ac,
445 (OpNode GPR32:$rs, GPR32:$rt, ACC64DSP:$acin))];
446446 string Constraints = "$acin = $ac";
447447 }
448448
449449 class MULT_DESC_BASE
450450 InstrItinClass itin> {
451 dag OutOperandList = (outs ACRegsDSP:$ac);
451 dag OutOperandList = (outs ACC64DSP:$ac);
452452 dag InOperandList = (ins GPR32:$rs, GPR32:$rt);
453453 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
454 list Pattern = [(set ACRegsDSP:$ac, (OpNode GPR32:$rs, GPR32:$rt))];
454 list Pattern = [(set ACC64DSP:$ac, (OpNode GPR32:$rs, GPR32:$rt))];
455455 InstrItinClass Itinerary = itin;
456456 int AddedComplexity = 20;
457457 bit isCommutable = 1;
459459
460460 class MADD_DESC_BASE
461461 InstrItinClass itin> {
462 dag OutOperandList = (outs ACRegsDSP:$ac);
463 dag InOperandList = (ins GPR32:$rs, GPR32:$rt, ACRegsDSP:$acin);
462 dag OutOperandList = (outs ACC64DSP:$ac);
463 dag InOperandList = (ins GPR32:$rs, GPR32:$rt, ACC64DSP:$acin);
464464 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
465 list Pattern = [(set ACRegsDSP:$ac,
466 (OpNode GPR32:$rs, GPR32:$rt, ACRegsDSP:$acin))];
465 list Pattern = [(set ACC64DSP:$ac,
466 (OpNode GPR32:$rs, GPR32:$rt, ACC64DSP:$acin))];
467467 InstrItinClass Itinerary = itin;
468468 int AddedComplexity = 20;
469469 string Constraints = "$acin = $ac";
12411241 // Pseudos.
12421242 let isPseudo = 1, isCodeGenOnly = 1 in {
12431243 // Pseudo instructions for loading and storing accumulator registers.
1244 defm LOAD_AC_DSP : LoadM<"", ACRegsDSPOpnd>;
1245 defm STORE_AC_DSP : StoreM<"", ACRegsDSPOpnd>;
1244 defm LOAD_ACC64DSP : LoadM<"", ACC64DSPOpnd>;
1245 defm STORE_ACC64DSP : StoreM<"", ACC64DSPOpnd>;
12461246
12471247 // Pseudos for loading and storing ccond field of DSP control register.
1248 defm LOAD_CCOND_DSP : LoadM<"", DSPCC>;
1249 defm STORE_CCOND_DSP : StoreM<"", DSPCC>;
1248 defm LOAD_CCOND_DSP : LoadM<"load_ccond_dsp", DSPCC>;
1249 defm STORE_CCOND_DSP : StoreM<"store_ccond_dsp", DSPCC>;
12501250 }
12511251
12521252 // Pseudo CMP and PICK instructions.
13831383
13841384 // Extr patterns.
13851385 class EXTR_W_TY1_R2_Pat :
1386 DSPPat<(i32 (OpNode GPR32:$rs, ACRegsDSP:$ac)),
1387 (Instr ACRegsDSP:$ac, GPR32:$rs)>;
1386 DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1387 (Instr ACC64DSP:$ac, GPR32:$rs)>;
13881388
13891389 class EXTR_W_TY1_R1_Pat :
1390 DSPPat<(i32 (OpNode immZExt5:$shift, ACRegsDSP:$ac)),
1391 (Instr ACRegsDSP:$ac, immZExt5:$shift)>;
1390 DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1391 (Instr ACC64DSP:$ac, immZExt5:$shift)>;
13921392
13931393 def : EXTR_W_TY1_R1_Pat;
13941394 def : EXTR_W_TY1_R2_Pat;
14051405
14061406 // mflo/hi patterns.
14071407 let AddedComplexity = 20 in
1408 def : DSPPat<(i32 (ExtractLOHI ACRegsDSP:$ac, imm:$lohi_idx)),
1409 (EXTRACT_SUBREG ACRegsDSP:$ac, imm:$lohi_idx)>;
1408 def : DSPPat<(i32 (ExtractLOHI ACC64DSP:$ac, imm:$lohi_idx)),
1409 (EXTRACT_SUBREG ACC64DSP:$ac, imm:$lohi_idx)>;
14101410
14111411 // Indexed load patterns.
14121412 class IndexedLoadPat :
9898
9999 multiclass ADDS_M
100100 SDPatternOperator OpNode = null_frag> {
101 def _D32 : ADDS_FTRegsOpnd, Itin, IsComm, OpNode>,
101 def _D32 : ADDS_FTOpnd, Itin, IsComm, OpNode>,
102102 Requires<[NotFP64bit, HasStdEnc]>;
103 def _D64 : ADDS_FTRegsOpnd, Itin, IsComm, OpNode>,
103 def _D64 : ADDS_FTOpnd, Itin, IsComm, OpNode>,
104104 Requires<[IsFP64bit, HasStdEnc]> {
105105 string DecoderNamespace = "Mips64";
106106 }
114114
115115 multiclass ABSS_M
116116 SDPatternOperator OpNode= null_frag> {
117 def _D32 : ABSS_FTRegsOpnd, AFGR64RegsOpnd, Itin, OpNode>,
117 def _D32 : ABSS_FTOpnd, AFGR64Opnd, Itin, OpNode>,
118118 Requires<[NotFP64bit, HasStdEnc]>;
119 def _D64 : ABSS_FTRegsOpnd, FGR64RegsOpnd, Itin, OpNode>,
119 def _D64 : ABSS_FTOpnd, FGR64Opnd, Itin, OpNode>,
120120 Requires<[IsFP64bit, HasStdEnc]> {
121121 string DecoderNamespace = "Mips64";
122122 }
123123 }
124124
125125 multiclass ROUND_M {
126 def _D32 : ABSS_FTRegsOpnd, AFGR64RegsOpnd, Itin>,
126 def _D32 : ABSS_FTOpnd, AFGR64Opnd, Itin>,
127127 Requires<[NotFP64bit, HasStdEnc]>;
128 def _D64 : ABSS_FTRegsOpnd, FGR64RegsOpnd, Itin>,
128 def _D64 : ABSS_FTOpnd, FGR64Opnd, Itin>,
129129 Requires<[IsFP64bit, HasStdEnc]> {
130130 let DecoderNamespace = "Mips64";
131131 }
230230 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC>, C_COND_FM;
231231 }
232232
233 defm S : C_COND_M<"s", FGR32RegsOpnd, 16>;
234 defm D32 : C_COND_M<"d", AFGR64RegsOpnd, 17>,
233 defm S : C_COND_M<"s", FGR32Opnd, 16>;
234 defm D32 : C_COND_M<"d", AFGR64Opnd, 17>,
235235 Requires<[NotFP64bit, HasStdEnc]>;
236236 let DecoderNamespace = "Mips64" in
237 defm D64 : C_COND_M<"d", FGR64RegsOpnd, 17>, Requires<[IsFP64bit, HasStdEnc]>;
237 defm D64 : C_COND_M<"d", FGR64Opnd, 17>, Requires<[IsFP64bit, HasStdEnc]>;
238238
239239 //===----------------------------------------------------------------------===//
240240 // Floating Point Instructions
241241 //===----------------------------------------------------------------------===//
242 def ROUND_W_S : ABSS_FT<"round.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
242 def ROUND_W_S : ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
243243 ABSS_FM<0xc, 16>;
244 def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
244 def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
245245 ABSS_FM<0xd, 16>;
246 def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
246 def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
247247 ABSS_FM<0xe, 16>;
248 def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
248 def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
249249 ABSS_FM<0xf, 16>;
250 def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
250 def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
251251 ABSS_FM<0x24, 16>;
252252
253253 defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
257257 defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>;
258258
259259 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
260 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
260 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
261261 ABSS_FM<0x8, 16>;
262 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
262 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
263263 ABSS_FM<0x8, 17>;
264 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
264 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
265265 ABSS_FM<0x9, 16>;
266 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
266 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
267267 ABSS_FM<0x9, 17>;
268 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
268 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
269269 ABSS_FM<0xa, 16>;
270 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
270 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
271271 ABSS_FM<0xa, 17>;
272 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
272 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
273273 ABSS_FM<0xb, 16>;
274 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
274 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
275275 ABSS_FM<0xb, 17>;
276276 }
277277
278 def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
278 def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, IIFcvt>,
279279 ABSS_FM<0x20, 20>;
280 def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
280 def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
281281 ABSS_FM<0x25, 16>;
282 def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
282 def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
283283 ABSS_FM<0x25, 17>;
284284
285285 let Predicates = [NotFP64bit, HasStdEnc] in {
286 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32RegsOpnd, AFGR64RegsOpnd, IIFcvt>,
286 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
287287 ABSS_FM<0x20, 17>;
288 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
288 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, IIFcvt>,
289289 ABSS_FM<0x21, 20>;
290 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
290 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, IIFcvt>,
291291 ABSS_FM<0x21, 16>;
292292 }
293293
294294 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
295 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32RegsOpnd, FGR64RegsOpnd, IIFcvt>,
295 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, IIFcvt>,
296296 ABSS_FM<0x20, 17>;
297 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32RegsOpnd, FGR64RegsOpnd, IIFcvt>,
297 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, IIFcvt>,
298298 ABSS_FM<0x20, 21>;
299 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
299 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, IIFcvt>,
300300 ABSS_FM<0x21, 20>;
301 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
301 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
302302 ABSS_FM<0x21, 16>;
303 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
303 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, IIFcvt>,
304304 ABSS_FM<0x21, 21>;
305305 }
306306
307307 let isPseudo = 1, isCodeGenOnly = 1 in {
308 def PseudoCVT_S_W : ABSS_FT<"", FGR32RegsOpnd, GPR32Opnd, IIFcvt>;
309 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64RegsOpnd, GPR32Opnd, IIFcvt>;
310 def PseudoCVT_S_L : ABSS_FT<"", FGR64RegsOpnd, GPR64Opnd, IIFcvt>;
311 def PseudoCVT_D64_W : ABSS_FT<"", FGR64RegsOpnd, GPR32Opnd, IIFcvt>;
312 def PseudoCVT_D64_L : ABSS_FT<"", FGR64RegsOpnd, GPR64Opnd, IIFcvt>;
308 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, IIFcvt>;
309 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, IIFcvt>;
310 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>;
311 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, IIFcvt>;
312 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>;
313313 }
314314
315315 let Predicates = [NoNaNsFPMath, HasStdEnc] in {
316 def FABS_S : ABSS_FT<"abs.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt, fabs>,
316 def FABS_S : ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, IIFcvt, fabs>,
317317 ABSS_FM<0x5, 16>;
318 def FNEG_S : ABSS_FT<"neg.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt, fneg>,
318 def FNEG_S : ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, IIFcvt, fneg>,
319319 ABSS_FM<0x7, 16>;
320320 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
321321 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
322322 }
323323
324 def FSQRT_S : ABSS_FT<"sqrt.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFsqrtSingle,
324 def FSQRT_S : ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, IIFsqrtSingle,
325325 fsqrt>, ABSS_FM<0x4, 16>;
326326 defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
327327
333333 /// Move Control Registers From/To CPU Registers
334334 def CFC1 : MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, IIFmove>, MFC1_FM<2>;
335335 def CTC1 : MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, IIFmove>, MFC1_FM<6>;
336 def MFC1 : MFC1_FT<"mfc1", GPR32Opnd, FGR32RegsOpnd, IIFmoveC1, bitconvert>,
336 def MFC1 : MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, IIFmoveC1, bitconvert>,
337337 MFC1_FM<0>;
338 def MTC1 : MTC1_FT<"mtc1", FGR32RegsOpnd, GPR32Opnd, IIFmoveC1, bitconvert>,
338 def MTC1 : MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, IIFmoveC1, bitconvert>,
339339 MFC1_FM<4>;
340 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64RegsOpnd, IIFmoveC1,
340 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, IIFmoveC1,
341341 bitconvert>, MFC1_FM<1>;
342 def DMTC1 : MTC1_FT<"dmtc1", FGR64RegsOpnd, GPR64Opnd, IIFmoveC1,
342 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, IIFmoveC1,
343343 bitconvert>, MFC1_FM<5>;
344344
345 def FMOV_S : ABSS_FT<"mov.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFmove>,
345 def FMOV_S : ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, IIFmove>,
346346 ABSS_FM<0x6, 16>;
347 def FMOV_D32 : ABSS_FT<"mov.d", AFGR64RegsOpnd, AFGR64RegsOpnd, IIFmove>,
347 def FMOV_D32 : ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, IIFmove>,
348348 ABSS_FM<0x6, 17>, Requires<[NotFP64bit, HasStdEnc]>;
349 def FMOV_D64 : ABSS_FT<"mov.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFmove>,
349 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, IIFmove>,
350350 ABSS_FM<0x6, 17>, Requires<[IsFP64bit, HasStdEnc]> {
351351 let DecoderNamespace = "Mips64";
352352 }
353353
354354 /// Floating Point Memory Instructions
355355 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
356 def LWC1_P8 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem64, load>,
356 def LWC1_P8 : LW_FT<"lwc1", FGR32Opnd, IIFLoad, mem64, load>,
357357 LW_FM<0x31>;
358 def SWC1_P8 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem64, store>,
358 def SWC1_P8 : SW_FT<"swc1", FGR32Opnd, IIFStore, mem64, store>,
359359 LW_FM<0x39>;
360 def LDC164_P8 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem64, load>,
360 def LDC164_P8 : LW_FT<"ldc1", FGR64Opnd, IIFLoad, mem64, load>,
361361 LW_FM<0x35> {
362362 let isCodeGenOnly =1;
363363 }
364 def SDC164_P8 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem64, store>,
364 def SDC164_P8 : SW_FT<"sdc1", FGR64Opnd, IIFStore, mem64, store>,
365365 LW_FM<0x3d> {
366366 let isCodeGenOnly =1;
367367 }
368368 }
369369
370370 let Predicates = [NotN64, HasStdEnc] in {
371 def LWC1 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem, load>, LW_FM<0x31>;
372 def SWC1 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem, store>, LW_FM<0x39>;
371 def LWC1 : LW_FT<"lwc1", FGR32Opnd, IIFLoad, mem, load>, LW_FM<0x31>;
372 def SWC1 : SW_FT<"swc1", FGR32Opnd, IIFStore, mem, store>, LW_FM<0x39>;
373373 }
374374
375375 let Predicates = [NotN64, HasMips64, HasStdEnc],
376376 DecoderNamespace = "Mips64" in {
377 def LDC164 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem, load>, LW_FM<0x35>;
378 def SDC164 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem, store>, LW_FM<0x3d>;
377 def LDC164 : LW_FT<"ldc1", FGR64Opnd, IIFLoad, mem, load>, LW_FM<0x35>;
378 def SDC164 : SW_FT<"sdc1", FGR64Opnd, IIFStore, mem, store>, LW_FM<0x3d>;
379379 }
380380
381381 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
382382 let isPseudo = 1, isCodeGenOnly = 1 in {
383 def PseudoLDC1 : LW_FT<"", AFGR64RegsOpnd, IIFLoad, mem, load>;
384 def PseudoSDC1 : SW_FT<"", AFGR64RegsOpnd, IIFStore, mem, store>;
385 }
386 def LDC1 : LW_FT<"ldc1", AFGR64RegsOpnd, IIFLoad, mem>, LW_FM<0x35>;
387 def SDC1 : SW_FT<"sdc1", AFGR64RegsOpnd, IIFStore, mem>, LW_FM<0x3d>;
383 def PseudoLDC1 : LW_FT<"", AFGR64Opnd, IIFLoad, mem, load>;
384 def PseudoSDC1 : SW_FT<"", AFGR64Opnd, IIFStore, mem, store>;
385 }
386 def LDC1 : LW_FT<"ldc1", AFGR64Opnd, IIFLoad, mem>, LW_FM<0x35>;
387 def SDC1 : SW_FT<"sdc1", AFGR64Opnd, IIFStore, mem>, LW_FM<0x3d>;
388388 }
389389
390390 // Indexed loads and stores.
391391 let Predicates = [HasFPIdx, HasStdEnc] in {
392 def LWXC1 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, GPR32Opnd, IIFLoad, load>,
392 def LWXC1 : LWXC1_FT<"lwxc1", FGR32Opnd, GPR32Opnd, IIFLoad, load>,
393393 LWXC1_FM<0>;
394 def SWXC1 : SWXC1_FT<"swxc1", FGR32RegsOpnd, GPR32Opnd, IIFStore, store>,
394 def SWXC1 : SWXC1_FT<"swxc1", FGR32Opnd, GPR32Opnd, IIFStore, store>,
395395 SWXC1_FM<8>;
396396 }
397397
398398 let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
399 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64RegsOpnd, GPR32Opnd, IIFLoad, load>,
399 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, GPR32Opnd, IIFLoad, load>,
400400 LWXC1_FM<1>;
401 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64RegsOpnd, GPR32Opnd, IIFStore, store>,
401 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, GPR32Opnd, IIFStore, store>,
402402 SWXC1_FM<9>;
403403 }
404404
405405 let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
406 def LDXC164 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, GPR32Opnd, IIFLoad, load>,
406 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, GPR32Opnd, IIFLoad, load>,
407407 LWXC1_FM<1>;
408 def SDXC164 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, GPR32Opnd, IIFStore, store>,
408 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, GPR32Opnd, IIFStore, store>,
409409 SWXC1_FM<9>;
410410 }
411411
412412 // n64
413413 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
414 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, GPR64Opnd, IIFLoad, load>,
414 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32Opnd, GPR64Opnd, IIFLoad, load>,
415415 LWXC1_FM<0>;
416 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, GPR64Opnd, IIFLoad,
416 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64Opnd, GPR64Opnd, IIFLoad,
417417 load>, LWXC1_FM<1>;
418 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32RegsOpnd, GPR64Opnd, IIFStore,
418 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32Opnd, GPR64Opnd, IIFStore,
419419 store>, SWXC1_FM<8>;
420 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, GPR64Opnd, IIFStore,
420 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64Opnd, GPR64Opnd, IIFStore,
421421 store>, SWXC1_FM<9>;
422422 }
423423
424424 // Load/store doubleword indexed unaligned.
425425 let Predicates = [NotMips64, HasStdEnc] in {
426 def LUXC1 : LWXC1_FT<"luxc1", AFGR64RegsOpnd, GPR32Opnd, IIFLoad>,
426 def LUXC1 : LWXC1_FT<"luxc1", AFGR64Opnd, GPR32Opnd, IIFLoad>,
427427 LWXC1_FM<0x5>;
428 def SUXC1 : SWXC1_FT<"suxc1", AFGR64RegsOpnd, GPR32Opnd, IIFStore>,
428 def SUXC1 : SWXC1_FT<"suxc1", AFGR64Opnd, GPR32Opnd, IIFStore>,
429429 SWXC1_FM<0xd>;
430430 }
431431
432432 let Predicates = [HasMips64, HasStdEnc],
433433 DecoderNamespace="Mips64" in {
434 def LUXC164 : LWXC1_FT<"luxc1", FGR64RegsOpnd, GPR32Opnd, IIFLoad>,
434 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, GPR32Opnd, IIFLoad>,
435435 LWXC1_FM<0x5>;
436 def SUXC164 : SWXC1_FT<"suxc1", FGR64RegsOpnd, GPR32Opnd, IIFStore>,
436 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, GPR32Opnd, IIFStore>,
437437 SWXC1_FM<0xd>;
438438 }
439439
440440 /// Floating-point Aritmetic
441 def FADD_S : ADDS_FT<"add.s", FGR32RegsOpnd, IIFadd, 1, fadd>,
441 def FADD_S : ADDS_FT<"add.s", FGR32Opnd, IIFadd, 1, fadd>,
442442 ADDS_FM<0x00, 16>;
443443 defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
444 def FDIV_S : ADDS_FT<"div.s", FGR32RegsOpnd, IIFdivSingle, 0, fdiv>,
444 def FDIV_S : ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>,
445445 ADDS_FM<0x03, 16>;
446446 defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
447 def FMUL_S : ADDS_FT<"mul.s", FGR32RegsOpnd, IIFmulSingle, 1, fmul>,
447 def FMUL_S : ADDS_FT<"mul.s", FGR32Opnd, IIFmulSingle, 1, fmul>,
448448 ADDS_FM<0x02, 16>;
449449 defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
450 def FSUB_S : ADDS_FT<"sub.s", FGR32RegsOpnd, IIFadd, 0, fsub>,
450 def FSUB_S : ADDS_FT<"sub.s", FGR32Opnd, IIFadd, 0, fsub>,
451451 ADDS_FM<0x01, 16>;
452452 defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
453453
454454 let Predicates = [HasMips32r2, HasStdEnc] in {
455 def MADD_S : MADDS_FT<"madd.s", FGR32RegsOpnd, IIFmulSingle, fadd>,
455 def MADD_S : MADDS_FT<"madd.s", FGR32Opnd, IIFmulSingle, fadd>,
456456 MADDS_FM<4, 0>;
457 def MSUB_S : MADDS_FT<"msub.s", FGR32RegsOpnd, IIFmulSingle, fsub>,
457 def MSUB_S : MADDS_FT<"msub.s", FGR32Opnd, IIFmulSingle, fsub>,
458458 MADDS_FM<5, 0>;
459459 }
460460
461461 let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
462 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32RegsOpnd, IIFmulSingle, fadd>,
462 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32Opnd, IIFmulSingle, fadd>,
463463 MADDS_FM<6, 0>;
464 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32RegsOpnd, IIFmulSingle, fsub>,
464 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32Opnd, IIFmulSingle, fsub>,
465465 MADDS_FM<7, 0>;
466466 }
467467
468468 let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
469 def MADD_D32 : MADDS_FT<"madd.d", AFGR64RegsOpnd, IIFmulDouble, fadd>,
469 def MADD_D32 : MADDS_FT<"madd.d", AFGR64Opnd, IIFmulDouble, fadd>,
470470 MADDS_FM<4, 1>;
471 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64RegsOpnd, IIFmulDouble, fsub>,
471 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64Opnd, IIFmulDouble, fsub>,
472472 MADDS_FM<5, 1>;
473473 }
474474
475475 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
476 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64RegsOpnd, IIFmulDouble, fadd>,
476 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64Opnd, IIFmulDouble, fadd>,
477477 MADDS_FM<6, 1>;
478 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64RegsOpnd, IIFmulDouble, fsub>,
478 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64Opnd, IIFmulDouble, fsub>,
479479 MADDS_FM<7, 1>;
480480 }
481481
482482 let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
483 def MADD_D64 : MADDS_FT<"madd.d", FGR64RegsOpnd, IIFmulDouble, fadd>,
483 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, IIFmulDouble, fadd>,
484484 MADDS_FM<4, 1>;
485 def MSUB_D64 : MADDS_FT<"msub.d", FGR64RegsOpnd, IIFmulDouble, fsub>,
485 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, IIFmulDouble, fsub>,
486486 MADDS_FM<5, 1>;
487487 }
488488
489489 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
490490 isCodeGenOnly=1 in {
491 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64RegsOpnd, IIFmulDouble, fadd>,
491 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, IIFmulDouble, fadd>,
492492 MADDS_FM<6, 1>;
493 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64RegsOpnd, IIFmulDouble, fsub>,
493 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, IIFmulDouble, fsub>,
494494 MADDS_FM<7, 1>;
495495 }
496496
542542 // This pseudo instr gets expanded into 2 mtc1 instrs after register
543543 // allocation.
544544 def BuildPairF64 :
545 PseudoSE<(outs AFGR64RegsOpnd:$dst),
545 PseudoSE<(outs AFGR64Opnd:$dst),
546546 (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
547 [(set AFGR64RegsOpnd:$dst,
547 [(set AFGR64Opnd:$dst,
548548 (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
549549
550550 // This pseudo instr gets expanded into 2 mfc1 instrs after register
552552 // if n is 0, lower part of src is extracted.
553553 // if n is 1, higher part of src is extracted.
554554 def ExtractElementF64 :
555 PseudoSE<(outs GPR32Opnd:$dst), (ins AFGR64RegsOpnd:$src, i32imm:$n),
555 PseudoSE<(outs GPR32Opnd:$dst), (ins AFGR64Opnd:$src, i32imm:$n),
556556 [(set GPR32Opnd:$dst,
557 (MipsExtractElementF64 AFGR64RegsOpnd:$src, imm:$n))]>;
557 (MipsExtractElementF64 AFGR64Opnd:$src, imm:$n))]>;
558558
559559 //===----------------------------------------------------------------------===//
560560 // InstAliases.
570570
571571 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
572572 (PseudoCVT_S_W GPR32Opnd:$src)>;
573 def : MipsPat<(MipsTruncIntFP FGR32RegsOpnd:$src),
574 (TRUNC_W_S FGR32RegsOpnd:$src)>;
573 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
574 (TRUNC_W_S FGR32Opnd:$src)>;
575575
576576 let Predicates = [NotFP64bit, HasStdEnc] in {
577577 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
578578 (PseudoCVT_D32_W GPR32Opnd:$src)>;
579 def : MipsPat<(MipsTruncIntFP AFGR64RegsOpnd:$src),
580 (TRUNC_W_D32 AFGR64RegsOpnd:$src)>;
581 def : MipsPat<(f32 (fround AFGR64RegsOpnd:$src)),
582 (CVT_S_D32 AFGR64RegsOpnd:$src)>;
583 def : MipsPat<(f64 (fextend FGR32RegsOpnd:$src)),
584 (CVT_D32_S FGR32RegsOpnd:$src)>;
579 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
580 (TRUNC_W_D32 AFGR64Opnd:$src)>;
581 def : MipsPat<(f32 (fround AFGR64Opnd:$src)),
582 (CVT_S_D32 AFGR64Opnd:$src)>;
583 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
584 (CVT_D32_S FGR32Opnd:$src)>;
585585 }
586586
587587 let Predicates = [IsFP64bit, HasStdEnc] in {
595595 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
596596 (PseudoCVT_D64_L GPR64Opnd:$src)>;
597597
598 def : MipsPat<(MipsTruncIntFP FGR64RegsOpnd:$src),
599 (TRUNC_W_D64 FGR64RegsOpnd:$src)>;
600 def : MipsPat<(MipsTruncIntFP FGR32RegsOpnd:$src),
601 (TRUNC_L_S FGR32RegsOpnd:$src)>;
602 def : MipsPat<(MipsTruncIntFP FGR64RegsOpnd:$src),
603 (TRUNC_L_D64 FGR64RegsOpnd:$src)>;
604
605 def : MipsPat<(f32 (fround FGR64RegsOpnd:$src)),
606 (CVT_S_D64 FGR64RegsOpnd:$src)>;
607 def : MipsPat<(f64 (fextend FGR32RegsOpnd:$src)),
608 (CVT_D64_S FGR32RegsOpnd:$src)>;
598 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
599 (TRUNC_W_D64 FGR64Opnd:$src)>;
600 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
601 (TRUNC_L_S FGR32Opnd:$src)>;
602 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
603 (TRUNC_L_D64 FGR64Opnd:$src)>;
604
605 def : MipsPat<(f32 (fround FGR64Opnd:$src)),
606 (CVT_S_D64 FGR64Opnd:$src)>;
607 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
608 (CVT_D64_S FGR32Opnd:$src)>;
609609 }
610610
611611 // Patterns for loads/stores with a reg+imm operand.
697697 // Pseudo multiply add/sub instruction with explicit accumulator register
698698 // operands.
699699 class MAddSubPseudo
700 : PseudoSE<(outs ACRegs:$ac),
701 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACRegs:$acin),
702 [(set ACRegs:$ac,
703 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACRegs:$acin))],
700 : PseudoSE<(outs ACC64:$ac),
701 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
702 [(set ACC64:$ac,
703 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
704704 IIImult>,
705705 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
706706 string Constraints = "$acin = $ac";
874874
875875 /// Pseudo instructions for loading and storing accumulator registers.
876876 let isPseudo = 1, isCodeGenOnly = 1 in {
877 defm LOAD_AC64 : LoadM<"", ACRegs>;
878 defm STORE_AC64 : StoreM<"", ACRegs>;
877 defm LOAD_ACC64 : LoadM<"", ACC64>;
878 defm STORE_ACC64 : StoreM<"", ACC64>;
879879 }
880880
881881 //===----------------------------------------------------------------------===//
10321032 MULT_FM<0, 0x18>;
10331033 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI, LO]>,
10341034 MULT_FM<0, 0x19>;
1035 def PseudoMULT : MultDivPseudo;
1036 def PseudoMULTu : MultDivPseudo, IIImult>;
1035 def PseudoMULT : MultDivPseudo, IIImult>;
1036 def PseudoMULTu : MultDivPseudo;
10371037 def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI, LO]>, MULT_FM<0, 0x1a>;
10381038 def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI, LO]>, MULT_FM<0, 0x1b>;
1039 def PseudoSDIV : MultDivPseudoRegs, GPR32Opnd, MipsDivRem, IIIdiv,
1039 def PseudoSDIV : MultDivPseudoC64, GPR32Opnd, MipsDivRem, IIIdiv,
10401040 0, 1, 1>;
1041 def PseudoUDIV : MultDivPseudoRegs, GPR32Opnd, MipsDivRemU, IIIdiv,
1041 def PseudoUDIV : MultDivPseudoC64, GPR32Opnd, MipsDivRemU, IIIdiv,
10421042 0, 1, 1>;
10431043
10441044 def MTHI : MoveToLOHI<"mthi", GPR32Opnd, [HI]>, MTLO_FM<0x11>;
13691369 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
13701370
13711371 // mflo/hi patterns.
1372 def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)),
1373 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>;
1372 def : MipsPat<(i32 (ExtractLOHI ACC64:$ac, imm:$lohi_idx)),
1373 (EXTRACT_SUBREG ACC64:$ac, imm:$lohi_idx)>;
13741374
13751375 // Load halfword/word patterns.
13761376 let AddedComplexity = 40 in {
6363 }
6464
6565 // Accumulator Registers
66 class ACC Enc, string n, list subregs>
66 class ACCReg Enc, string n, list subregs>
6767 : MipsRegWithSubRegs {
6868 let SubRegIndices = [sub_lo, sub_hi];
6969 let CoveredBySubRegs = 1;
191191 def HWR29 : MipsReg<29, "29">;
192192
193193 // Accum registers
194 def AC0 : ACC<0, "ac0", [LO, HI]>;
195 def AC1 : ACC<1, "ac1", [LO1, HI1]>;
196 def AC2 : ACC<2, "ac2", [LO2, HI2]>;
197 def AC3 : ACC<3, "ac3", [LO3, HI3]>;
198
199 def AC0_64 : ACC<0, "ac0", [LO64, HI64]>;
194 def AC0 : ACCReg<0, "ac0", [LO, HI]>;
195 def AC1 : ACCReg<1, "ac1", [LO1, HI1]>;
196 def AC2 : ACCReg<2, "ac2", [LO2, HI2]>;
197 def AC3 : ACCReg<3, "ac3", [LO3, HI3]>;
198
199 def AC0_64 : ACCReg<0, "ac0", [LO64, HI64]>;
200200
201201 // DSP-ASE control register fields.
202202 def DSPPos : Register<"">;
313313 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
314314
315315 // Accumulator Registers
316 def ACRegs : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
316 def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
317317 let Size = 64;
318318 }
319319
320 def ACRegs128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
320 def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
321321 let Size = 128;
322322 }
323323
324 def ACRegsDSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
324 def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
325325 let Size = 64;
326326 }
327327
342342 let ParserMethod = "parseGPR64";
343343 }
344344
345 def ACRegsDSPAsmOperand : MipsAsmRegOperand {
346 let Name = "ACRegsDSPAsm";
347 let ParserMethod = "parseACRegsDSP";
345 def ACC64DSPAsmOperand : MipsAsmRegOperand {
346 let Name = "ACC64DSPAsm";
347 let ParserMethod = "parseACC64DSP";
348348 }
349349
350350 def CCRAsmOperand : MipsAsmRegOperand {
393393 let ParserMatchClass = HWRegsAsmOperand;
394394 }
395395
396 def AFGR64RegsOpnd : RegisterOperand {
396 def AFGR64Opnd : RegisterOperand {
397397 let ParserMatchClass = AFGR64AsmOperand;
398398 }
399399
400 def FGR64RegsOpnd : RegisterOperand {
400 def FGR64Opnd : RegisterOperand {
401401 let ParserMatchClass = FGR64AsmOperand;
402402 }
403403
404 def FGR32RegsOpnd : RegisterOperand {
404 def FGR32Opnd : RegisterOperand {
405405 let ParserMatchClass = FGR32AsmOperand;
406406 }
407407
409409 let ParserMatchClass = FCCRegsAsmOperand;
410410 }
411411
412 def ACRegsDSPOpnd : RegisterOperand {
413 let ParserMatchClass = ACRegsDSPAsmOperand;
414 }
412 def ACC64DSPOpnd : RegisterOperand {
413 let ParserMatchClass = ACC64DSPAsmOperand;
414 }
7676 case Mips::STORE_CCOND_DSP_P8:
7777 expandStoreCCond(MBB, I);
7878 break;
79 case Mips::LOAD_AC64:
80 case Mips::LOAD_AC64_P8:
81 case Mips::LOAD_AC_DSP:
82 case Mips::LOAD_AC_DSP_P8:
79 case Mips::LOAD_ACC64:
80 case Mips::LOAD_ACC64_P8:
81 case Mips::LOAD_ACC64DSP:
82 case Mips::LOAD_ACC64DSP_P8:
8383 expandLoadACC(MBB, I, 4);
8484 break;
85 case Mips::LOAD_AC128:
86 case Mips::LOAD_AC128_P8:
85 case Mips::LOAD_ACC128:
86 case Mips::LOAD_ACC128_P8:
8787 expandLoadACC(MBB, I, 8);
8888 break;
89 case Mips::STORE_AC64:
90 case Mips::STORE_AC64_P8:
91 case Mips::STORE_AC_DSP:
92 case Mips::STORE_AC_DSP_P8:
89 case Mips::STORE_ACC64:
90 case Mips::STORE_ACC64_P8:
91 case Mips::STORE_ACC64DSP:
92 case Mips::STORE_ACC64DSP_P8:
9393 expandStoreACC(MBB, I, 4);
9494 break;
95 case Mips::STORE_AC128:
96 case Mips::STORE_AC128_P8:
95 case Mips::STORE_ACC128:
96 case Mips::STORE_ACC128_P8:
9797 expandStoreACC(MBB, I, 8);
9898 break;
9999 case TargetOpcode::COPY:
209209 bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
210210 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
211211
212 if (Mips::ACRegsDSPRegClass.contains(Dst, Src))
212 if (Mips::ACC64DSPRegClass.contains(Dst, Src))
213213 return expandCopyACC(MBB, I, Dst, Src, 4);
214214
215 if (Mips::ACRegs128RegClass.contains(Dst, Src))
215 if (Mips::ACC128RegClass.contains(Dst, Src))
216216 return expandCopyACC(MBB, I, Dst, Src, 8);
217217
218218 return false;
424424 }
425425
426426 case MipsISD::InsertLOHI: {
427 unsigned RCID = Subtarget.hasDSP() ? Mips::ACRegsDSPRegClassID :
428 Mips::ACRegsRegClassID;
427 unsigned RCID = Subtarget.hasDSP() ? Mips::ACC64DSPRegClassID :
428 Mips::ACC64RegClassID;
429429 SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32);
430430 SDValue LoIdx = CurDAG->getTargetConstant(Mips::sub_lo, MVT::i32);
431431 SDValue HiIdx = CurDAG->getTargetConstant(Mips::sub_hi, MVT::i32);
3737
3838 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
3939 if (VT == MVT::Untyped)
40 return Subtarget->hasDSP() ? &Mips::ACRegsDSPRegClass :
41 &Mips::ACRegsRegClass;
40 return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
41 &Mips::ACC64RegClass;
4242
4343 return TargetLowering::getRepRegClassFor(VT);
4444 }
188188 Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
189189 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
190190 Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
191 else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
192 Opc = IsN64 ? Mips::STORE_AC64_P8 : Mips::STORE_AC64;
193 else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC))
194 Opc = IsN64 ? Mips::STORE_AC_DSP_P8 : Mips::STORE_AC_DSP;
195 else if (Mips::ACRegs128RegClass.hasSubClassEq(RC))
196 Opc = IsN64 ? Mips::STORE_AC128_P8 : Mips::STORE_AC128;
191 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
192 Opc = IsN64 ? Mips::STORE_ACC64_P8 : Mips::STORE_ACC64;
193 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
194 Opc = IsN64 ? Mips::STORE_ACC64DSP_P8 : Mips::STORE_ACC64DSP;
195 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
196 Opc = IsN64 ? Mips::STORE_ACC128_P8 : Mips::STORE_ACC128;
197197 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
198198 Opc = IsN64 ? Mips::STORE_CCOND_DSP_P8 : Mips::STORE_CCOND_DSP;
199199 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
221221 Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
222222 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
223223 Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
224 else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
225 Opc = IsN64 ? Mips::LOAD_AC64_P8 : Mips::LOAD_AC64;
226 else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC))
227 Opc = IsN64 ? Mips::LOAD_AC_DSP_P8 : Mips::LOAD_AC_DSP;
228 else if (Mips::ACRegs128RegClass.hasSubClassEq(RC))
229 Opc = IsN64 ? Mips::LOAD_AC128_P8 : Mips::LOAD_AC128;
224 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
225 Opc = IsN64 ? Mips::LOAD_ACC64_P8 : Mips::LOAD_ACC64;
226 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
227 Opc = IsN64 ? Mips::LOAD_ACC64DSP_P8 : Mips::LOAD_ACC64DSP;
228 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
229 Opc = IsN64 ? Mips::LOAD_ACC128_P8 : Mips::LOAD_ACC128;
230230 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
231231 Opc = IsN64 ? Mips::LOAD_CCOND_DSP_P8 : Mips::LOAD_CCOND_DSP;
232232 else if (Mips::FGR32RegClass.hasSubClassEq(RC))