llvm.org GIT mirror llvm / 491a136
Add a RegisterClassInfo class that lazily caches information about register classes. It provides information for each register class that cannot be determined statically, like: - The number of allocatable registers in a class after filtering out the reserved and invalid registers. - The preferred allocation order with registers that overlap callee-saved registers last. - The last callee-saved register that overlaps a given physical register. This information usually doesn't change between functions, so it is reused for compiling multiple functions when possible. The many possible combinations of reserved and callee saves registers makes it unfeasible to compute this information statically in TableGen. Use RegisterClassInfo to count available registers in various heuristics in SimpleRegisterCoalescing, making the pass run 4% faster. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132450 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 9 years ago
5 changed file(s) with 215 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
6666 RegAllocGreedy.cpp
6767 RegAllocLinearScan.cpp
6868 RegAllocPBQP.cpp
69 RegisterClassInfo.cpp
6970 RegisterCoalescer.cpp
7071 RegisterScavenging.cpp
7172 RenderMachineFunction.cpp
0 //===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RegisterClassInfo class which provides dynamic
10 // information about target register classes. Callee saved and reserved
11 // registers depends on calling conventions and other dynamic information, so
12 // some things cannot be determined statically.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "RegisterClassInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/Target/TargetMachine.h"
19
20 using namespace llvm;
21
22 RegisterClassInfo::RegisterClassInfo() : Tag(0), TRI(0) {}
23
24 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
25 bool Update = false;
26 MF = &mf;
27
28 // Allocate new array the first time we see a new target.
29 if (MF->getTarget().getRegisterInfo() != TRI) {
30 TRI = MF->getTarget().getRegisterInfo();
31 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
32 Update = true;
33 }
34
35 // Does this MF have different CSRs?
36 const unsigned *CSR = TRI->getCalleeSavedRegs(MF);
37 if (CSR != CalleeSaved) {
38 // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
39 // overlapping CSR.
40 CSRNum.reset(new uint8_t[TRI->getNumRegs()]);
41 for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
42 for (const unsigned *AS = TRI->getOverlaps(Reg);
43 unsigned Alias = *AS; ++AS)
44 CSRNum[Alias] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
45 Update = true;
46 }
47 CalleeSaved = CSR;
48
49 // Different reserved registers?
50 BitVector RR = TRI->getReservedRegs(*MF);
51 if (RR != Reserved)
52 Update = true;
53 Reserved = RR;
54
55 // Invalidate cached information from previous function.
56 if (Update)
57 ++Tag;
58 }
59
60 /// compute - Compute the preferred allocation order for RC with reserved
61 /// registers filtered out. Volatile registers come first followed by CSR
62 /// aliases ordered according to the CSR order specified by the target.
63 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
64 RCInfo &RCI = RegClass[RC->getID()];
65
66 // Raw register count, including all reserved regs.
67 unsigned NumRegs = RC->getNumRegs();
68
69 if (!RCI.Order)
70 RCI.Order.reset(new unsigned[NumRegs]);
71
72 unsigned N = 0;
73 SmallVector, 8> CSRAlias;
74
75 // FIXME: Once targets reserve registers instead of removing them from the
76 // allocation order, we can simply use begin/end here.
77 TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
78 TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
79
80 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
81 unsigned PhysReg = *I;
82 // Remove reserved registers from the allocation order.
83 if (Reserved.test(PhysReg))
84 continue;
85 if (unsigned CSR = CSRNum[PhysReg])
86 // PhysReg aliases a CSR, save it for later.
87 CSRAlias.push_back(std::make_pair(CSR, PhysReg));
88 else
89 RCI.Order[N++] = PhysReg;
90 }
91 RCI.NumRegs = N + CSRAlias.size();
92 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
93
94 // Sort CSR aliases acording to the CSR ordering.
95 if (CSRAlias.size() >= 2)
96 array_pod_sort(CSRAlias.begin(), CSRAlias.end());
97
98 for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i)
99 RCI.Order[N++] = CSRAlias[i].second;
100
101 // RCI is now up-to-date.
102 RCI.Tag = Tag;
103 }
104
0 //===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RegisterClassInfo class which provides dynamic
10 // information about target register classes. Callee saved and reserved
11 // registers depends on calling conventions and other dynamic information, so
12 // some things cannot be determined statically.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
17 #define LLVM_CODEGEN_REGISTERCLASSINFO_H
18
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/OwningPtr.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23
24 namespace llvm {
25
26 class RegisterClassInfo {
27 struct RCInfo {
28 unsigned Tag;
29 unsigned NumRegs;
30 OwningArrayPtr Order;
31
32 RCInfo() : Tag(0), NumRegs(0) {}
33 operator ArrayRef() const {
34 return ArrayRef(Order.get(), NumRegs);
35 }
36 };
37
38 // Brief cached information for each register class.
39 OwningArrayPtr RegClass;
40
41 // Tag changes whenever cached information needs to be recomputed. An RCInfo
42 // entry is valid when its tag matches.
43 unsigned Tag;
44
45 const MachineFunction *MF;
46 const TargetRegisterInfo *TRI;
47
48 // Callee saved registers of last MF. Assumed to be valid until the next
49 // runOnFunction() call.
50 const unsigned *CalleeSaved;
51
52 // Map register number to CalleeSaved index + 1;
53 OwningArrayPtr CSRNum;
54
55 // Reserved registers in the current MF.
56 BitVector Reserved;
57
58 // Compute all information about RC.
59 void compute(const TargetRegisterClass *RC) const;
60
61 // Return an up-to-date RCInfo for RC.
62 const RCInfo &get(const TargetRegisterClass *RC) const {
63 const RCInfo &RCI = RegClass[RC->getID()];
64 if (Tag != RCI.Tag)
65 compute(RC);
66 return RCI;
67 }
68
69 public:
70 RegisterClassInfo();
71
72 /// runOnFunction - Prepare to answer questions about MF. This must be called
73 /// before any other methods are used.
74 void runOnMachineFunction(const MachineFunction &MF);
75
76 /// getNumAllocatableRegs - Returns the number of actually allocatable
77 /// registers in RC in the current function.
78 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
79 return get(RC).NumRegs;
80 }
81
82 /// getOrder - Returns the preferred allocation order for RC. The order
83 /// contains no reserved registers, and registers that alias callee saved
84 /// registers come last.
85 ArrayRef getOrder(const TargetRegisterClass *RC) const {
86 return get(RC);
87 }
88
89 /// getLastCalleeSavedAlias - Returns the last callee saved register that
90 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
91 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
92 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
93 if (unsigned N = CSRNum[PhysReg])
94 return CalleeSaved[N-1];
95 return 0;
96 }
97 };
98 } // end namespace llvm
99
100 #endif
101
771771 // CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
772772 if (!CP.isPartial()) {
773773 const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg());
774 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
774 unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2;
775775 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
776776 if (Length > Threshold) {
777777 ++numAborts;
790790 const TargetRegisterClass *SrcRC,
791791 const TargetRegisterClass *DstRC,
792792 const TargetRegisterClass *NewRC) {
793 unsigned NewRCCount = allocatableRCRegs_[NewRC].count();
793 unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC);
794794 // This heuristics is good enough in practice, but it's obviously not *right*.
795795 // 4 is a magic number that works well enough for x86, ARM, etc. It filter
796796 // out all but the most restrictive register classes.
820820 unsigned NewUses = SrcUses + DstUses;
821821 unsigned NewSize = SrcSize + DstSize;
822822 if (SrcRC != NewRC && SrcSize > ThresSize) {
823 unsigned SrcRCCount = allocatableRCRegs_[SrcRC].count();
823 unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC);
824824 if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
825825 return false;
826826 }
827827 if (DstRC != NewRC && DstSize > ThresSize) {
828 unsigned DstRCCount = allocatableRCRegs_[DstRC].count();
828 unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC);
829829 if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
830830 return false;
831831 }
13991399 if (VerifyCoalescing)
14001400 mf_->verify(this, "Before register coalescing");
14011401
1402 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
1403 E = tri_->regclass_end(); I != E; ++I)
1404 allocatableRCRegs_.insert(std::make_pair(*I,
1405 tri_->getAllocatableSet(fn, *I)));
1402 RegClassInfo.runOnMachineFunction(fn);
14061403
14071404 // Join (coalesce) intervals if requested.
14081405 if (EnableJoining) {
1616 #include "llvm/CodeGen/MachineFunctionPass.h"
1717 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
1818 #include "llvm/CodeGen/RegisterCoalescer.h"
19 #include "llvm/ADT/BitVector.h"
19 #include "RegisterClassInfo.h"
2020
2121 namespace llvm {
2222 class SimpleRegisterCoalescing;
4646 LiveDebugVariables *ldv_;
4747 const MachineLoopInfo* loopInfo;
4848 AliasAnalysis *AA;
49
50 DenseMap allocatableRCRegs_;
49 RegisterClassInfo RegClassInfo;
5150
5251 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
5352 ///