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AMDGPU/GlobalISel: Fix ValueMapping tables for i1 This was incorrectly selecting SGPR for any i1 values, e.g. G_TRUNC to i1 from a VGPR was still an SGPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349715 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 10 months ago
3 changed file(s) with 98 addition(s) and 28 deletion(s). Raw diff Collapse all Expand all
1515
1616 enum PartialMappingIdx {
1717 None = - 1,
18 PM_SGPR1 = 0,
19 PM_SGPR16 = 4,
20 PM_SGPR32 = 5,
21 PM_SGPR64 = 6,
22 PM_SGPR128 = 7,
23 PM_SGPR256 = 8,
24 PM_SGPR512 = 9,
25 PM_VGPR1 = 10,
26 PM_VGPR16 = 14,
27 PM_VGPR32 = 15,
28 PM_VGPR64 = 16,
29 PM_VGPR128 = 17,
30 PM_VGPR256 = 18,
31 PM_VGPR512 = 19,
32 PM_SGPR96 = 20,
33 PM_VGPR96 = 21
18 PM_SGPR1 = 1,
19 PM_SGPR16 = 5,
20 PM_SGPR32 = 6,
21 PM_SGPR64 = 7,
22 PM_SGPR128 = 8,
23 PM_SGPR256 = 9,
24 PM_SGPR512 = 10,
25 PM_VGPR1 = 11,
26 PM_VGPR16 = 15,
27 PM_VGPR32 = 16,
28 PM_VGPR64 = 17,
29 PM_VGPR128 = 18,
30 PM_VGPR256 = 19,
31 PM_VGPR512 = 20,
32 PM_SGPR96 = 21,
33 PM_VGPR96 = 22
3434 };
3535
3636 const RegisterBankInfo::PartialMapping PartMappings[] {
3737 // StartIdx, Length, RegBank
3838 {0, 1, SCCRegBank},
39 {0, 1, SGPRRegBank}, // SGPR begin
3940 {0, 16, SGPRRegBank},
4041 {0, 32, SGPRRegBank},
4142 {0, 64, SGPRRegBank},
4243 {0, 128, SGPRRegBank},
4344 {0, 256, SGPRRegBank},
4445 {0, 512, SGPRRegBank},
45 {0, 1, SGPRRegBank},
46
47 {0, 1, VGPRRegBank}, // VGPR begin
4648 {0, 16, VGPRRegBank},
4749 {0, 32, VGPRRegBank},
4850 {0, 64, VGPRRegBank},
5456 };
5557
5658 const RegisterBankInfo::ValueMapping ValMappings[] {
59 // SCC
5760 {&PartMappings[0], 1},
61
62 // SGPRs
63 {&PartMappings[1], 1},
64 {nullptr, 0}, // Illegal power of 2 sizes
5865 {nullptr, 0},
5966 {nullptr, 0},
60 {nullptr, 0},
61 {&PartMappings[1], 1},
6267 {&PartMappings[2], 1},
6368 {&PartMappings[3], 1},
6469 {&PartMappings[4], 1},
6570 {&PartMappings[5], 1},
6671 {&PartMappings[6], 1},
6772 {&PartMappings[7], 1},
73
74 // VGPRs
75 {&PartMappings[8], 1},
6876 {nullptr, 0},
6977 {nullptr, 0},
7078 {nullptr, 0},
71 {&PartMappings[8], 1},
7279 {&PartMappings[9], 1},
7380 {&PartMappings[10], 1},
7481 {&PartMappings[11], 1},
7582 {&PartMappings[12], 1},
7683 {&PartMappings[13], 1},
7784 {&PartMappings[14], 1},
78 {&PartMappings[15], 1}
85 {&PartMappings[15], 1},
86 {&PartMappings[16], 1}
7987 };
8088
8189 enum ValueMappingIdx {
82 SGPRStartIdx = 0,
83 VGPRStartIdx = 10
90 SCCStartIdx = 0,
91 SGPRStartIdx = 1,
92 VGPRStartIdx = 11
8493 };
8594
8695 const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
8897 unsigned Idx;
8998 switch (Size) {
9099 case 1:
91 Idx = BankID == AMDGPU::SCCRegBankID ? PM_SGPR1 : PM_VGPR1;
100 if (BankID == AMDGPU::SCCRegBankID)
101 return &ValMappings[0];
102 Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;
92103 break;
93104 case 96:
94105 Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;
98109 Idx += Log2_32_Ceil(Size);
99110 break;
100111 }
112
113 assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length));
114 assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
115
101116 return &ValMappings[Idx];
102117 }
103118
474474 case AMDGPU::G_FCMP: {
475475 unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
476476 unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
477 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 1);
477 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1);
478478 OpdsMapping[1] = nullptr; // Predicate Operand.
479479 OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
480480 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
514514 unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
515515 unsigned Op0Bank = Op2Bank == AMDGPU::SGPRRegBankID &&
516516 Op3Bank == AMDGPU::SGPRRegBankID ?
517 AMDGPU::SCCRegBankID : AMDGPU::VGPRRegBankID;
517 AMDGPU::SCCRegBankID : AMDGPU::SGPRRegBankID;
518518 OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, 1);
519519 OpdsMapping[1] = nullptr; // Predicate Operand.
520520 OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
99 bb.0:
1010 liveins: $sgpr0_sgpr1
1111 ; CHECK-LABEL: name: trunc_i64_to_i32_s
12 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0
12 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
1313 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s32) = G_TRUNC [[COPY]](s64)
1414 %0:_(s64) = COPY $sgpr0_sgpr1
1515 %1:_(s32) = G_TRUNC %0
2323 bb.0:
2424 liveins: $vgpr0_vgpr1
2525 ; CHECK-LABEL: name: trunc_i64_to_i32_v
26 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0
26 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
2727 ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s32) = G_TRUNC [[COPY]](s64)
2828 %0:_(s64) = COPY $vgpr0_vgpr1
2929 %1:_(s32) = G_TRUNC %0
3030 ...
31 ---
32 name: trunc_i64_to_i1_s
33 legalized: true
34
35 body: |
36 bb.0:
37 liveins: $sgpr0_sgpr1
38 ; CHECK-LABEL: name: trunc_i64_to_i1_s
39 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
40 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s64)
41 %0:_(s64) = COPY $sgpr0_sgpr1
42 %1:_(s1) = G_TRUNC %0
43 ...
44
45 ---
46 name: trunc_i64_to_i1_v
47 legalized: true
48
49 body: |
50 bb.0:
51 liveins: $vgpr0_vgpr1
52 ; CHECK-LABEL: name: trunc_i64_to_i1_v
53 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
54 ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s64)
55 %0:_(s64) = COPY $vgpr0_vgpr1
56 %1:_(s1) = G_TRUNC %0
57 ...
58
59 ---
60 name: trunc_i32_to_i1_s
61 legalized: true
62
63 body: |
64 bb.0:
65 liveins: $sgpr0
66 ; CHECK-LABEL: name: trunc_i32_to_i1_s
67 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
68 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
69 %0:_(s32) = COPY $sgpr0
70 %1:_(s1) = G_TRUNC %0
71 ...
72
73 ---
74 name: trunc_i32_to_i1_v
75 legalized: true
76
77 body: |
78 bb.0:
79 liveins: $vgpr0
80 ; CHECK-LABEL: name: trunc_i32_to_i1_v
81 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
82 ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
83 %0:_(s32) = COPY $vgpr0
84 %1:_(s1) = G_TRUNC %0
85 ...